CA2182382C - Multi-channel digital transceiver and method - Google Patents

Abstract

A multi-channel digital transceiver (400) receives uplink radio frequency signals and converts these signals to digital intermediate frequency signals. Digital signal processing, including a digital converter module (426), is employed to select digital intermediate frequency signals received at a plurality of antennas (412) and to convert these signals to baseband signals. The baseband signals are processed to recover a communication channel therefrom. Downlink baseband signals are also processed and digital signal processing within the digital converter module (426) up converts and modulates the downlink baseband signals to digital intermediate frequency signals. The digital intermediate frequency signals are converted to analog radio frequency signals, amplified and radiated from transmit antennas (420).

Description

WO 96/21288 X 1 8 2 3 ~ 2 PCT/US95/17117 MULTI-CHANNEL DIGITAL TRANSCEIVER AND
METHOD
Field of the Invention S The present invention relates to co"""~ systems. and more particularly, to multi-channel digital ~ ",;~ , receivers and Llculsc~h~ for use in cu~ ;r~ systems.
Background of the Invention T,~."~",iit~ .:i and receivers for comml~ni~tion systems generally are designed such that they are tuned to transmit and receive one of a mllltiplirity of signals having widely va~ying bandwidths and which may fall within a particular rl~ u~ y range.
It will be appreciated by those skilled in the art that these 1~ Ll,.,l~ tl .~. and receivers radiate or intercept, I.,~AUe~ Y, cl~Lll.",;~n~tir radiation within a desired frequency band. The ~le~,L~ I;r radiation can be output from or input to the LldllsllliLL~I or receiver, respectively, by several types of devices including an antenna, a wave euide, a coaxial cable and an optical 20 fiber.
These commllni~tion system ll,.ll~lllil,~.l~ and receivers may be capable of Ll,.ll~lllill;ll~ and receiving a mllltirli~ity ûf sienals;
hûwever, such Ll~ul~llliL~ and receivers generally utilize circuitry which is duplicated for each l~ ,Liv~ signal to be tr~n~mittPd or 25 received which has a different frequency or bandwidth. This circuitry duplication is not an optimal multi-channel comml~nic~tior unit design architecture, because of the added cost and complexity :~ccori~t~d with building cûmplete intll~p~.n-llont LI~ II;IIr~ and/or . receivers for each comml-ni~tion channel.

21823~

An alternative t~ rl and receiver ~ iL~,-,Lult~ is possible which would be capable of L~ il.v and receiving signals having a desired multi-channel wide bandwidth. This alternative ~ u~ iLLt and receiver may utilize a digitizer (e.g., an analog-to-digital S converter) which operates at a sl~fficiPntly high sampling rate to ensure that the signal of the desired bandwidth can be digitized in acc~-~Lu-c~ with the Nyquist criteria (e.g., digitizing at a sampling rate equal to at least twice the bandwidth to be digitized).
~llhsPqllPntly7 the digitized signal preferably is pre- or post-processed using digital si~nal processing tPrhniqllP5 to dirrt-~.-Li~Le between the multiple channels within the digitized bandwidth.
With reference to FIG. 1, a prior wideband Ll~lsc~hv~" 100 is shown. Radio fi-,~.,.-~;y (RF) signals are received at antenna 102 processed through RF converter 104 and digitized by analog-to-digital converter 106 The digitized signals are processed through a discrete fourier transform (DFT) 108, a channel processor 110 and from the channel ~lv~ei~svlb 110 to a cellular network and a public switched telephone network (PSTN). In a transmit mode, signals received from the cellular network are processed through channel processors 110, inverse discrete fourier transform (IDFT) 114 and digital-to-analog converter 116. Analog signals from the digital-to-analog converter 116 are then up converted in RF up converter 118 and radiated from antenna 120.
A disadvantage of this alternative type of c~mmllnir~tion unit is that the digital processing portion of the cl mm~lni~tion unit must have a sllfficiPntly high sampling rate to ensure that the Nyquist criteria is met for the ~,,,.x;,,,,,,,, bandwidth of the received cle.,ùu...agnetic radiation which is equal to the sum of the individual c~-mmllnic~ti~-n channels which form the composite received 30 clc~LIu..lagnetic radiation bandwidth. If the composite bandwidth signal is s--ffi~i~ntly wide, the digital plUC~bbillg portion of the 2 ~ 8 ~ 3 8 2 P~ I7 ..
cnmm--nic~tion unit may be very costly and may consume a c~nci~lPr~hlP~ amount of power. ~ ition~ y, the channels p}oduced by a DFT or IDFT filtering technique must typically be adjacent to each other.
A need exists for a ~ and a receiver, like the one which is described above, which is capable of ll.1ll~lll;li;ll,., and receiving a mllltirlit~ity of signals within cc,~ u,.ding channels with the same Lldll~llli~t11 or receiver circuitry. However, this ll~ul~lllilL~,l and receiver circuitry preferably should reduce c~mm~ni~til rl unit design u~ cgor;~tpd with the above Llallsi~;vt;l duul~il.,.,lul~. If such a l,dl,~...;llr, and receiver it~ UI~; could be developed, then it would be ideally suited fo}
cellular ra~liotfl~ ~)h~ r C~ ;nn systems. Cellular base stations typically need to transmit and receive multiple channels within a wide frequency bandwidth (e.g., 824 Illcgall~ , to 894 megahertz). In addition, cullull.,l-,ial pressures on cellular infrastructure and ~UI,s, lil,~ uiylll~,llt m~nllf~tllrers are prompting these ~ - r~ U,I~ to find ways to reduce the cost of C-)l l- lllll;~ ~I;on units. Similarly, such a multi-channel lli.l.clll;lt,..
20 and receiver architecture would be well suited for personal cl)mm~ni~tion systems (PCS) which will have smaller service regions (than their ~,OUlll~ ~l cellular service re~ions) for each base station and as such a coll~auul.ding larger number of base stations will be required to cover a given geographic region.
25 Operators which purchase base stations ideally would like to have a less complex and reduced cost unit to install throughout their licensed service regions.
An Atl~iti~m~l advantage may be ~ained by cellular and PCS
m~nllf~ ~llrers as the result of designing multi-channel 30 c- mml-rli~ti~-n units which share the same analog signal processing portion. Traditional c~mmllni~tion units are desicned to operate 38~

under a single information signal coding and ~ ,. .f ~ if m standard.
In contrast, these multi-channel C~)llllllllllif 'l;llll units include a di~italsignal processing portion which may be l~lu~l,..llll.rfl at will, through software during the m~mlf:lrtllrin~ process or in the field S after inctsl~ tir~n such that these multi-channel comm--nir~tion units may operate in ac~o-dd-.ce with any one of several information signal coding and ~ fl;,~l;r~n standards.
The many advantages and features of the present invention will be d~ .,;dt~d from the following detailed description of several 10 preferred embodiments of the invention with reference to the attached drawings in which:
Brief Description of the Drawings FIG. 1 is a block diagram of a prior art multi-channel Lldll5Cci~
FIG. 2 is a block diagram l-,~ .l jfm of a multi-channel receiver in accb..l~.lce with a preferred embodiment of the present invention;
E~I&. 3 is a block diagram l"~!~. S~ l if m of a multi-channel l,,."~",;ll,, in accu-dd..~c with preferred embodiment of the present invention;
FIG. 4 is a block diagram Ic~lcsGlllation of a multi-channel l1~ISCC;~.~,I in accul.ldl~ce with a preferred embodiment of the 25 present invention;
FIG. 5 is a block diagram l~ cll~dlion of the multi-channel receiver shown in FIG. 2 and modified to provide per-channel scanning in accu--l~..ce with another preferred embodiment of the present invention;

~ WO ~6/21288 2 ~ 8 2 3 8 ~ P~ s l /117 ,;
, FIG. 6 is a block diagram ~ lLaLion of a multi-channel transceiver in accul.l~llc~ with another preferred embodiment of the present invention;
EiIG. 7 is a block diagram 1~ n of a multi-channel 5 transceiver in accol~ c with another preferred embodiment of the present i~ Liull;
FIG. 8 is a block diagram ~ s.l ion of data routing in a multi-channel Llall~ l in acculd~l~G with a preferred embodiment of the present invention;
FIG. 9 is a block diagram ~ I;nn of data routing in a multi-channel ll~ c~;vel in acGvl~..ce with another preferred embodiment of the present invention;
FIG. 10 is a block diagram l~ lll of data routing in a multi-channel Ll~ulsc~ih,~,l in acculd~l.cè with another preferred 15 embodiment of the present ill~,llLioll;
FIG. 11 is a block diagram l~ inn of a digital converter module for the multi-channel tl.~ of FIG. 5 and further in acculdall, ~ with a preferred embodiment of the present invention;
FIG. 12 is a block diagram l~ l;nn of a preferred 20 embodiment of a digital down converter in accu.~l-,c with the present invention;
F~G. 13 is a block diagram l~ cr.~l~l;nn of a preferred embodiment of a digit~l up converter in acco-uallce with the present invention;
FIG. 14 is a block diagram ~ s-,llLd~ion of an up converter adaptable to the digital up converter of the present invention;
~IG. 15 is a block diagram l~ s~ ;nn of a mofl~ or adaptable to the digital up converter of the present invention;

W0 96/21288 r~ 7 ~

FIG. 16 is a block diagram l~r~ of a preferred embodiment up collvclL~,./Il-odulator for the digital up converter of the present invention;
FIG. 17 is a block diagram IC~I~S` .,I~;nn of a preferred 5 embodiment of a channel processor card in accol.lal~cc with the present invention;
FIG. 18 is a block diagram l~r~ca~ aLion of another preferred ~Illbodill.~.lL of a channel ~JIUUGaaVI card in accol~l-,c with the present invention; and FIG 19 is a flowchart ~ ctr~tin~ a scan ~luce1ulc in acc~ldalll~e with a preferred fmho~lim~nt ûf the present invention.
Detailed Description of a Preferred Embodiment The present invention is directed to a wideband multi-channel Lldllallli~ and receiver (Llalls~ v.,l) which il~l,Ol~JvlaL~s a high degree of flexibility and l~lulldalll"y and which is particularly adaptable to the cellular or PCS cc.. -;- AI;c)n systems. The Llallac~ ,. provides support for multiple antennas for either 20 sectnri7~d cellular operation, diversity reception, redundancy or as preferred, a combination of all of these features with enhanced user - capacity at reduced cost. The LlallaCcivcl of the present invention ~cu..,~ l.f c these and many other features through a practical architecture which enhances pcl~llllalll c through illcc~l~ulalion of ~5 s~lhst~nti~l digital ~ucesai,,g and dynamic fqllirmfnt sharing (DES).
With reference to FIG. 4, a Llallscc;vcl 400 according to a preferred embodiment of the present invention is shown. For ease Of ~1ic~-llccic~n, preferred embodiments of wideband multi-channel digital receiver and llallalllillcl portions, 200 and 300, l~a~ulhl~ly, 30 of transceiver 400 are tliCCUccf~ Furthermore, to presen~ a WO 96/21288 æ ~ 8 ~ 3 8 2 PCTlUS9!il17117 preferred i",~ .". .";.lion of the present invention, a transceiver operable in the cellular radio frequency (RF) band is presented. It should be understood, however, that ~e present invention may be easily adapted to service any RF ct)mmllnir~tinn band inrlll~lin~, for 5 example, the PCS and the like bands.
With reference then to FIG. 2, a wideband multi-channel digital receiver portion (receiver) 200 in a,_co~ lce with a preferred embodiment of the present invention is shown. The receiver 200 includes a plurality of antennas 202 (individually antennas 1,3,...,n-10 1) which are coupled, l~ec~ ,ly, to a plurality of radio-frequency rnixers 204 for Cullv~lLillg RF signals received at antennas 202 to illlrl ",F.l;~lr r~ u~ ,y (IF) signals. It should be ~ d that the mixers 204 contain the a~lu~liaL~ signal processing elements at least including filters, amplifiers, and oscillators for pre-15 conditioning the received RF signals, isolating the particular RF bandof interest and mixing the RF signals to the desired IF signals.
The IF signals are then commllnir~tFd to a plurality of analog-to-digital cull~lt~ (ADCs) 210 where the entire band of interest is digitized. One past ~is~d~ ~ulL~ge of prior wideband receivers was the 20 It~luil~,lll~llL that the ADC, to completely and accurately digitize the entire band, operate at a very high sarnpling rate. For example~ the cellular A and B bands occupy 25 lllc~,lll.,lL~ (MHz) of RF spectrum.
In ac!_oldallce with the well known Nyquist criteria~ to accurately digitize the entire cellular bands with a single ADC would require a 25 device capable of operating at a sampling rate of more than 50 MHz (or 50 million samples per second~ 50 Ms/s). Such devices are becoming more common and it is rontFmrl~tFd within the scope of - the present invention to utilize the latest ADC technology. The ADCs 210 digitize the IF signals thereby producing digital signals.
30 These digital signals are then ~ ;r, lrd to digital down CUII~.,lL~l~ (DDCs) 214.

3~

The DDC 214 of the preferred emho~iimPnt seen more clearly in FIG. 12, ineludes a switeh 1216 whieh allows DDC 214 to seleet I~ signals from any one of the plurality of antennas 202. Based on the state of switeh 1216, the DDC 214 aecepts a high speed stream of 5 di~ital words (e.g. approximately 60 MHz) from the ADC 210 a~soci~t~,~ with the selected antenna, in the preferred embodiment via a b~rk~ r i~ ,ululeul 1108, EiIG. 11. The DDC 214 is operable to select a particular rl~u.,ll-,y (in the digital domain), to provide decimation (rate reduetion) and to filter the signal to a bandwidth 10 ~ccori~tr~d with channels of the erlmmllnir ~tir)n system. With particular reference to FIG. 12, each DDC 214 contains a n-lmPrir~lly controlled oscillator (NCO) 1218 and a eomplex mllltirlit~r 1220 to perform a down e.,ll~ iol~ on the digital word stream. Note, this is a seeond down eonversion since a first down 15 eonYersion was performed on the reeeived analog signal by mixers 204. The result of the down conversion and complex multiplication is a data stream in yuaL~lul~, i.e., having in-phase, I, and ~luadl~Lulc~, Q, Culllpoll~ , whieh has been speetrally translated to a center r ~ u~ .y of zero hertz (baseband or zero IF). The I,Q
20 c.)~ lr.,l~ of the data stream are cr.""""..;~ t d to a pair of decimation filters 1222, IC~C-;Liv~ly to reduee the bandwidth and the data rate to a suitable rate for the partieular cr mm~mir~tion system air interfaee (eommon air interfaee or CAI) being proeessed. In the preferred embodiment, the data rate output of the decimation filters 25 is about 2.5 times the desired bandwidth of the CAI It should be understood that the desired bandwidth may ehange the preferred decimation filters 1222 output rate. The t1~-rim~trd data stream is then low pass filtered to remove any undesirable alias colllpc through digital filters 1224. Deeimation filters 1222 and digital 30 filters 1224 provide rough seleetivity, final sclc~,Livily is aeeomplished within the ehannel processors 228 in a known manner.

WO 96/21288 21~ 2 3 8 2 PCTIUS95117117 =

Observed in FIG. 2, a plurality of DDCs 214 are provided in the preferred embodiment and each are i~ rd to ADCs 210.
- Each of the DDCs 214 can select one of the plurality of ADCs 210/allLGIlllas 202 from which to receive a high speed dicital word stream via b~rkpl~nr 1106. The outputs of the DDCs 214, a low speed data stream (e.g. ~IllU~illl.lt~ly 10 MHz, baseband signal), are c-mnrct-od to a time domain multiplex (TDM) bus 226 for commllnir:lti--n to a plurality of channel processors 228 via output formatter 1232. By placing the outputs of the DDCs on TDM bus 226, it is possible to have any one of the channel ~IUCCG~ 228 select any one of the DDCs 214 for receiving a baseband signal. In the event of a failure of a channel ~IUCcssul 228 o} a DDC 214, the channel ~)lU~,GSSCII:~ 228 would be operable, via the control bus 224 and control bus interface 1234, to ill~l-;ulllle~,~ available channel 15 IJlUCGi~Ul~ to available DDCs with a~ Le contention/arbitration ~IUCGi~illg to prevent two channel processors from attempting to access the same DDC. In the preferred embodiment, however, the DDCs 214 are allocated a dedicated time slot on TDM bus 226 for illt~ )",lf~l;on to a particular channel processor 228.
The channel processors 228 are operable to send control sionals via the control bus 224 to the DDCs 214 for setting digital word stream processing p~ll.,t~ . That is, the channel processors 228 can instruct the DDCs 214 to select a down conversion frequency, a ~i~rim~ti~m rate and filter l.ll,..,l~.lr~ r~ (e.g., bandwidth shape, etc.) 25 for processing the digital data streams. It is understood that the NCO 1218, complex mllltiplifr 1220, decimator 1222 and digital filter 1224 are lGs~ iv~ to mlmfrir~l control to modify the signal processing r~r~mrtPrS. This allows receiver 200 to receive c~mmllni~tion signals Cull~ullllillg to a number of different air - 30 interface standards.

W0 96/21288 r~ 117 --2l~2382 With contin~lPd reference to FIG. 2, the receiYer of the present invention further provides a plurality of receiver banks (two shown and illustrated as 230 and 230'). Each of the receiver banks 230 and 230' inc~ude the elements described above prior to TDM bus 226 for 5 receiving and processing a radio frequency signal. In order to provide diversity reception with the present invention, a pair of adjacent antennas, one from antennas 202 and one from antennas 202' (individually ler~le~ d as 2,4,..., n), each slcsori~t~d with receiver banks 230 and 230', Le~ee~ively~ are ~lPsi~n~tPd to service a 10 sector of the commllni~tion system. The signals received at each antenna 202 arld 202' are processed intlP.pPnrlPntly through receiver banks 230 and 230', l~,O~e~ ,ly. The outputs of the receiver banks 230 and 230' are cu,.,."~.;. ,.t. d l~,Oy.,llively on TDM buses 226 and 226', although it is understood that a single bus may be used, to the 15 channel processors 228, wherein the diversity reception is The channel ylueeooulo 228 receive the baseband signals and perform the required baseband signal processing, selectivity to recover commllnic~ticm channels. This processing at least includes 20 audio filtering in analog CAI comml~nir:-tion systems, forward error correction in digital CAI cnmmllnir~titm systems, and receive signal strength inflir~ticm (RSSI) in all commllniC~tion systems. Each channel processor 228 recovers traffic channels in~lPpPn-lPntly.
Furthermore, to provide diversity, each channel processor 228 is 25 operable to listen to each of the pair of antennas assigned to a sector and to thereby receive and process two baseband signals, one per antenna. The channel processors 228 are further provided an interface 436, I;IG. 4, to the communication network, for example in a cellular commllnir~tion system to a base station controller or 30 mobile switching center, via a suitable illLel~;ollll~

WO 96121288 ~ 3. 8 2 3 8 2 P~1lU~ 7 ,`, : .

With reference to FIG. 17 a preferred embodiment of a channel ucc~sol 228 is shown. As will be ~l~srrih~ each of the channel ~IUe~55Vlb iS operable for both transmit and receive operations. In the preferred embodiment, each channel ~IUCGs~ul 228 is capable of 5 servicing up to 8 comm~mir~ti-ln channels of the c~mmllnir~tion system in both transmit and receive (4 channels in receive mode with diversity). The low speed baseband signal from ~DM buses 226 or 226' are received l~ eLively at input/output (VO) ports 1740 and 1740' and are comm--nir~tPd to a pair of ~IUCC ,bulb 1742 and 1742'.
ACcori~tPd with each ~IU~Ci,~ul 1742 and 1742', are digital signal ~IU~C~bolb (DSPs) 1744 and 1744' and memory 1746 and 1746'.
Each processor 1742 and 1742' is operable to service four (4) cnmm--nir~tirn channels. As can be seen in FIG. 17, in a preferred l ."ho-l;..-l ..l the l~lU~,Gi~bUlb 1742 amd 1742' are configured to listen 15 to either one, or both as is required in the preferred diversity arr~n~m~nt of the receiver banks 230 or 230'. This structure, while also enabling diversity, provides redundancy. In the receive mode if one of the processors 1742 or 1742' fails, only diversity is lost as the other ~IUCG~ 1742 or 1742' is still available to process 20 the uplink baseband signals from the other receiver bank. It should be d~ Led that ~Iu~ aulb 1742 and 1742' can be imrlPmrntPd with a~J~Iu~ G diversity selection or diversity combining processing capability. Processors 1742 and 1742' are further in commllnir~ion with control elements 1748 and 1748', I~ e-,~ivGly, 25 for processing and cu,~,.;~ ,.l;,.~ control information to the DDCs 214 via VO ports 1740 and 1740' and the control bus 224 as ~iPsrrihe~
With co~tinlll~d reference to FIG. 17 and reference to FIG. 4, the Llall~llliLLGl portion 300 (LldllbllliLl~l) of transceive} 400 will be - 30 described. In a transmit mode, the channel ~luce~bul~ 228 receive downlink commllnic~tion signals from the c~ mm~nir~tion system WO 96121288 ' ' PCT/US95/17117 network (via interface 436 not shown in FIG. 17) for comml-nir~tjon over a crmmllnir~tion channel. These downlink signals can be, for example, control or signaling information intended for the entire cell (e.g., a page message) or a particular sector of a cell (e.g., a handoff 5 command) or downlink voice arld/or data (e.g., a traffic channel) Within channel ~luCc;.,~VI~ 228, processors 1742 and 1742' intlrp~ontll~ntly operate on the downlink signals to generate low speed baseband signals. In transmit mode, the channel plvce~sol~ 228 are capable of servicing eight (8) commllnir~ti~n channels (eithe} traffic 10 channels, signaling channels or a cu-l-billd~ion thereof). If one of the processors 1742 or 1742' fails, the effect on the system is a loss of capacity, but not a loss of an entire sector or cell. Moreover, removing one of the plurality of chaMel ~ IV~,Ci,~vl~ 228 from the commllnir~tion system results in the loss of only eight channels.
The lulu~ aillg of the baseband signals through the lld~
300 is c~ ."~ ,y to the ~"vc~ i"g comrl~t~d in the receive}
200. The low speed baseband signals are cv"", ~ cl frvm the channel ~,vcessv,~ 228 via I/O ports 1740 or 1740' to TDM
downlink busses 300 and 300', although a single bus may be used, 20 -dnd from there to a plurality of digital up uv~ .t~ (DUCs) 30~.
The DUCs 302 interpolate the baseband signals to a suitable data rate. The interpolation is required so that all baseband signals from the channel processors 228 are at the same rate allowing for summing the baseband signals at a central location. The interpolated 25 baseband signals are then up converted to an d~,ulupiia~ IF signal such as quadrature phase shift keying (QPSK) dir~,~"~ial quadrature phase shift keying (DQPSK), r~ u~ y modulation (FM) or ~mplitll~lP modulation (AM) signals (with I,Q input, the modulation is accomplished within the channel processors 228). The baseband 30 signals are now carrier m- fhll~t~d high speed baseband data signals offset from zero hertz. The amount of offset is controlled by the ~ WO96/21288 2~,.82382 PCr/US9~117117 ;ll~ of the DUCs 302. The modlllAtPd baseband signals are comm~ni~At~d on a high speed bA~ k~ ,r illt~ C~ 304 to signal selectors 306. The signal selectors are operable to select sub-groups of the mnrllll~ted baseband signals. The selected sub-groups are comm~ni~ -Atinn channels which are to be LIA"~",ilt~ ~ within a particular sector of the ~lllllllllll;- A~ system. The selected sub-group of mr)dlllAtPd baseband signals are then CVIIIIII~ .At~ d to digital summers 308 and summed. The summed signals, still at high speed, are then co"""""i~ 1 via b~rkl l~nP illt~"-,ulll.~;L 1130 to digital-to-analog ~,OIIV~ (DACs) 310 and are ,ull~ d to IF
analog signals. These IF analog signals are then up converted by up Cull\~ 314 to RF signals, amplified by A~nrlifiPr.c 418 (FIG. 4) and radiated from antennas 420 (F~G. 4).
In the preferred cllll)ûdilll~ , to once again provide enhanced system reliability, a plurality of DACs 310 are provided with groups 311 of three DACs being arrarlged on RF shelves, one DAC
Acco~iAtPd with a shelf. The groups of DACs 311 convert three summed signals, received on separate signal busses 313 of bArkrl~nP
ill~t;l~;OllllC-,~ 1130, to analog signals. This provides for increased dynamic range over what could be achieved with a single DAC. This arr-An~emPnt further provides redundancy since if any of the DACs fail, there are others available. The result is merely a decrease in system capacity and not a loss of an entire sector or cell. The outputs of a group of DACs 311 receiving signals for a sector of the c~-mmlmi~-Ation system are then analog summed in summers 312, with the summed analog signal being commllni~-AtPd to up converters 314.
Similar to the receiver 200, the Lldll~ el 300 is also arranged with a plurality of ~Idll~ l banks (two shown as 330 and 330').
The ~Idll: llli~L~I banks 330 and 330' include all of the ~ for the ~ ",illrl 300 between the channel processors 228 and the WO 96121288 PCTIUS9~;/17117 21 82~2 amplifiers 418. The output of the up converters 314, up converting summed analog signals for a sector of the comml-nic~tion system, for each ll~LII`t~ bank 330 and 330' are then summed in RF summers 316 The summed RF signals are then c.."""",.;. ~ d to amplifiers 418 and radiated on antennas 420~ If an entire L~ bank 330 or 330' fails, the effect is still only a loss of system capacity and not a loss of arl entire portion of the cnmmllnir~tinn system.
With reference to FIG. 13 a DUC 302 irl acc~,ld~l-,e with a preferred embodirnent of the present invention is shown. In the preferred embodiment, there is provided a plurality of DUCs 302 each of which includes an up c~ /ll.odulator 1340 which receives downlink baseband signals from busses 300 and 300' and control signals from control bus 224 via formater circuits 1341.
The output of the up ~ m1~ tnr 1340 is then comm-~nic~t~d to selector 306. In the preferred embodiment, selector 306 can take the form of ~anks of dual-input AND gates, one input of which is connected to one bit of the data word (i.e. the moA~ t~d baseband signal). With the control line held high (logical 1), the outputs will follow the tr~ncitinnc of the inputs. The output of selector 306 is then comml-nir:lt~d to a digital summer bank 1308, which adds data from previous digital summers associated with other DUCs onto one of a plurality of signal paths 313. Each signal path, as intlir~t~tl is associated with a sector of the cr.mmllnir~tinn system and c~l"ll"l"i~ .lrs the summed signals to DAC groups 311. If selector 306 is open, the output of selector 306 is zeros, and as an input to summer 1308 leaves the incoming signal unchanged. It should also be understood that scaling may be required on the input, the output or both of summers 1308 for scaling the summed digital signal within the dynamic range of the sumrners 1308. In this manner, the outputs of the DUCs, I~ illg signals destined for particular sectors of the c~mmlmir~tiorl system can be summed into a WO 96121~88 ~ ~ 8 ~ 3 ~ 2 PCTIUS95/17117 . .

single signal for conversion to an analog signal. O}, as is ~rcomrli~hPd in the preferred embodiment, may be further collected in sets and converted to ana!og signals by multiple DACs for Pnh~nrin~ the dynamic range and providing redundancy.
With reference to F~G. 14, an up converter 1400 for I,Q
mrri~ tion in a~co~ ce with the present invention is shown. The up converter 1400 includes first and second il~ oldlion filters 1402 and 1404 (e.g., finite impulse response (FIR) filters) for interpolating the I,Q portions of the baseband signal, ~ c~ ,ly.
The interpolated l,Q portions of the baseband signal are up converted in mixers 1406 and 1408, receiving input from nllmPri~ ~lly controlled oscillator 1410. Numerically controlled oscillator (NCO) 1410 receives as an input the product of the up conversion frequency, (oO~ and the inverse sample rate, ~, which is a fixed phase ill~ on the up conversion frequency.
This product is supplied to a phase ~rcllmlll~tr,r 1412 within NCO
1410. The output of phase ~rc--m--l~tr)r 1412 is a sample phase, ~), which is crlmm--nir~tPd to sine and cosine ~II.,Idl~ 1414 and 1416, iV~Iy, for ~,.l."aLillg the up c~ ,vl- signals. The up converted I,Q portions of the baseband signal are then summed in summer 1418 providing the mo~ tPd IF signal output of up converter 1400.
In FIG. 15, a m-)dlll~tor 1500 for R,~3 modulation, direct mr,~illl~tion of the phase, is shown. Modulator 1500 provides a ~imrlificd way of ~enerating FM over up converter 1400. The baseband signal is commllnir~tPd to interpolation filter 1502( e.g., and FIR filter) which is then scaled by k~ in scaler 1504. The interpolated and scaled baseband signai is then summed in summer 1506 with the fixed phase ill~ ~o~ in a nllmPrir~ controlled oscillator/modulator (NCOM) 1508. This sum is then commllnir~tPd to a phase rrcl~mlll~tr,r 1510 which outputs a sample phas~, ~, which W0 96/21288 - r~ 7 ~823~Z

in turn is cr,mml-nic~t~d to a sinusoid generator 1512 for generating the m~ t~d IF signal output of motl-ll^~ lr 1500.
The devices shown in FlGs. 14 and 15 are suitable for use in up converter/modulator 1340 of the present invention. However, the up converter 1400 is not efficient with respect to generating FM, while m~dlll~tnr 1500 does not provide I,Q up conversion. In FIG. 16, a preferred up c~ .t~/lllo-lulator 1340 is shown which provides botb I,Q up conversion and FM modulation. Interpolator/modulator 1340 provides I,Q up Cull~ iOll for a single baseband signal or R.~3 mo~llll~ti~n for two baseband signals.
The I,Q portions of the baseband signal or two R,~ signals are input to up c~llv~lL~ .ot1l~ r 1340 at ports 1602 arld 1604, c.,Li~.,ly. Signal selectors 1606 and 1608 are provided and select between the I,Q or R,~3 signals based upon the mode of operation of up ~ ".L~ tr,r 1340.
With respect to processing of an ~,Q signal, the r portion of the signal is co~ """:r~trd from selector 1606 to illL~ OIaLiOn filter, (e.g., an FIR filter) 1610. The interpolated I signal is then c--mml]ni~slt~d to mixer 1612 where it is up converted by a sinusoid from cosine generator 1614. Cosine generator 1614 receives an input sample phase ~ from phase ~rCIlmlll~t~r 1616. A selector 1618 is provided and selects a zero input for I,Q up conversion. The ~~ ~ ~~` - -output of selector 1618 is scaled by k~ in scaler 1620 yielding a zero output which is added to (Dol in adder 162'2. This sum, which is ~O~ in the l,Q up conversion case, is input to phase ~ccl~m~ tr~r 1616 to produce the sample phase output, ~.
Processing of the Q portion of the signal is similar. The Q
signal is selected by selector 1608 and commllnir~lt~d to interpolation filter ~e.g., an FIR filter) 1626. The interpolated Q signal is then commllnir~t~d to mixer 1628 where it is up converted by a sinusoid from sine generator 1630. Sine generator 1630 receives an input wog6nl288 ~823~2 P~l/u~ 3l~ll7 ~ , . .
.

from selector 1632 which selects the sample phase, ~, generated by phase Ar, ~ 1616 in the I,Q case. The up converted I,Q
signals are then summed in summer 1634 as the up converted/modulated output of up Cull~Gll~./lllo~1~llAtrlr 1340 in the 5 I,Q mode.
In R,~3 processing, the selectors 1606 and 1608 select two separate R,~3 signals. For R,~) processing, up cu~ .t~ lo.lulator 340 is operable to process two R,~3 signals ~imllltAn~.ously. The first signal, R,~3-l is interpolated and filtered in interpolation filter 1610.
In the R,~ case, selector 1618 selects the interpolated R,~3-1 signal which is scaled by k~ in scaler 1620 and added to ~ol in adder 1622.
The output of adder 1622 is then c-~".",~";. . ~ d to phase ArcllmlllAf~r 1616 which produces a sample phase, ~P which is input to cosine generator 1614. The output of cosine generator 1614 is 15 one of two m~ llAtPd IF signal outputs of up CullvGI~./,t)tl--lAs-lr 1340 in R,~3 processing mode.
The second R,~3 signal, R,13-2, is selected by selector 1608 and is cllmmllnirAf~d to interpolation filter 1626. The interpolated R.H-2 signal is then comm--nirAtr.d to scaler 1636 where it is scaled by k~.
The scaled signal is then summed with ~O~ in adder 1638. The output of adder 1638 is input to phase ArCllmlll~tr)r 1640 which produces an output sample phase, ~ which is selected by selector 1632 and comm~nif At~d to sine generator 1630. The output of sine generator 1630 is the second of two m~rllllAf~d IF signal outputs of -up cUIl~.,.~./~.o,l~lAt~ r 1340 in R,~3 processing mode.
Having now described separately the receiver 200 and transmitter 300 portions of LldllsCGiVGI 400, Ll~lscGivGI 400 will be ~ crrihed in more detail with reference to FIG. 4. Tldlls~ei.~. 400 is structured in a pair of transceiver banks 402 and 404. Each bank is identical and includes a plurality of RF processing shelves 406.
Each RF processing shelf 406 houses a RF mixer 408 and an ADC

WO 96/~1288 ~ 3 ~ ~ PCTIUS9~117117 410 which are coupled to receive and digitize a signal from antenna 412. RF processing shelf 406 further includes three ~ACs 414, the c)utputs of which are summed by summer 416 arld comm~ni~tfd to RF up converter 418. The output of RF up converter 417 is further 5 cnmm--ni~:ltPd to an RF summer 419 for summing with a u U~ v-lding output from Ll~lsc~;~.,. bank 404. The surnmed RF
signal is then c~...,,,,,,..;~-l. d to amplifier 418 where it is amplifled before being radiated from arlterma 420.
Received signals from ADC 410 are illL~ d to a 10 plurality of digital converter modules (DCMs) 426 via receive busses 428. Similarly, transmit signals are cc .,....~ =- t~ d from DCMs 426 to DACs 414 via transmit busses 430. As will be appreciated, receive busses 428 and transmit busses 430 are high spee~ data buses i..,l)l; ., ~ ..t~ d into a b~ krl~nP ~,llit~ ul~ within the RF frame 432.
15 In the preferred ~Illbodil.~.lL, c~-mmllnic~tion over the b~rk~l~nP is at dL~IJIu~dlll~ly 60 MHz, however, the close physical relationship of the elements allows for such high speed C.~)ll,,,,,..,;. ,.~ioll without nifir~nt errors in the high speed data signal.
With reference to FIG. 11 a preferred embodiment of a DCM
426 is illustrated. DCM 426 includes a plurality of DDC application specific integrated circuits (ASICs) 1102 arld a plurality of DUC
ASICs 1104 for providing receive and transmit signal processing.
Receive signals are crmmllni~tpd from antennas 412 via a receive b~rkrl~nP illt~ Ic~ 1108~ h~ f receiver 1106 and buffer/driver bar~ 1107 to DDC ASICs 1102 over cnmml-ni~tion links 1110. In the preferred embodiment, DCM 426 includes ten DDC ASICs 1102 each DDC ASIC 1102 having imrlPmPntPd therein tbree individual DDCs, as described above. In the preferred embodiment, eight of the DDC ASlCs 1102 provide commllni~tinn channel functions while two of the DDC ASICs 1102 provide scanning functions. The outputs of DDC ASICs 1102 are WO 96121288 .~ 3 ~ PCTIUS9~/1711~
' ` . .;

cnmmllnir~tPd via links 1112 and b~ kl,l ",r formater 1114 and - b~rkrl~nP driYe}s 1116 to the b~rkrl~nP il~ ulu~e- l 1118. From b~rkrl~nP. ill.~ l~;vllllC~ L 1118, receive signals are cr,mmllnir~tPd to an interface media 450 (FIG. 4) for c~ "."",.,;.. .linn to a plurdlity of S channel processors 448 arranged in groups in plUC~55Vl shelves 446.

In transmit mode, transmit signals are c-)mmlTnir~tPd from channel ~lucei,~ol~ 448 over the interface media 450 and b~rkrl~nP
illLt;l~ vllllccl 1118 to the trarlsrnit b~-=k~ r receivers 1 120 to a plurality of DUC ASICs 1104 via sclc~Lvl/rvlllldt~l 1124. Each of 10 the DUC ASICs 1104 contain four individual DUCs, the DUCs as rlP~rtih~Pcl above, for processing four crlmmlmir~ltion channels in R,13 mode or two crlmm--ni~tinn channels in I,Q mode. The outputs of DUC ASICs 1104 are c.~""" ~ ,; ,.t, d via links 1126 to transmit bill k~ "r drivers 1128 and b~rkrl~np illL~l~vlllle~ L 1130 for 15 comm--nir~ticn to the DACs 414 It should be understood that suitable provision is made for providing clock signals to the elements of DCM 426 as generally indicated as 460.

With respect to the interface media 450 between the DCMs 426 20 and the channel processors 448, this may be any suitable comm--nir~tinn media. For example, interface media may be a rnicrowave link, TDM span or fiber optic link. Such an dlldllr.,~.lll~;ll~
would allow for channel Illvce.,svl~ 448 to be Dub~L~ulLidlly remotely located with respect to the DCMs 426 and the RF processing shelves 25 406. Hence, the channel processing functions could be accnmrlichPd centrally, while the Lldi~SCGi\'~l functions are accomplished at a Cv~llllllll;rA~ion cell site. This dll~l"~.. "r ,l simplifies construction.of.
cnmm--nic~tion cell sites as a ~ Alil;~l portion of the commllnir~tir~n e~lui~ c.l~ can be remotely located from the actual 30 cv,,,,,,,,,,ir;.lion cell site.

WO 96/21288 PCTIUS9~/17117 0 ~1~2~82 As shown in nG. 4, L,al,sc~;~G, 400 includes three DCMs 426, with a capability of twelve c~.,,,,,,,~.,ir~lion channels per DCM 426.
This ~Icu~t~ L provides system reliability. Should a DCM 426 fail, the system loses only a portion of the available comml~nir~tion 5 channels. Moreover, DCMs may be modified to provide multiple air interface capability. That is the DDCs and DUCs on the DCMs may be individually p~ug~dl~ d for particular air intPrf~rPc Hence, Llal~ScG;~,- 400 provides multiple air interface capability.
As d~ ;dlGd from the foregoing, there are IlUll~G~.Ju~
advantages to the structure of l1~l5CC;~, 400. With reference to FIG. 5 a receiver 500 of LldllS~G~VGI 400 is shown which is very similar to the receiver 200 shown in FIG. 2. The plurality of DDCs 214 and the il.t.,l~."ll ~ l illg, TDM bus 226 have been removed for clarity only, and it should be understood that receiver 500 includes these elements. Receiver 500 includes an ~ itir)n~1 DDC 502 illt~ t~ d as before via a selector 504 to ADCs 506 for receiving uplink digital signals from antennas 508/mixers 509 and for c.u"""""i~ data signals to channel ~"uc~s~ 510 via data bus 514. During operation, it may be necessary for a channel 20 ~lUCc~o, 510 to survey other antennas, antennas other than an antenna it is presently processing a commllnir~tion channel for, to tiPtPrminP if it is Comml-nir:-tin~ over the best antenna in the ct-mml-nir~tiûn cell. That is, if an antenna servicing another sector of the c~".""~ lion cell provides better commllnir~tion quality, 25 the c~-mmllnir~tion link should be reestablished on that antenna. To rlrl Illil~ the availability of such arltennas providing better crlmmllnir~tirn quality, the channel processor scans each sector of the r~mmllnir~fj(m cell. In the present invention, this is accomplished by having the channel processor 510 seize DDC 502 30 and program it, via the control bus 512, to receive communications from each of the antennas in the commllnir~tion cell. The ~\ W096/21288 ~1 ~23.~2 ~ P~ 1117 information received, for example received signal strength in~ tinnc (RSSI) and the like, are evaluated by channel ~luce~vl~
510 to rl~tlormin~ if a better antenna exists. The processing in DDC
502 is identical to the l.lv~e~ c~ llrd in DDCs 214, with S the exception that DDC 502, under instruction of channel processor 510, receives signals from a plurality of the antennas in the c~mm~nir~tinn cell as opposed to a single antenna servicing an active c~ ;r ~ inn channel F~G. 19 illllctr~t~c a method 1900-1926 of accomplishing this 10 per-channel scanning feature. The method enters at bubble 1900 and proceeds to block 1902 where a timer is set. The channel ~,IUC~ssul then checks if DDC 302 is idle, 1904, i.e., not presently p~,lrulll~..lg a scan for another channel ~IUC~ vl, and if it is idle, checks to see if the control bus 312 is also idle, 1906. If it is, the timer is stopped, 1908 and channel plUCc~ol 310 seizes the control bus 312, 1909. If channel ylvc~ssûl 310 is unable to seize the control bus 312, 1912, then the method loops back to block 1902. If either the DDC 302 or the control bus 312 are not idle, then a time out check is made, 1910, if time out has not been reached, the method loops back to check if the DDC has become available. If a time out has been reached, an error is reported, 1920, i.e., channel processor 310 was unable to complete a desired scan.
If the control bus 312 is successfully seized, 1912, channel ~)IU~ iSUl programs DDC 302 for the scan function, 1914. If, however, DDC 302 has become active 1916, the ~.lu~ln~lllll;ll" is aborted and an error is reported, 1920. Otherwise, the DDC 302 accepts the LJIv~,n""";ll~ and begins collecting samples, 1918, from the various antennas 308. When all the samples are collected, 1922, the DDC is programmed to an idle state, 1924, and the method ends 1926.

WO 96~21288 ~ . ~,1/1).. ~17117 0 23~2 Another feature of hall~CCi~ 400 is an ability to provide signaling to pdlLil,ulai sectors or to all sectors of a comm--nic~tion cell. With reference once again to FlGs. 3 and 13, the outputs of up cul,~lLt-/.l,odulators 1340 are comm--nicS~t~d to selectors 306 which 5 are operable to select outputs from the plurality of up co~ elLc-/,l,odulators 1340 which are to be directed to a particular sector of the cnmm-lni~tinn cell. As illll~tr~tPd in nG. 3, for a three sector ~o~ ;r~tin~ cell, three data paths 313 are provided ~:UIl~.Dl..,.~.li.,E to the three sectors of the cnmm--nir~tion cell, and the 10 function of selectors 306 is to sum the output of up co"~v.,l~.,l~/modulators 1340 onto one of these three data paths. In this manner, the downlirlk signals from up lu~ .L~I~/modulators 1340 are G~nmmllnic~t~d to an ~ lu~lidLc sector of the cnmm--nic~tinn cell.
Sclector 306, however, is further operable to apply the output of an up cull~lt~llllln~ tnr 1340 to all of the signal paths 313. In this case, the downlink signals from the up cu..~lLt,/"iodulator 1340 is comm--nir~t~d to all sectors of the culll",~ on cell ~in IlllA~rou~ly. Hence, an omni like signaling channel, through 20 ~imlllc~t7 is created by rl~ci~n~tin~ an up cu,l~c,~l/",odulator as a signaling channel and p~U~I~lllllillg selector 306 to communicate the downlink signals from this up co,~ llo-lulator to all sectors of the cullllll~ on cell. Moreover, it should be ~p~JI~,.,i~Lcd that signaling to particular sectors may be accomplished by 25 reprograrnIning selector 306 to romm~nir~t~ the downlink signals from a signaling up cu"~c.Lcl/l..n~ tnr 1340 to one or more sectors of the c~,.,l"l.~ on cell.
With reference to FIG. 6, a transceiver 600 is shown which, while containing the functional elements described with respect to 30 transceiver 400, provides a different architectural arrangement.
TI~IDC.,;~.,I 600 advantageously provides uplink digital down ~ WO 96/21288 ~18 2 3 ~ 2 PCT/US9~/171~7 ,, , ~ ,,; ~, conYersion and corresponding downlink digital up conversion within the channel ~ lucessul~. The channel processors are then P~ Ird to the RF hardware via a high speed link.
In a receive mode, RF signals are received at antennas 602 (individually number 1, 2, ..., n) and are cnmmllnir~t~od to ~CrJri~tPd receive RF processing shelves 604. Each receive RF shelf 604 contains an RF down converter 606 and an analog to digital converter 608. The outputs of the receive RF shelves 604 are high speed digital data streams which are cnmm-lnir~tPd via an uplink bus 610 to a plurality of channel yluc~vl~ 612. The uplink bus 610 is suitable high speed bus, such as a fiber optic bus or the like. The channel processors 612 include a selector for selecting one of the antennas from which to receive a data stream arld a DDC and other baseband processing cblll~ull~ 613 for selecting and processing a 15 data stream from one of the antennas to recover a Comm~nir~tinn channel. The c~.".l.~ l;..., channel is then c~ rd via a suitable illLt:l-,ullll~,l to the cellular network and PSTN.
In a transmit mode, downlink signals are received by the channel l~luce~ul~ 612 from the cellular network and PSTN. The channel ~IUCcssvl~ include up ~ullv~ /",nfl~ torc 615 for up converting and modulating the downlink signals prior to comml-nir~tin" a downlink data stream to transmit RF processing shelves 614 over transmit bus 616. In should be understood that transmit bus 616 is also a suitable high speed bus. Transmit RF
processing shelves 614 include the digital summers 618, DACs 620 and RF up converters 622 for processing the downlirlk data streams into RF analog signals. The RF analog signals are then c~-llll.lllll;. ~lrd via an analog transmit bus 624 to power amplifier 626 and antennas 628 where the RF analog signals are radiated.
With reference to FIG. 7, a LI~lSC~ ,l 700 is shown which, while also corlt~ining~ the functional elements described with respect 3 ~ 2 to Ll~l~sct;ivtl 400, provides still another a.~ lulal arrangement.
T~ cci~ 700 is described for a single sector of a 5~ d commnnir~tion system. It should be a~ ,idt~,d that transceiver 700 is easily modified to service a plurality of sectors.
In â receive mode, RF signals are received by antennas 702 and commllnir~t~d to receiYe RF processing shelves 704. Receive RF
~lu~s~illg shelves 704 each contain an RF down converter 703 and an ADC 705. The output of receive RF l lUC~ illg shelves 704 is a high speed data stream which is c~.,,,,,,ll,,i~ ~d via high speed b:~rkrl ~n~ 706 to â plurality of DDCs 708. DDCs 708 operate as previously described to select the high speed data streams and to down convert the data streams. The outputs of DDCs 708 are low speed data streams which are c~lmmllnir~trd on busses 710 and 712 to channel ~IuC~vl~ 714. Channel ~IUCci.~ul~ 714 operate as previously described to process a ~u",l"~"ir~l;on channel and to C~ lr the COIlllll~ I;on channel to the cellular network and PSTN via a channel bus 716 and network interfaces 718. The DDCs 708 of Llàllsc~iv~l 700 may also be advantageously located on a channel processor shelf with an àl!~)lU~ high speed b~rkpl~n~
i.~ ;o~ c~l.
In a transmit mode, downlink signals are cnmmlmir~t~d from the cellular network and PSTN via int,orf~res 718 and channel bus 716 to the chânnel processors 714. Channel ~IUCc~ol~ 714 include DUCs and DACs for up converting and digitizing the downlink 2~ signals to analog IF signals. The analog IF signals are communicated via coaxial cable illLe.-,ull~le~ 722, or other suitable interconnection media, to a transmit matrix 724 where the downlink signals are combined with other downlink analog IF signals. The combined analog IF signals are then crJmmllnir~tP~l via coaxial interconnects 726, to RF up converters 728. RF up COIl~"L~ 728 convert the IF
signals to RF signals. The RF signals from up conve~ ers 728 are RF

~ WO 96/21288 218 2 3 ~ 2 PCT/US9~/17117 . .
. .

summed in summer 730 and are then comm-lnir:-tPd to power ~nnrlifiP~ and transmit antennas (not shown).
As will be d~ ,idl~d from Llal.a~ 700, the high speed data processing, i:e., the digital up CU~ aiUII, on the downlink signals is 5 advantageously ~cf mrli~hPd within the channel processors 714. A
preferred embodiment of a channel lJIUC~;aaC~i 714 is shown in FIG.
18. Channel ~JIUCCaSOl 714 is similar in most aspects to channel processor 228 shown in FIG. 17 with like elements bearing like reference numeral. Channel ~.u, csso. 714 includes, in addition to 10 these element, DUCs 1802 are coupled to receive downlink signals from ~llUC~aac~la 1742, 1742'. DUCs 1802 up convert the downlink signals which are c~ d to DACs 1806 where the downlink signals are converted to analog IF signals. The analog IF signals are the comm~nir~tPfl via ports 1740, 1740', to the transmit matrix 724.
With reference to FIGs. 8, 9 and 10 further ~llallg~,.,-tll~a for illt~ ,l)lllIf~ the elements of LlallSC~ ,I 400 are shown. To avoid the loss of an entire cell due to the failure of a single Culll~ull~,-lL, daisy chain ill~ u",le-,~ion of Culll~Jullt;llL~ is avoided. As seen in FIG. 8, and for example in the downlink ,.llallC,. .Il~ .ll selectors 800 are provided in the DCMs 802 prior to DUCs 804 and DAC 806.
Direct data links 808 are provided from DUCs 804 to selectors 800 from DCM 802 to DCM 802 and finally to DAC 806. Bypass data links 810 are also provided tapping into direct data links 808. In operation, if one or more DCMs 802 fails, selectors 800 are operable 2~ to activate the ~lu~lial~ bypass data links 810 to bypass the failed DCM 802 and to allow corltin~Pd c"" " "~ I ;fm of signals to amplifier 812 and transmit antenna 814. It should be understood that the uplink elements can be similarly connected to provide a fault tolerant receive portion of the LldllSC~
FIG. 9 shows an alternate arrangement. In FIG. 9, channel processors 920 are ill~ Clllllf~ via a TDM bus 922 to DCMs 902.

WO 96/21288 PCT/U99~/17117 DCMs are irlt~l..""~ ..d as described in FIG. 8, selectors 900 associated with each DCM 902 are not shown, it being understood that selectors may easily be il,lpl~ l.t, ~ directly in the DCMs 902.
By pass links 924 illt~ the channel processors 920 directly 5 to an associated DCM, and into an ~l(lition~l selector (not shown) within DCMs 902. In the event of the failure of a channel processor 920 bringing down TDM bus 922 or a failure of TDM bus 922 itself, the selectors within the DCMs 902 can activate the c.~lupliale bypass link 924 to allow continll~d ~""", "~ ;on of signals to DAC
10 906, amplifier 912 and transrnit antenna 914.
FIG. 10 shows still another alternate ~, ~ . "- ,l Again, DCMs 1002 are il,L~ ",~t~ d as described in FIG. 8. In FIG. 10 direct links 1030 i"t~ ul"lc~,l channel ~ JC~S:~ul:l 820 in a daisy chain fashion, the output of each channel processor 1020 being lS summed in summers 1032 and then c~mmllnir~t~d to DCMs 1002 on a TDM bus 1034. By pass links 1036 forming a second bus, are provided as are selectors 1038 in a fashion similar to that shown for DCMs 802 in FIG. 8. In the event of a failure of any one of the channel ~,uc~;~,v,~, the signals from the remaining channel 20 IllUCCSSGI~ 1020 can be routed around the failed channel processors in the same manner as described for the DCMs 802, above to selector 1000, DAC, 1006, amplifier 1012 and antenna 1014.
The many advantages and features of the present invention will be a~ d from the fore~oing description of several preferred 2~ embodiments. It should be understood, that many other embodiments, advantaoes and features fall within its fair scope as may be understood from the subjoined claims.
What is c~aimed is: -

Claims (35)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A multi-channel digital receiver comprising:
a first receiver bank, the first receiver bank comprising:
a first plurality of radio frequency converters each coupled to a first plurality of antennas and operable to convert radio frequency signals received at the first plurality of antennas to a first set of intermediate frequency signals;
a first plurality of analog-to-digital converters coupled to each of the first plurality of radio frequency converters for converting the first set of intermediate frequency signals to a first set of digital signals;
a first switched digital down converter coupled to the first plurality of analog-to-digital converters and operable for selecting one of the first set of digital signals and converting the one of the first set of digital signals to a first baseband intermediate frequency signal;
a second receiver bank, the second receiver bank comprising:
a second plurality of radio frequency converters each coupled to a second plurality of antennas and operable to convert radio frequency signals received at the second plurality of antennas to a second set of intermediate frequency signals;
a second plurality of analog-to-digital converters coupled to each of the second plurality radio frequency converters for converting the second set of intermediate frequency signals to a second set of digital signals;
a second switched digital down converter coupled to the second plurality of analog-to-digital converters and operable for selecting one of the second set of digital signals and converting the one of the second set of digital signals to a second baseband intermediate frequency signal; and a plurality of channel processors coupled to the first and second switched digital down converters via a bus for recovering one of a plurality of communication channels contained within the first and second baseband intermediate frequency signals.

2. The multi-channel digital receiver as in claim 1 wherein the first switched digital down converter comprises a first plurality of switched digital down converters.

3. The multi-channel digital receiver as in claim 2 wherein each of the first plurality of switched digital down converters are coupled to the first plurality of analog-to-digital converters.

4. The multi-channel digital receiver as in claim 2, further comprising a first bus for connecting the first plurality of digital down converters to the plurality of channel processors.

5. The multi-channel digital receiver as in claim 1, wherein the second switched digital down converter comprises a second plurality of switched digital down converters.

6. The multi-channel digital receiver as in claim 5, further comprising a second bus for connecting the second plurality of digital down converters to the plurality of channel processors.

7. A multi-channel digital transmitter comprising:
a plurality of channel processors in communication with a communication system for receiving digital downlink communication signals and for processing the digital downlink communication signals for transmission on one of a plurality of communication channels;
a plurality of up converters/modulators respectively associated with each of the plurality of communication channels and connected to the channel processors for up converting and modulating the digital downlink communication signals to digital intermediate frequency signals;
a plurality of digital summers connecting the up converters/modulators for summing the digital intermediate frequency signals into digital intermediate frequency signal sub-groups;
a plurality of digital-to-analog converters for converting the digital intermediate frequency signal sub-groups into a plurality of analog signals;

a plurality of radio-frequency up converters respectively coupled to the digital-to-analog converters for converting the analog signals to radio frequency signals; and a plurality of power amplifiers respectively coupled to the up converters for amplifying the radio frequency signals and for communicating the radio frequency signals to a plurality of antennas.

8. The multi-channel digital transmitter as in claim 7 wherein the sub-groups of digital intermediate frequency signals are associated with a plurality of sectors of a sectorized communication system.

9. The multi-channel digital transmitter as in claim 7 wherein the plurality of up converter/modulators are connected to the channel processors via a time domain multiplex bus.

10. The multi-channel digital transmitter as in claim 7 wherein the plurality of digital summers comprise signal selectors for selecting a sub-group of the digital intermediate frequency signals for summing into digital intermediate frequency sub-groups.

11. The transmitter of claim 7, further comprising a bypass data link in communication with at least one of the plurality of channel processors.

12. The transmitter of claim 7, wherein at least one of the plurality of channel processors is in remote communication with at least one of the plurality of up converters/modulators.

13. A multi-channel digital transmitter comprising:
a plurality of channel processors in communication with a communication system for receiving digital downlink communication signals and for processing the digital downlink communication signals for transmission on one of a plurality of communication channels;

a plurality of up converters/modulators respectively associated with each of the plurality of communication channels and connected to the channel processors for up converting and modulating the digital downlink communication signals to digital intermediate frequency signals;
a plurality of digital summers connecting the up converters/modulators for summing the digital intermediate frequency signals into digital intermediate frequency signal sub-groups;
a plurality of digital-to-analog converters for converting the digital intermediate frequency signal sub-groups into analog signals;
an analog summer sellectively connected to the digital-to-analog converters for summing a sub-set of the analog signals into an analog intermediate frequency signal;
a radio-frequency up converter coupled to the analog summer for converting the analog intermediate frequency signal to a radio frequency signal; and a power amplifier coupled to the radio-frequency up converter for amplifying the radio frequency signal and for communicating the radio frequency signal to an antenna.

14. The multi-channel digital transmitter as in claim 13 wherein the sub-set of the plurality of analog signals are associated with a sector of a sectorized communication system.

15. The multi-channel digital transmitter as in claim 13 wherein the plurality of up converter/modulators are connected to the channel processors via a time domain multiplex bus.

16. The multi-channel digital transmitter as in claim 13 wherein the plurality of digital summers comprise signal selectors for selecting a sub-group of the digital intermediate frequency signals for summing into digital intermediate frequency sub-groups.

17. The transmitter of claim 13, wherein at least one of the plurality of up converters/modulators further comprises a selector.

18. The transmitter of claim 17, wherein the selector is in communication with at least one of the plurality of digital-to-analog converters.

19. The transmitter of claim 17, further comprising a bypass data link coupled to the selector.

20. The transmitter of claim 13, wherein at least one of the plurality of channel processors is in remote communication with at least one of the plurality of up converters/modulators.

21. A mufti-channel digital transmitter comprising:
a plurality of channel processors in communication with a communication system for receiving digital downlink communication signals and for processing the digital downlink communication signals for transmission on one of a plurality of communication channels;
a plurality of radio frequency processing shelves, each of the radio frequency processing shelves comprising a plurality of up converters/modulators respectively associated with each of the plurality of communication channels and connected to the channel processors for up converting and modulating the digital downlink communication signals to digital intermediate frequency signals and a plurality of digital summers connecting the up converters/modulators for summing the digital intermediate frequency signals into digital intermediate frequency signal sub-groups;
a plurality of digital-to-analog converters for converting the digital intermediate frequency signal sub-groups into analog signals;
an analog summer selectively connected to the digital-to-analog converters for summing a sub-set of the analog signals into an analog intermediate frequency signal;

a radio-frequency up converter coupled to the analog summer for converting the analog intermediate frequency signal to a radio frequency signal; and a power amplifier coupled to the radio-frequency up converter for amplifying the radio frequency signal arid for communicating the radio frequency signal to an antenna.

22. The mufti-channel digital transmitter as in claim 21 wherein the sub-groups of digital intermediate frequency signals are associated with sectors of a sectorized communication system.

23. The mufti-channel digital transmitter as in claim 21 wherein the sub-set of the analog signals are associated with a sector of a sectorized communication system.

24. The mufti-channel digital. transmitter as in claim 21 wherein the plurality of up converters/modulators are connected to the channel processors via a time domain multiplex bus.

25. The multi-channel digital transmitter as in claim 21 wherein the plurality of digital summers comprise signal selectors for selecting a sub-group of the digital intermediate frequency signals for summing into digital intermediate frequency sub-groups.

26. The transmitter of claim 21, further comprising a plurality of analog summers, a first of the plurality of analog summers responsive to a first group of the plurality of digital-to-analog converters and a second of the plurality of analog summers responsive to a second group of the plurality of digital-to-analog converters.

27. The transmitter of claim 21, wherein the first group of the plurality of digital-to-analog converters includes at least three digital-to-analog converters.

28. A mufti-channel digital transmitter comprising:
a plurality of channel processors in communication with a communication system for receiving digital downlink communication signals and for processing the digital downlink communication signals for transmission on one of a plurality of communication channels;
a plurality of transmitter banks, each of the transmitter banks comprising:
(a) a plurality of radio frequency processing shelves, each of the radio frequency processing shelves comprising a plurality of up converters/modulators respectively associated with each of the plurality of communication channels and connected to the channel processors for up converting and modulating the digital downlink communication signals to digital intermediate frequency signals and a plurality of digital summers connecting the up converters/modulators for summing the digital intermediate frequency signals into digital intermediate frequency signal sub-groups;
(b) a plurality of digital-to-analog converters for converting the digital intermediate frequency signal sub-groups into analog signals;
(c) a plurality of analog summers selectively connected to the digital-to-analog converters for summing a sub-set of the analog signals into analog intermediate frequency signals;
(d) a plurality of radio-frequency up converters coupled to the plurality of analog summers for converting the analog intermediate frequency signals to radio frequency signals;
a plurality of radio-frequency summers for summing sub-sets of radio frequency signals into a summed radio frequency signals;
and a plurality of power amplifiers respectively coupled to the radio-frequency summers for amplifying the summed radio frequency signals and for communicating the summed radio frequency signals to antennas.

29. The multi-channel digital transmitter as in claim 28 wherein the sub-groups of digital intermediate frequency signals are associated with sectors of a sectorized communication system.

30. The multi-channel digital transmitter as in claim 28 wherein the sub-set of the analog signals are associated with a sector of a sectorized communication system.

31. The multi-channel digital transmitter as in claim 28 wherein the plurality of up converters/modulators are connected to the channel processors via a time domain multiplex bus.

32. The multi-channel digital transmitter as in claim 28 wherein the plurality of digital summers comprise signal selectors for selecting a sub-group of the digital intermediate frequency signals for summing into digital intermediate frequency sub-groups.

33. A method of digitally transmitting a multi-channel wideband frequency signal comprising the steps of:
receiving digital downlink signals from a communication network interconnect of a communication system;
processing the digital downlink signals for transmission on one of a plurality of communication channels;
up converting and modulating the digital downlink signals to digital intermediate frequency signals;
summing sub-groups of the digital intermediate frequency signals; directing the sub-groups of the digital intermediate frequency signals, respectively, to sectors of the communication system;
converting the summed sub-groups of the digital intermediate frequency signals to analog intermediate frequency signals;
summing the analog intermediate frequency signals from a plurality of downlink signal sources into sub-sets of analog intermediate frequency signals, the sub-sets of analog intermediate frequency signals being associated with a sector of the communication system;

up converting the sub-sets of the analog intermediated frequency signals to radio frequency signals;
amplifying the radio frequency signals; and radiating the radio frequency signals from an antenna.

34. A method of digitally transmitting a multi-channel wideband frequency signal comprising the steps of:
receiving digital downlink signals from a communication network interconnect of a communication system;
processing the digital downlink signals for transmission on one of a plurality of communication channels;
up converting and modulating the digital downlink signals to digital intermediate frequency signals;
directing sub-groups of the digital intermediate frequency signals, respectively, to sectors of the communication system;
summing the directed sub-groups of the digital intermediated frequency signals;
converting the summed sub-groups of the digital intermediate frequency signals to analog intermediate frequency signals;
up converting the analog intermediate frequency signals to radio frequency signals;
radio frequency summing the radio frequency signals from a plurality of downlink signal sources into sub-sets of radio frequency signals, the sub-sets of radio frequency signals being associated with a sector of the communication system;
amplifying the summed radio frequency signals; and radiating the amplified radio frequency signals from an antenna.

35. A multi-channel wideband frequency transceiver comprising:
a plurality of receive antennas for receiving radio frequency signals;
a plurality of radio frequency converters coupled to each of the plurality of receive antennas and operable to convert the radio frequency signals to intermediate frequency signals;

a plurality of analog-to-digital converters coupled to each of the radio frequency converters for converting the intermediate frequency signals to digital signals;
a switched digital down converter coupled to the analog-to-digital converters and operable for selecting one of the digital signals and converting the one of the digital signals to a baseband intermediate frequency signal;
a plurality of channel processors coupled to the switched digital down converter for recovering one of a plurality of communication channels contained within the baseband intermediate frequency signal and for communicating the recovered communication channel to a network interconnect of a communication system; the plurality of channel processors being further operable to receive digital downlink communication signals from the network interconnect and for processing the digital downlink communication signals for transmission on one of the plurality of communication channels;
a plurality of up converters/modulators respectively associated with each of the plurality of communication channels and connected to the channel processors for up converting and modulating the digital downlink communication signals to digital intermediate frequency signals;
a plurality of digital summers connecting the up converters/modulators for summing the digital intermediate frequency signals into digital intermediate frequency signal sub-groups;
a plurality of digital-to-analog converters for converting the digital intermediate frequency signal sub-groups into analog signals;
an analog summer selectively connected to the digital-to-analog converters for summing a sub-set of the analog signals into an analog intermediate frequency signal;
a radio-frequency up converter coupled to the analog summer for converting the analog intermediate frequency signal to a radio frequency signal; and a power amplifier coupled to the radio-frequency up converter for amplifying the radio frequency signal and for communicating the radio frequency signal to a transmit antenna.