CA2176880A1 - Scaled adaptive lithography - Google Patents

Scaled adaptive lithography

Info

Publication number
CA2176880A1
CA2176880A1 CA002176880A CA2176880A CA2176880A1 CA 2176880 A1 CA2176880 A1 CA 2176880A1 CA 002176880 A CA002176880 A CA 002176880A CA 2176880 A CA2176880 A CA 2176880A CA 2176880 A1 CA2176880 A1 CA 2176880A1
Authority
CA
Canada
Prior art keywords
feed
representation
artwork
line ends
positions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002176880A
Other languages
French (fr)
Other versions
CA2176880C (en
Inventor
Leonard Richard Douglas
Richard Joseph Saia
Kevin Matthew Durocher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of CA2176880A1 publication Critical patent/CA2176880A1/en
Application granted granted Critical
Publication of CA2176880C publication Critical patent/CA2176880C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

An adaptive method of providing electrical interconnections for a plurality of feed-through lines each having a respective end extending to at least one substrate surface includes generating an artwork representation for the electrical interconnections using specified feed--through line end positions on the at least one substrate surface. The at least one substrate surface may include a surface of a stack of substrates with at least two substrates having feed-through line ends facing a common direction. Actual positions of the at least two of the feed--through line ends are determined, and a scale factor is estimated using the determined actual positions. Actual positions of others of the feed-through line ends are estimated using the scale factor, and the artwork representation is modified to properly include electrical interconnections to ones of the feed-through line ends which are not in their specified positions. The artwork representation can be converted into a turn point polygon (TPP) format for effective data handling and modification of the artwork representation, and the TPP format can then be can be converted to a rectangular representation. A laser can be controlled in accordance with the rectangular representation of the modified artwork.
CA002176880A 1995-05-30 1996-05-17 Scaled adaptive lithography Expired - Fee Related CA2176880C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/453,110 US5844810A (en) 1995-05-30 1995-05-30 Scaled adaptive lithography
US08/453,110 1995-05-30

Publications (2)

Publication Number Publication Date
CA2176880A1 true CA2176880A1 (en) 1996-12-01
CA2176880C CA2176880C (en) 2007-11-13

Family

ID=23799247

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002176880A Expired - Fee Related CA2176880C (en) 1995-05-30 1996-05-17 Scaled adaptive lithography

Country Status (5)

Country Link
US (1) US5844810A (en)
EP (1) EP0746020B1 (en)
JP (1) JP4100728B2 (en)
CA (1) CA2176880C (en)
DE (1) DE69620945T2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6003715A (en) * 1998-09-15 1999-12-21 Harris; Walter H. Plastic bucket air vent and method
US6330708B1 (en) * 1998-09-17 2001-12-11 International Business Machines Corporation Method for preparing command files for photomask production
US6622295B1 (en) * 2000-07-05 2003-09-16 Dupont Photomasks, Inc. Network-based photomask data entry interface and instruction generator for manufacturing photomasks
US6760640B2 (en) * 2002-03-14 2004-07-06 Photronics, Inc. Automated manufacturing system and method for processing photomasks
US7669167B2 (en) * 2002-07-30 2010-02-23 Photronics, Inc. Rule based system and method for automatically generating photomask orders by conditioning information from a customer's computer system
US7269813B2 (en) * 2004-11-19 2007-09-11 Alcatel Off-width pitch for improved circuit card routing
US9595485B2 (en) * 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933042A (en) * 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US4783695A (en) * 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4835704A (en) * 1986-12-29 1989-05-30 General Electric Company Adaptive lithography system to provide high density interconnect
GB2202673B (en) * 1987-03-26 1990-11-14 Haroon Ahmed The semi-conductor fabrication
US4972311A (en) * 1988-08-15 1990-11-20 Kulicke And Soffa Industries Inc. X-Y table error mapping apparatus and method
US5019946A (en) * 1988-09-27 1991-05-28 General Electric Company High density interconnect with high volumetric efficiency
US4894115A (en) * 1989-02-14 1990-01-16 General Electric Company Laser beam scanning method for forming via holes in polymer materials
US5019997A (en) * 1989-06-05 1991-05-28 General Electric Company Adaptive lithography accommodation of tolerances in chip positioning in high density interconnection structures
US5161093A (en) * 1990-07-02 1992-11-03 General Electric Company Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive
US5257178A (en) * 1991-12-19 1993-10-26 General Electric Company Method of optimally operating a computer numerical control milling machine to mill optimal high density interconnect substrates
US5285571A (en) * 1992-10-13 1994-02-15 General Electric Company Method for extending an electrical conductor over an edge of an HDI substrate
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
US5355306A (en) * 1993-09-30 1994-10-11 Motorola, Inc. Alignment system and method of alignment by symmetrical and asymmetrical analysis
US5506793A (en) * 1994-01-14 1996-04-09 Gerber Systems Corporation Method and apparatus for distortion compensation in an automatic optical inspection system

Also Published As

Publication number Publication date
CA2176880C (en) 2007-11-13
EP0746020A3 (en) 1997-07-02
JP4100728B2 (en) 2008-06-11
EP0746020A2 (en) 1996-12-04
DE69620945D1 (en) 2002-06-06
US5844810A (en) 1998-12-01
DE69620945T2 (en) 2002-12-12
JPH09102576A (en) 1997-04-15
EP0746020B1 (en) 2002-05-02

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Legal Events

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