CA2107437A1 - Information processing system - Google Patents
Information processing systemInfo
- Publication number
- CA2107437A1 CA2107437A1 CA002107437A CA2107437A CA2107437A1 CA 2107437 A1 CA2107437 A1 CA 2107437A1 CA 002107437 A CA002107437 A CA 002107437A CA 2107437 A CA2107437 A CA 2107437A CA 2107437 A1 CA2107437 A1 CA 2107437A1
- Authority
- CA
- Canada
- Prior art keywords
- memory
- data
- address
- cpu
- information processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
Abstract
ABSTRACT OF THE DISCLOSURE
In an information processing system, a wait state signal is inserted into a RDY signal, according to which data are transmitted through memory and I/O buses. A CPU controls the number of the wait state signal to adjust the difference of the transfer speeds of the memory and I/O buses.
In an information processing system, a wait state signal is inserted into a RDY signal, according to which data are transmitted through memory and I/O buses. A CPU controls the number of the wait state signal to adjust the difference of the transfer speeds of the memory and I/O buses.
Description
2la7~37 INl~ORMaTION PROCESSING SYSTEM
BACRGROllND OF THE Il~ TION
The present invention relates to an information processing system, and more particularly to a game computer system processing both image and sound data.
In a computer system, a CPU and peripheral devices are connected with each other through control, address and data buses. The CPU is connected to a memory and I/O devices through memory and I/O buses, respectively. In such a system, the following instructions are repeated to transfer data from the memory to the I/O spaces (I/O devices) continuously:
* READ DATA FROM MEMOR~
* WRITE DATA TO I/O
In a general computer system, the following instruction for readin~ or writing is prepared after the current process has been completed.
A game computer system which works at a high speed includes a CPU that processes the following instruction while the current instruction is being in pxocess, this process being known as a DMA (Direct Memory Access) function. According to this system, data to be transmitted are accumulated on the memory bus, because the l/O bus transmits data slower than the memory bus. As a result, the computer system can not perform pipeline processing normally.
Accordingly, in one ~ype of conventional game computer 2~07~37 system, timing for transmitting data is controlled by a user program with NOP (NO Operation) instructions. That is, the following program is used to transfer data from the memory to the I/O space:
* READ DATA FROM MEMORY
* WRITE DATA TO I/O
* NOP
In this case, the transmission timing is adjusted by the NOP instruction after the data are written into the I/O
space.
The following program is used to transfer data from the I/O space to the memory:
* READ DATA FROM I/O
* NOP
* WRITE DATA TO MEMORY
According to the program, the data are transmitted from the CPU to the memory securely.
Recently, with development of high performance CPUs, peripheral devices must be accessed with exact timings which are controlled by a program.
Generally, in an information processing system, the configuration of a DRAM (dynamic random access memory) is different depending on the type of data to be processed and the capacity of the memory, that is, the DRAM is addressed for each 8 and 16 bits when 8 and 16 bit data are to be processed, respectively. Most conventional computer systems employ decode 2:l~7~3~
IC chips for generating addresses fitting a variety of memory configurations.
Fig. 1 shows a memory of 64K x 2 chip type, according to a conventional computer system. When address information is supplied to a decode IC, corresponding data in the memory are accessed by the decode IC. According to this system, the decode IC is necessary and the memory configurations are limited, and therefore, it is difficult to access a variety of memories having different configurations.
The memory (DRAM) is composed of plural memory cells each composed of a transistor and a capacitor to decrease its cost and to increase its integration rate. The DRAM is accessed by an address multiplex system to decrease the si~e of the system, as shown in Fig. 2. In this system, address signals are supplied to address terminals by a time di~ision system, as shown in Fig. 3.
The DRAM is accessed in a high speed access mode to increase the access speed. In this mode, a word line is selected in accordance with a row address to supply all data connected with the word line to corresponding sense amplifiers, and then one of the amplifiers is selected in accordance with a column address to obtain data to be accessed. After that, when the column address only is changed, data stored in another sense amplifier is accessed.
When data are read from a memory in a read cycle, the memory is accessed by repeating RAS (Row Addressing) and CAS
2~0~437 (Column addressing) cycles alternately, the cycle bein~ called an "MADR cycle," and the access system a "page mode access."
~ccording to this system, much data can not be accessed at a high speed~ this problem being serious for graphic data processing that needs to treat much continuous data.
Accordingly, another type of conventional computer systems employs a cache memory managed directly by a CPU, as shown in Fig. 5. The cache memory stores data read from a DRAM, so ~hat the CPU reads the data from the cache memory directly, not from the DRAM. If the cache memory stores no data to be accessed by the CPU, the CPU must accesses the DRAM. For that reason, the cache memory is r.ecessary to store enough data.
According to the conventional system, however, it is difficult to debug the program, because the CPU points to addresses in the cache memory, not in the main memory (DRAM~.
It is difficult to find the locations of program erroxs.
Further, the system needs an extra memory chip for the cache memory in addition to the main memory (DRAM), and therefore, the hardware becomes complicated in structure.
In the conventional computer system, when the CPU is connected to peripheral devices of different types of bit (width), data to be transmitted are adjusted in width by software. For instance, when data are transferred from an 8-bit device to a 16-bit device, eight zeros are added at the end of 8 bit data to be transferred, as shown in Fig. 6. On the other hand, when data are transferred from a 16-bit device to an 8-bit 2~7~37 device, the 16 bit data are divided into two pieces of 8 bit data to be transferred, as shown in Fig. 7. According to the conventional system, a program (software) must be designed in consideration of the width of data to be transmitted.
In general, an area out of a memory space is not addressed, when an application program is designed in a high-level language, because the memory is treated with variables.
On the other hand, in a system program or application program which is designed using a low-level language, such as an assembler language, an address out of the memory may be specified.
In the conventional system, if a nonexistent address space is addressed, an incomprehensible image is displayed on a CRT. For example, in a game computer system dealing with sound and image, a strange image is displayed on a screen if a nonexistent address of a memory is specified.
Fig. 8 shows a memory space of the conventional system. ~enerally, the memory space to be addressed by the CPU
is different from a space ()16 to (1000)16 for the actual memory (DRAM) region. In the conventional system, when the program specifies an address (3)16r an address decoder (address IC chip) analyzes the address as being an address (1000)l6, because the decoder ignores the addresses over the upper boundary address (1000)16, as shown in Fig. 9. Although no datum exists at address (3)161 the system judges as if predetermined data exist there.
21~7~37 According to the conventional system, however, when a strange image is displayed on the screen, i~ is ~ifficult to find the error location, because a programmer tends to guess that proper image data might have some errors, and therefore, the error can not be found in the worst case. In more detail, when a nonexistent memory area is accidentally specified, other data or instruction is broken, and therefore, an error occurs when the data or instruction is later accessed. Although an exceptional error may stop the processing when the instruction is broken, the error portion can not be found in debugging, because the error is based on the wrong addressing.
~UMMARY OF THE INV~NTI~N
Accordingly, it is an object of the present invention to provide an information processing system, in which the difference of data processing speeds between a memory bus and an I/O bus is adjusted by a CPU to ease the burden of a programmer.
It is another object of the present invention to provide an information processing system, in which a memory may be accessed flexibly to manage a variety of memory having different configurations.
It is another object of the present invention to provide an information processing system, in which a CPU may access a memory at a high speed without a cache memory.
25It is another object of the present invention to provide an information processing system, in which a variety of 21~37 types of peripheral devices may be managed easily.
It is still another object of the present invention to provide an information processing system, in which an addressing error may be found easily.
According to a first feature of the present invention, a wait state signal is inserted into a RDY signal to adjust the difference of the transfer speeds of memory and I/O buses, which are connected to a CPU.
According to a second feature of the present invention, an MCU is provided with configuration and refresh timer registers for specifying the configuration and the refresh cycle of a memory to be accessed, respectively.
According to a third feature of the present invention, an MCU (Memory Controller Unit~ divides an address signal into row and column addresses. The first row address is held when the same row address are supplied continuously so that a memory is accessed continuously only by changing the column address.
According to a fourth feature of the present invention, the width (number of bits) of data to be transmitted is adjusted to be compatible for a device to be accessed.
According to a fifth feature of the present invention, the configuration of a memory to be accessed is specified by a register. An error signal is generated when an area out of the actual memory area in a memory space is addressed, so that memory I/O error exceptional treatment is carried out.
21 0~37 BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is an explanatory diagram showing operation for addressing a memory using a decode IC, according to a conventional computer system.
Fig. 2 is an explanatory diagram showing a multiplexer system, according to the conventional computer system.
Fig. 3 is a timing chart showing operation for addressing the memory, according to the conventional system.
Fig. 4 is a timing chart showing a read cycle in a page mode, according to the conventional system.
Fig. 5 is an explanatory diagram showing operation for accessing the memory using a cache memory, according to the conventional system.
Figs. 6 and 7 are explanatory diagrams each showing operation for transmitting data, according to the conventional system.
Fig. 8 is a diagram illustrating a memory space, according to the conventional system.
Fig. 9 is a diagram showing operation for addressing the memory using an address decoder, according to the conventional system.
Fig. 10 is a block diagram illustrating a computer system according to the invention.
Fig. 11 is a diagram showing the address space of a CPU, according to a first preferred embodiment.
Fig. 12 is a timing chart showing operation of a basic 2~1~7437 3-3 bus cycle, according to the first preferred embodiment.
Fig. 13 is a timing chart showing operation of the basic 3-3 bus cycle including one wait state signal, according to the first preferred embodiment.
Fig. 14 is a block diagram illustrating the internal architecture of a CPU, according to a second preferred embodiment.
Fig. 15 is a diagram showing a memory map of the CPU, according to the second preferred embodiment.
Fig. 16 is a table showing specifications of memories, according to the second preferred embodiment.
Fig. 17A is a diagram illustrating the configuration of an MCU (Memory Control Unit), according to the second preferred embodiment.
Fig. 17B is a diagram illustrating the configuration of a memory specifying register, according to the second preferred embodiment.
Fig. 18 is a block diagram illustrating the architecture of a refresh timer, according to the second preferred embodiment.
Fig. 19 is a diagram showing a memory map and an address bit of a DRAM (64K x 16), accordi~g to the second preferred embodiment.
Fig. 20 is a diagram showing a memory map and an address bit of a DR~M (128K x 8), according to the second preferred embodiment.
21Q7~
Fig. 21 is a timing chart of a read cycle in a fast page mode, according to a third preferred embodiment.
Fig. 22 is a diagram illustrating ~he two-dimensional character arrangement of a main memory, according to the third preferred embodiment.
Fig. 23 is a diagram showing an access cycle in the page mode.
Fig. 24 is a diagram showing an access cycle in the fast page mode, according to the third preferred embodiment.
Fig. 25 is a diagram showing an I/O memory map of a CPU, according to a fourth preferred embodiment.
Figs. 26 and 27 are diagrams illustrating operation for transmitting th~ different types of data, according to the fourth preferred embodiment.
Figs. 28 and 29 are time charts showing the different types of read cycles, according to the fourth preferred embodiment.
Fig. 30 is a diagram illustrating the configuration of a memory, according to a fifth preferred embodiment.
Fig. 31 is an explanatory diagram illustrating operation for addressing the memory using an RAS (row address) and a CAS (column address), according to the fifth preferred embodiment.
Fig. 32 is a diagram showing the address map of a CPU, according to the fifth preferred embodiment.
Fig. 33 is a flow chart showing operation for 21~7~37 accessing the memory, which includes memory I/O error exceptional treatment, according to the fifth preferred embodiment.
Fig. 34 is a ~low chart showing operation for accessing ~he memory, which includes non-instruction exceptional treatment, according to the conventional system DETAILED D~3SCRIPTION OF qlHE~ TION
Fig. 10 shows a computer system of the inven~ion, which includes a game-software recording medium 100 such as a CD-ROM, a CPU 102 of the 32-bit type, a control ~mit 104 for mainly controlling transmission of image and sound data and interfacing peripheral devices to each other, an image data extension unit 106, an image data output unit, a sound data output unit 110, a video encoder unit 112, a VDP unit 114 and a TV display 116.
CPU 102, control unit 104, image data e~tension unit 106 and VDP unit 114 are provided with their own memories M-RAM, K-RAM, R-RAM and V-RAM, respectively.
CPU 102 directly controls a DRAM via a memory support, and performs communication through an I/O port to peripheral devices, that is called an I/O control function. CPU 102 includes a timer, a parallel I/O port and an interruption control system. CPU 102 writes display data into the VRAM, and the data are read by VDP unit 114. The display data are transmitted to video encoder unit 112 whereby the data are 21~7~37 displayed on the TV display 116.
Control unit 104 includes an SCSI controller to which image and sound data are supplied from CD-ROM 100 through an SCSI interface. The K-RAM buffers data supplied to the SCSI
S controller. Control unit 104 also includes a DRAM controller for reading data buffered in the K-RAM at a predetermined timing. In control unit 104, priority judgement i9 carried out for each dot of natural background image data. Control unit 104 transmits moving image data (full color/ pallet), which have been compressed, to image data extension unit 106 to extend the image data.
Video encoder unit 112 receives an output signal of the control unit. Video encoder unit 112 superimposes VDP image data, natural background image data and moving image data (full color, pallet) transmitted from VDP unit 114, control unit 104 and image data extension unit 108. Video encoder unit 112 performs color pallet reproducing, special effect processing, D/A converting and the like. Output data of video encoder unit 112 are encod~d into an NTSC signal by an external circuit.
ADPCM sound data recorded in CD-ROM 100 are buffered in the K-RAM and then transmitted to sound data output unit 110 under control of control unit 104. The sound data output unit reproduces the sound data.
Fig. ll shows the address space of a CPU according to a first preferred embodiment, which includes memory and I/O
spaces of 2G bytes. The CPU accesses the I/O space with some 21~r~43rl intervals to avoid jamming of a memory bus.
As shown in Fig. 12, it takes three bus-clocks (BCLK) to access the I/O port (I/O space), and the operation is finished in response to a high level RD~ signal. This operation S is called a l~basic 3-3 bus cycle.~ While the RDY signal is at low level, wait state signals may be inserted into the RDY
signal to adjust access timing of the I/O space.
When one wait state signal is inserted into the RDY
signal, as shown in Fig. 13, it takes four bus clocks to access the I/O space. This operation is called a "4-4 bus cycle.~
As described above, according to the first preferred embodiment, programmers can design a program without being conscious of access timing, because the CPU controls access timing by itself. As a result, memory space used for the program may be reduced.
Fig. 14 shows the internal architecture of a CPU
according to a second pre~erred embodiment. The architecture includes an instruction fetch unit (IFV) 120, an instruction execution unit (IEU) 122, an I/O control unit (IOU) 124 and a memory control unit (MCU) 126. MCU 126 generates all control signals to control a memory port connected to a main memory DRAM. In this architecture, data are treated for each eight bits, so that data are treated for each byte or integral byte multiples. In this system, one word is indicated by 4 bytes (32 bits).
The DRAM is composed of some memory arrays, the number 2~0~7 of words (depth in address direction) contained in each array being different depending on the depth in address direction of the chip. That is, for example, a "256 x n" type of DRAM has memory arrays each having 256k words. The number of chips forming each array is defined by the number of data ports of the DRAM.
Fig. 15 shows the DRAM of 256k-word size.
Fig. 16 shows specifications for different types of DRA~s. In this embodiment, different types of DR~Ms 64k x 16, 128k x 8, 256k x 4, 256k x 16, 512k x 8 and the like may be employed. Such memory types may be specified by a memory specifying register. These memories are controlled by the CPU
when the memory system information has been supplied to the MCU.
If such a memory system is used in a conventional system, a decode IC is necessary to decode data.
The system has a register in the MCU to specify the configuration of the memory to set a refresh time by a predetermined program. The register may be addressed in accordance with a special register transmitting instruction.
The register is mapped in a special hardware register region (bank 3, address 4-7), as shown in Fig. 17A. A memory specifying register region takes 32 bits (4 bytes) at the address 4 in the bank 3. An area for instructing refresh time is taken at the address 5 in the same bank. The content of the memory specifying register is as follows:
210743~
ROW_SIZE
000 8 bits 001 9 bits 010 10 bits 5011 11 bits 100 12 bits COL_SIZE (column size) 00 B bits 01 9 bits 10 10 bits 11 11 bits ARRAYS (array size) 0 1 array 1 2 arrays REFRESH_EN (refresh enable) 0 refresh disable 1 refresh enable The DRAM system is defined by the combination of "ROW_SIZE" and "COL_SIZE". For example, when the "ROW_SIZE" =
2 (= (010)2, that is, 10 bits) and "COL_SIZE" = 1 (= (01)2, that is, 9 bits), a DRAM of 512k x 8 (ROW x COL = 10 x 9) is instructed to be set as shown in the table of Fig. 16. Further, 2:La7~37 a type of a 1 array - 4 chips is specified when "ARRAYS = 0" is held in the register.
Next, refresh cycle operation of this system will be explained in conjunction with Fig. 1~. In general, when a DRAM
is not accessed in a predetermined period, data stored in the memory is erased. For that reason, it is necessary to refresh the memory (that is, to electrically activate it) at predetermined intervals. The MCU has a refresh timer which includes a frequency divider, a refresh timer register and a timer counter. The frequency divider divides the frequency of a system clock to generate a timer clock having a frequency of one thirty-second (1/32) that of the system clock. The timer counter receives timer clock signals. ~efresh cycle (time) is programmable and varies depending on the configuration of the DRAM.
The memory refresh operation is controlled by data stored in 0 to 6 bits regions of the refresh timer register, as shown in Fig. 16. The control operation is automatically carried out by the ports. When the memory specifying register pro~ides a refresh enable instruction, the refresh cycle is determined in accordance with contents of the timer counter and refresh timer register, whereby the memory is refreshed at predetermined intervals.
When the CPU supplies data to the refresh timer (bank 3, address 5), the data are written in the timer register. On the other hand, the CPU reads data from the timer counter of the 2~07~37 refresh timer. The timer register assumes a zero state after reset. Refresh operation is required at each time when the timer counter finishes counting (0 x 7F, that is 7F of hexadecimal notation). The timer counter continues to count the clocks for each timer clock cycle, and then the timer counter is initialized in accordance with data stored in the refresh timer r~gister when the counting is finished.
In order to assure that the DRAM on a memory port is refreshed at the rated timing, figures to be used for controlling a period of memory refresh cycle are loaded in the refresh register. The refresh timer register stores predetermined figure data, which are calculated by a program using a DRAM refresh period, a DRAM refresh cycle and a clock period of the timer clock. That is, the figure data are given by the followin~ equations.
REFRESH TIMER = 0 x 7F - CYCLE NUMBER
CYCLE NUMBER = REFRESH INTERVAL / CLOCK PERIOD
REFRESH INTERVAL = REFRESH PERIOD / REFRESH CYCLE NUMBER
The MCU employs a "CAS before RAS refresh system", so that address data are not necessary to be supplied to the D~AM
for each refresh cycle.
Next, how to address the memory by the MCU will be explained. When an address signal is supplied to the MCU, the signal is divided into row, column and array signals. The dividing method is different depending on the memory configuration, for example, a DRAM of 64 x 16 is addressed as 2~7~3~
shown in Fig. 7. An address bit system is given automatically when the type of the DRAM is determined, as follows:
ROW_SIZE = 0 COL_SIZE = 0 When "ARRAY = 0" is set in the register, the memory space has an area of 64K words (256K bytes), as shown in Fig.
19. The cross point of row and column address signals supplied from the MCU becomes an address point.
When a DRAM of 128K x 8 is used, the following 0 instructions are set in the memory setting register:
ROW_SIZE = 1 COL_SIZE = 0 In this case, the MCU forms row and column addresses of 8 and 9 bits, respectively, as shown in Fig. 20. "ARRAY = 1"
is set in the register, so that two arrays 1 and 0 are formed in the memory map, and the memory has an area of lM bytes (128K
words x 2).
Next, how to calculate the refresh time of the DRAM
will be explained. When refresh period, refresh cycle, external clock and the clock frequency of a time clock are determined to be 4ms, 256, 23ns and 736ns, respectively, refresh time is given as follows:
REFRESH INTERVAL = 4,000,00Ons / 256 = 115.625ns CYCLE = 15.625ns / 736ns = 21.229 REFRESH TIME = 0x7F - 21 = 106 (0x = 7F in hexadecimal) 2 :1~ r~ ~13 ~
While the calculated refresh time is set in the refresh timer register, the timer co~mter is refreshed in accordance with the refresh time.
The second preferred embodiment uses the computer system, shown in Fig. 10, used in the first preferred embodiment. In this embodiment, the MCU also has the function of a decode IC used in the conventional system. A memory configuration, and a memory refresh cycle which is different depending on the DRAM, are specified by programming.
A third preferred embodiment is now explained, in which a CPU may access a main memory at a high speed without a cache memory. In this embodiment, the CPU memori~es a first RAS
(Row Addressing) cycle so that data can be read continuously from the memory according only to a CAS (Column Addressing) cycle, as shown in Fig. 21. Therefore, the RAS cycle having a length of lBCLK may be omitted after starting of reading, it being called a "fast page mode access."
Next, the page mode access of the conventional system and a fast page mode access of the prefexred embodiment are now compared with each other in the following program of the C-language:
char a[100][2];
for (i=0; i<=99; i++)printf("%c",a[i][0];
2~ 0~3~
, where "printf" is a function including a read or write instruction to the memory or display. The above program means that odd characters in a two-dimensional character arrangement are displayed. In this program, "a" represents a DRAM of 16 bit shown in Fig. 22.
The odd characters are arranged at the lower bit side of the memory. The DRAM uses only one RAS, so that image data may be displayed only by changing the CAS in the fast page mode.
Figs. 23 and 24 show the operations of the page mode and fast page mode accesses in the case of reading data, respectively. As shown in these figures, an access period for the ~ast page mode is half that for the page mode. The effect of the invention becomes more remarkable when many data are accessed.
According to the third preferred embodiment, the load of the hardware is reduced, because the system uses no cache memory.
A fourth preferred embodiment is now explained in conjunction with Figs. 25 to 29. In Fig. 25 showing an I/O map managed by a CPU, each pin with "*1", such as CE(0) and CE(1), is for 8 bit device, and the other pins CE(4), CE(5), and the like, are for 16 bit devices. Each bus connected to corresponding pin supports dynamic bus sizing. Double bus sizing is determined for each clock cycle. A slave or address decode logic circuit detects an existence of an 8 bit device.
2~ ~74~7 The CPU judges the size of data to be transferred, whether 8 bits (SIZE 8) or 16 bits (SIZE 16), to control the transmission. That is, for ins ance, two pieces of 8 bit data are coupled to form 16 bit data to be transmitted to a 16 bit device, as shown in Fig. 26. 32 bit data are divided into two segments of 16 bit data to be transmitted to the 16 bit device.
On the other hand, 16 and 32 bit data are divided into 2 and 4 of 8 bit data, respectively, to be transmitted to a 8 bit device, as shown in Fig. 27.
Fig~ 28 shows a read cycle for reading 32 bit data from a 16 bit device. In this case, data are not read until RDY
signal attains high level. The 32 bit data are divided into two segments of 16 bit data to be transferred twice, the operation being called a "multi-cycle."
Fig. 29 shows a read cycle for reading 16 bit data from a 8 bit device. In this cycle, 8 and 16 bit devices may be connected to each other by using the SIZE 8 pin. The 16 bit data are divided into two segments of 8 bit data to be transferred twice in the "multi-cycle." Above mentioned, operation is controlled by the CPU.
According to the fourth preferred embodiment, a program for accessing the memory becomes easy to be designed, because the CPU adjusts the length of data to be transmitted.
On the other hand, in the conventional system, dummy data (zero data) are added to original data to adjust the length of the original data, and as a result, the transfer speed is decreased.
2~.~7~3~1 A fifth preferred embodiment is now explained, in which the configuration of a memory is specified by a program without an address IC chip, so that the memory may be accessed by a CPU directly. The configuration of the memory is specified by a memory setting register of 32 bits. The configuration of the memory is defined by "ROW_SIZE," COL_SIZE" and "ARRAYS," as shown in Fig. 16, as follows:
ROW_SIZE<2 2 3> : number of bit for row address COL_SIZE<4:3> : number of bit for column address ARRAYS<5> : number of array REFRESH EN<6> : refresh enabling , where <n:m> and ~n> represent that the information is arranged in a range of ~m~th bit to ~n~th bit, and at ~n~th bit, respectively.
When the configuration of the memory is defined as follows in the memory setting register, the configuration becomes as shown in Fig. 30:
ROW_SIZE = 10 COL_SIZE = 9 AR~AYS = 2 On the other hand, an address specified by a program is processed to provide RAS and CAS signals by an MCU (Memory Control Unit), so that the memory is addressed in accordance with the RAS and CAS signals, as shown in Fig. 31. In this addressing process, if an area out of the actual memory space is addressed, an exceptional error signal is generated based on the 2~7~3~
memory configuration by the CPU, this function being called an "area protection break."
Next, the CPU of the 32 bit type according to the fifth preferred embodiment will be explained. The CP~ includes an instruction fetch unit (IFU3, an I/O control unit (IOU) and a memory control unit (MCU). The CPU has memory bus and I/O
spaces of 2G bytes.
In this embodiment, when data are written in a memory area with the address out of the actual memory, the current routine is transferred to an I/O error exceptional treatment in accordance with a break by an I/O error exception, as shown in Fig. 33. In this exceptional treatment routine, an arror message is generated, so that a user can find the error location by checking the instruction for accessing the memory or I/O
space and address data located around the instruction.
Fig. 34 shows the operation of a conventional system for the same processing as the fifth preferred embodiment, shown in Fig. 33. In the conventional system, a memory is addressed by a memory IC chip (address decoder), and therefore, it is not necessary to specify the configuration of the memory by a register. It is assumed that an instruction 200 is defective when data are written in a memory area with the address out of the actual memory. When the defective instruction is fetched by the ~PU, it is judged that the instruction does not exist there because the instruction is defective, as shown in Fig. 34.
After that, the current routine is transferred for non-21074~7 instruction exceptional treatment in accordance with the errorexception. In this exceptional treatment routine, an error message is generated to finish the program. It is possible to find that instruction 200 is not normal, based on the error message. However, the instruction is normal in a source program list, because the instruction is defective in processing.
Therefore, it is difficult to find the error (bug).
According to the fifth preferred embodiment, it is easy to debug the program, because the error message shows the position where the error has occurred. This system is succes~ful especially for a game computer, in which addresses are handles by using an assembler or C-language directl~.
BACRGROllND OF THE Il~ TION
The present invention relates to an information processing system, and more particularly to a game computer system processing both image and sound data.
In a computer system, a CPU and peripheral devices are connected with each other through control, address and data buses. The CPU is connected to a memory and I/O devices through memory and I/O buses, respectively. In such a system, the following instructions are repeated to transfer data from the memory to the I/O spaces (I/O devices) continuously:
* READ DATA FROM MEMOR~
* WRITE DATA TO I/O
In a general computer system, the following instruction for readin~ or writing is prepared after the current process has been completed.
A game computer system which works at a high speed includes a CPU that processes the following instruction while the current instruction is being in pxocess, this process being known as a DMA (Direct Memory Access) function. According to this system, data to be transmitted are accumulated on the memory bus, because the l/O bus transmits data slower than the memory bus. As a result, the computer system can not perform pipeline processing normally.
Accordingly, in one ~ype of conventional game computer 2~07~37 system, timing for transmitting data is controlled by a user program with NOP (NO Operation) instructions. That is, the following program is used to transfer data from the memory to the I/O space:
* READ DATA FROM MEMORY
* WRITE DATA TO I/O
* NOP
In this case, the transmission timing is adjusted by the NOP instruction after the data are written into the I/O
space.
The following program is used to transfer data from the I/O space to the memory:
* READ DATA FROM I/O
* NOP
* WRITE DATA TO MEMORY
According to the program, the data are transmitted from the CPU to the memory securely.
Recently, with development of high performance CPUs, peripheral devices must be accessed with exact timings which are controlled by a program.
Generally, in an information processing system, the configuration of a DRAM (dynamic random access memory) is different depending on the type of data to be processed and the capacity of the memory, that is, the DRAM is addressed for each 8 and 16 bits when 8 and 16 bit data are to be processed, respectively. Most conventional computer systems employ decode 2:l~7~3~
IC chips for generating addresses fitting a variety of memory configurations.
Fig. 1 shows a memory of 64K x 2 chip type, according to a conventional computer system. When address information is supplied to a decode IC, corresponding data in the memory are accessed by the decode IC. According to this system, the decode IC is necessary and the memory configurations are limited, and therefore, it is difficult to access a variety of memories having different configurations.
The memory (DRAM) is composed of plural memory cells each composed of a transistor and a capacitor to decrease its cost and to increase its integration rate. The DRAM is accessed by an address multiplex system to decrease the si~e of the system, as shown in Fig. 2. In this system, address signals are supplied to address terminals by a time di~ision system, as shown in Fig. 3.
The DRAM is accessed in a high speed access mode to increase the access speed. In this mode, a word line is selected in accordance with a row address to supply all data connected with the word line to corresponding sense amplifiers, and then one of the amplifiers is selected in accordance with a column address to obtain data to be accessed. After that, when the column address only is changed, data stored in another sense amplifier is accessed.
When data are read from a memory in a read cycle, the memory is accessed by repeating RAS (Row Addressing) and CAS
2~0~437 (Column addressing) cycles alternately, the cycle bein~ called an "MADR cycle," and the access system a "page mode access."
~ccording to this system, much data can not be accessed at a high speed~ this problem being serious for graphic data processing that needs to treat much continuous data.
Accordingly, another type of conventional computer systems employs a cache memory managed directly by a CPU, as shown in Fig. 5. The cache memory stores data read from a DRAM, so ~hat the CPU reads the data from the cache memory directly, not from the DRAM. If the cache memory stores no data to be accessed by the CPU, the CPU must accesses the DRAM. For that reason, the cache memory is r.ecessary to store enough data.
According to the conventional system, however, it is difficult to debug the program, because the CPU points to addresses in the cache memory, not in the main memory (DRAM~.
It is difficult to find the locations of program erroxs.
Further, the system needs an extra memory chip for the cache memory in addition to the main memory (DRAM), and therefore, the hardware becomes complicated in structure.
In the conventional computer system, when the CPU is connected to peripheral devices of different types of bit (width), data to be transmitted are adjusted in width by software. For instance, when data are transferred from an 8-bit device to a 16-bit device, eight zeros are added at the end of 8 bit data to be transferred, as shown in Fig. 6. On the other hand, when data are transferred from a 16-bit device to an 8-bit 2~7~37 device, the 16 bit data are divided into two pieces of 8 bit data to be transferred, as shown in Fig. 7. According to the conventional system, a program (software) must be designed in consideration of the width of data to be transmitted.
In general, an area out of a memory space is not addressed, when an application program is designed in a high-level language, because the memory is treated with variables.
On the other hand, in a system program or application program which is designed using a low-level language, such as an assembler language, an address out of the memory may be specified.
In the conventional system, if a nonexistent address space is addressed, an incomprehensible image is displayed on a CRT. For example, in a game computer system dealing with sound and image, a strange image is displayed on a screen if a nonexistent address of a memory is specified.
Fig. 8 shows a memory space of the conventional system. ~enerally, the memory space to be addressed by the CPU
is different from a space ()16 to (1000)16 for the actual memory (DRAM) region. In the conventional system, when the program specifies an address (3)16r an address decoder (address IC chip) analyzes the address as being an address (1000)l6, because the decoder ignores the addresses over the upper boundary address (1000)16, as shown in Fig. 9. Although no datum exists at address (3)161 the system judges as if predetermined data exist there.
21~7~37 According to the conventional system, however, when a strange image is displayed on the screen, i~ is ~ifficult to find the error location, because a programmer tends to guess that proper image data might have some errors, and therefore, the error can not be found in the worst case. In more detail, when a nonexistent memory area is accidentally specified, other data or instruction is broken, and therefore, an error occurs when the data or instruction is later accessed. Although an exceptional error may stop the processing when the instruction is broken, the error portion can not be found in debugging, because the error is based on the wrong addressing.
~UMMARY OF THE INV~NTI~N
Accordingly, it is an object of the present invention to provide an information processing system, in which the difference of data processing speeds between a memory bus and an I/O bus is adjusted by a CPU to ease the burden of a programmer.
It is another object of the present invention to provide an information processing system, in which a memory may be accessed flexibly to manage a variety of memory having different configurations.
It is another object of the present invention to provide an information processing system, in which a CPU may access a memory at a high speed without a cache memory.
25It is another object of the present invention to provide an information processing system, in which a variety of 21~37 types of peripheral devices may be managed easily.
It is still another object of the present invention to provide an information processing system, in which an addressing error may be found easily.
According to a first feature of the present invention, a wait state signal is inserted into a RDY signal to adjust the difference of the transfer speeds of memory and I/O buses, which are connected to a CPU.
According to a second feature of the present invention, an MCU is provided with configuration and refresh timer registers for specifying the configuration and the refresh cycle of a memory to be accessed, respectively.
According to a third feature of the present invention, an MCU (Memory Controller Unit~ divides an address signal into row and column addresses. The first row address is held when the same row address are supplied continuously so that a memory is accessed continuously only by changing the column address.
According to a fourth feature of the present invention, the width (number of bits) of data to be transmitted is adjusted to be compatible for a device to be accessed.
According to a fifth feature of the present invention, the configuration of a memory to be accessed is specified by a register. An error signal is generated when an area out of the actual memory area in a memory space is addressed, so that memory I/O error exceptional treatment is carried out.
21 0~37 BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is an explanatory diagram showing operation for addressing a memory using a decode IC, according to a conventional computer system.
Fig. 2 is an explanatory diagram showing a multiplexer system, according to the conventional computer system.
Fig. 3 is a timing chart showing operation for addressing the memory, according to the conventional system.
Fig. 4 is a timing chart showing a read cycle in a page mode, according to the conventional system.
Fig. 5 is an explanatory diagram showing operation for accessing the memory using a cache memory, according to the conventional system.
Figs. 6 and 7 are explanatory diagrams each showing operation for transmitting data, according to the conventional system.
Fig. 8 is a diagram illustrating a memory space, according to the conventional system.
Fig. 9 is a diagram showing operation for addressing the memory using an address decoder, according to the conventional system.
Fig. 10 is a block diagram illustrating a computer system according to the invention.
Fig. 11 is a diagram showing the address space of a CPU, according to a first preferred embodiment.
Fig. 12 is a timing chart showing operation of a basic 2~1~7437 3-3 bus cycle, according to the first preferred embodiment.
Fig. 13 is a timing chart showing operation of the basic 3-3 bus cycle including one wait state signal, according to the first preferred embodiment.
Fig. 14 is a block diagram illustrating the internal architecture of a CPU, according to a second preferred embodiment.
Fig. 15 is a diagram showing a memory map of the CPU, according to the second preferred embodiment.
Fig. 16 is a table showing specifications of memories, according to the second preferred embodiment.
Fig. 17A is a diagram illustrating the configuration of an MCU (Memory Control Unit), according to the second preferred embodiment.
Fig. 17B is a diagram illustrating the configuration of a memory specifying register, according to the second preferred embodiment.
Fig. 18 is a block diagram illustrating the architecture of a refresh timer, according to the second preferred embodiment.
Fig. 19 is a diagram showing a memory map and an address bit of a DRAM (64K x 16), accordi~g to the second preferred embodiment.
Fig. 20 is a diagram showing a memory map and an address bit of a DR~M (128K x 8), according to the second preferred embodiment.
21Q7~
Fig. 21 is a timing chart of a read cycle in a fast page mode, according to a third preferred embodiment.
Fig. 22 is a diagram illustrating ~he two-dimensional character arrangement of a main memory, according to the third preferred embodiment.
Fig. 23 is a diagram showing an access cycle in the page mode.
Fig. 24 is a diagram showing an access cycle in the fast page mode, according to the third preferred embodiment.
Fig. 25 is a diagram showing an I/O memory map of a CPU, according to a fourth preferred embodiment.
Figs. 26 and 27 are diagrams illustrating operation for transmitting th~ different types of data, according to the fourth preferred embodiment.
Figs. 28 and 29 are time charts showing the different types of read cycles, according to the fourth preferred embodiment.
Fig. 30 is a diagram illustrating the configuration of a memory, according to a fifth preferred embodiment.
Fig. 31 is an explanatory diagram illustrating operation for addressing the memory using an RAS (row address) and a CAS (column address), according to the fifth preferred embodiment.
Fig. 32 is a diagram showing the address map of a CPU, according to the fifth preferred embodiment.
Fig. 33 is a flow chart showing operation for 21~7~37 accessing the memory, which includes memory I/O error exceptional treatment, according to the fifth preferred embodiment.
Fig. 34 is a ~low chart showing operation for accessing ~he memory, which includes non-instruction exceptional treatment, according to the conventional system DETAILED D~3SCRIPTION OF qlHE~ TION
Fig. 10 shows a computer system of the inven~ion, which includes a game-software recording medium 100 such as a CD-ROM, a CPU 102 of the 32-bit type, a control ~mit 104 for mainly controlling transmission of image and sound data and interfacing peripheral devices to each other, an image data extension unit 106, an image data output unit, a sound data output unit 110, a video encoder unit 112, a VDP unit 114 and a TV display 116.
CPU 102, control unit 104, image data e~tension unit 106 and VDP unit 114 are provided with their own memories M-RAM, K-RAM, R-RAM and V-RAM, respectively.
CPU 102 directly controls a DRAM via a memory support, and performs communication through an I/O port to peripheral devices, that is called an I/O control function. CPU 102 includes a timer, a parallel I/O port and an interruption control system. CPU 102 writes display data into the VRAM, and the data are read by VDP unit 114. The display data are transmitted to video encoder unit 112 whereby the data are 21~7~37 displayed on the TV display 116.
Control unit 104 includes an SCSI controller to which image and sound data are supplied from CD-ROM 100 through an SCSI interface. The K-RAM buffers data supplied to the SCSI
S controller. Control unit 104 also includes a DRAM controller for reading data buffered in the K-RAM at a predetermined timing. In control unit 104, priority judgement i9 carried out for each dot of natural background image data. Control unit 104 transmits moving image data (full color/ pallet), which have been compressed, to image data extension unit 106 to extend the image data.
Video encoder unit 112 receives an output signal of the control unit. Video encoder unit 112 superimposes VDP image data, natural background image data and moving image data (full color, pallet) transmitted from VDP unit 114, control unit 104 and image data extension unit 108. Video encoder unit 112 performs color pallet reproducing, special effect processing, D/A converting and the like. Output data of video encoder unit 112 are encod~d into an NTSC signal by an external circuit.
ADPCM sound data recorded in CD-ROM 100 are buffered in the K-RAM and then transmitted to sound data output unit 110 under control of control unit 104. The sound data output unit reproduces the sound data.
Fig. ll shows the address space of a CPU according to a first preferred embodiment, which includes memory and I/O
spaces of 2G bytes. The CPU accesses the I/O space with some 21~r~43rl intervals to avoid jamming of a memory bus.
As shown in Fig. 12, it takes three bus-clocks (BCLK) to access the I/O port (I/O space), and the operation is finished in response to a high level RD~ signal. This operation S is called a l~basic 3-3 bus cycle.~ While the RDY signal is at low level, wait state signals may be inserted into the RDY
signal to adjust access timing of the I/O space.
When one wait state signal is inserted into the RDY
signal, as shown in Fig. 13, it takes four bus clocks to access the I/O space. This operation is called a "4-4 bus cycle.~
As described above, according to the first preferred embodiment, programmers can design a program without being conscious of access timing, because the CPU controls access timing by itself. As a result, memory space used for the program may be reduced.
Fig. 14 shows the internal architecture of a CPU
according to a second pre~erred embodiment. The architecture includes an instruction fetch unit (IFV) 120, an instruction execution unit (IEU) 122, an I/O control unit (IOU) 124 and a memory control unit (MCU) 126. MCU 126 generates all control signals to control a memory port connected to a main memory DRAM. In this architecture, data are treated for each eight bits, so that data are treated for each byte or integral byte multiples. In this system, one word is indicated by 4 bytes (32 bits).
The DRAM is composed of some memory arrays, the number 2~0~7 of words (depth in address direction) contained in each array being different depending on the depth in address direction of the chip. That is, for example, a "256 x n" type of DRAM has memory arrays each having 256k words. The number of chips forming each array is defined by the number of data ports of the DRAM.
Fig. 15 shows the DRAM of 256k-word size.
Fig. 16 shows specifications for different types of DRA~s. In this embodiment, different types of DR~Ms 64k x 16, 128k x 8, 256k x 4, 256k x 16, 512k x 8 and the like may be employed. Such memory types may be specified by a memory specifying register. These memories are controlled by the CPU
when the memory system information has been supplied to the MCU.
If such a memory system is used in a conventional system, a decode IC is necessary to decode data.
The system has a register in the MCU to specify the configuration of the memory to set a refresh time by a predetermined program. The register may be addressed in accordance with a special register transmitting instruction.
The register is mapped in a special hardware register region (bank 3, address 4-7), as shown in Fig. 17A. A memory specifying register region takes 32 bits (4 bytes) at the address 4 in the bank 3. An area for instructing refresh time is taken at the address 5 in the same bank. The content of the memory specifying register is as follows:
210743~
ROW_SIZE
000 8 bits 001 9 bits 010 10 bits 5011 11 bits 100 12 bits COL_SIZE (column size) 00 B bits 01 9 bits 10 10 bits 11 11 bits ARRAYS (array size) 0 1 array 1 2 arrays REFRESH_EN (refresh enable) 0 refresh disable 1 refresh enable The DRAM system is defined by the combination of "ROW_SIZE" and "COL_SIZE". For example, when the "ROW_SIZE" =
2 (= (010)2, that is, 10 bits) and "COL_SIZE" = 1 (= (01)2, that is, 9 bits), a DRAM of 512k x 8 (ROW x COL = 10 x 9) is instructed to be set as shown in the table of Fig. 16. Further, 2:La7~37 a type of a 1 array - 4 chips is specified when "ARRAYS = 0" is held in the register.
Next, refresh cycle operation of this system will be explained in conjunction with Fig. 1~. In general, when a DRAM
is not accessed in a predetermined period, data stored in the memory is erased. For that reason, it is necessary to refresh the memory (that is, to electrically activate it) at predetermined intervals. The MCU has a refresh timer which includes a frequency divider, a refresh timer register and a timer counter. The frequency divider divides the frequency of a system clock to generate a timer clock having a frequency of one thirty-second (1/32) that of the system clock. The timer counter receives timer clock signals. ~efresh cycle (time) is programmable and varies depending on the configuration of the DRAM.
The memory refresh operation is controlled by data stored in 0 to 6 bits regions of the refresh timer register, as shown in Fig. 16. The control operation is automatically carried out by the ports. When the memory specifying register pro~ides a refresh enable instruction, the refresh cycle is determined in accordance with contents of the timer counter and refresh timer register, whereby the memory is refreshed at predetermined intervals.
When the CPU supplies data to the refresh timer (bank 3, address 5), the data are written in the timer register. On the other hand, the CPU reads data from the timer counter of the 2~07~37 refresh timer. The timer register assumes a zero state after reset. Refresh operation is required at each time when the timer counter finishes counting (0 x 7F, that is 7F of hexadecimal notation). The timer counter continues to count the clocks for each timer clock cycle, and then the timer counter is initialized in accordance with data stored in the refresh timer r~gister when the counting is finished.
In order to assure that the DRAM on a memory port is refreshed at the rated timing, figures to be used for controlling a period of memory refresh cycle are loaded in the refresh register. The refresh timer register stores predetermined figure data, which are calculated by a program using a DRAM refresh period, a DRAM refresh cycle and a clock period of the timer clock. That is, the figure data are given by the followin~ equations.
REFRESH TIMER = 0 x 7F - CYCLE NUMBER
CYCLE NUMBER = REFRESH INTERVAL / CLOCK PERIOD
REFRESH INTERVAL = REFRESH PERIOD / REFRESH CYCLE NUMBER
The MCU employs a "CAS before RAS refresh system", so that address data are not necessary to be supplied to the D~AM
for each refresh cycle.
Next, how to address the memory by the MCU will be explained. When an address signal is supplied to the MCU, the signal is divided into row, column and array signals. The dividing method is different depending on the memory configuration, for example, a DRAM of 64 x 16 is addressed as 2~7~3~
shown in Fig. 7. An address bit system is given automatically when the type of the DRAM is determined, as follows:
ROW_SIZE = 0 COL_SIZE = 0 When "ARRAY = 0" is set in the register, the memory space has an area of 64K words (256K bytes), as shown in Fig.
19. The cross point of row and column address signals supplied from the MCU becomes an address point.
When a DRAM of 128K x 8 is used, the following 0 instructions are set in the memory setting register:
ROW_SIZE = 1 COL_SIZE = 0 In this case, the MCU forms row and column addresses of 8 and 9 bits, respectively, as shown in Fig. 20. "ARRAY = 1"
is set in the register, so that two arrays 1 and 0 are formed in the memory map, and the memory has an area of lM bytes (128K
words x 2).
Next, how to calculate the refresh time of the DRAM
will be explained. When refresh period, refresh cycle, external clock and the clock frequency of a time clock are determined to be 4ms, 256, 23ns and 736ns, respectively, refresh time is given as follows:
REFRESH INTERVAL = 4,000,00Ons / 256 = 115.625ns CYCLE = 15.625ns / 736ns = 21.229 REFRESH TIME = 0x7F - 21 = 106 (0x = 7F in hexadecimal) 2 :1~ r~ ~13 ~
While the calculated refresh time is set in the refresh timer register, the timer co~mter is refreshed in accordance with the refresh time.
The second preferred embodiment uses the computer system, shown in Fig. 10, used in the first preferred embodiment. In this embodiment, the MCU also has the function of a decode IC used in the conventional system. A memory configuration, and a memory refresh cycle which is different depending on the DRAM, are specified by programming.
A third preferred embodiment is now explained, in which a CPU may access a main memory at a high speed without a cache memory. In this embodiment, the CPU memori~es a first RAS
(Row Addressing) cycle so that data can be read continuously from the memory according only to a CAS (Column Addressing) cycle, as shown in Fig. 21. Therefore, the RAS cycle having a length of lBCLK may be omitted after starting of reading, it being called a "fast page mode access."
Next, the page mode access of the conventional system and a fast page mode access of the prefexred embodiment are now compared with each other in the following program of the C-language:
char a[100][2];
for (i=0; i<=99; i++)printf("%c",a[i][0];
2~ 0~3~
, where "printf" is a function including a read or write instruction to the memory or display. The above program means that odd characters in a two-dimensional character arrangement are displayed. In this program, "a" represents a DRAM of 16 bit shown in Fig. 22.
The odd characters are arranged at the lower bit side of the memory. The DRAM uses only one RAS, so that image data may be displayed only by changing the CAS in the fast page mode.
Figs. 23 and 24 show the operations of the page mode and fast page mode accesses in the case of reading data, respectively. As shown in these figures, an access period for the ~ast page mode is half that for the page mode. The effect of the invention becomes more remarkable when many data are accessed.
According to the third preferred embodiment, the load of the hardware is reduced, because the system uses no cache memory.
A fourth preferred embodiment is now explained in conjunction with Figs. 25 to 29. In Fig. 25 showing an I/O map managed by a CPU, each pin with "*1", such as CE(0) and CE(1), is for 8 bit device, and the other pins CE(4), CE(5), and the like, are for 16 bit devices. Each bus connected to corresponding pin supports dynamic bus sizing. Double bus sizing is determined for each clock cycle. A slave or address decode logic circuit detects an existence of an 8 bit device.
2~ ~74~7 The CPU judges the size of data to be transferred, whether 8 bits (SIZE 8) or 16 bits (SIZE 16), to control the transmission. That is, for ins ance, two pieces of 8 bit data are coupled to form 16 bit data to be transmitted to a 16 bit device, as shown in Fig. 26. 32 bit data are divided into two segments of 16 bit data to be transmitted to the 16 bit device.
On the other hand, 16 and 32 bit data are divided into 2 and 4 of 8 bit data, respectively, to be transmitted to a 8 bit device, as shown in Fig. 27.
Fig~ 28 shows a read cycle for reading 32 bit data from a 16 bit device. In this case, data are not read until RDY
signal attains high level. The 32 bit data are divided into two segments of 16 bit data to be transferred twice, the operation being called a "multi-cycle."
Fig. 29 shows a read cycle for reading 16 bit data from a 8 bit device. In this cycle, 8 and 16 bit devices may be connected to each other by using the SIZE 8 pin. The 16 bit data are divided into two segments of 8 bit data to be transferred twice in the "multi-cycle." Above mentioned, operation is controlled by the CPU.
According to the fourth preferred embodiment, a program for accessing the memory becomes easy to be designed, because the CPU adjusts the length of data to be transmitted.
On the other hand, in the conventional system, dummy data (zero data) are added to original data to adjust the length of the original data, and as a result, the transfer speed is decreased.
2~.~7~3~1 A fifth preferred embodiment is now explained, in which the configuration of a memory is specified by a program without an address IC chip, so that the memory may be accessed by a CPU directly. The configuration of the memory is specified by a memory setting register of 32 bits. The configuration of the memory is defined by "ROW_SIZE," COL_SIZE" and "ARRAYS," as shown in Fig. 16, as follows:
ROW_SIZE<2 2 3> : number of bit for row address COL_SIZE<4:3> : number of bit for column address ARRAYS<5> : number of array REFRESH EN<6> : refresh enabling , where <n:m> and ~n> represent that the information is arranged in a range of ~m~th bit to ~n~th bit, and at ~n~th bit, respectively.
When the configuration of the memory is defined as follows in the memory setting register, the configuration becomes as shown in Fig. 30:
ROW_SIZE = 10 COL_SIZE = 9 AR~AYS = 2 On the other hand, an address specified by a program is processed to provide RAS and CAS signals by an MCU (Memory Control Unit), so that the memory is addressed in accordance with the RAS and CAS signals, as shown in Fig. 31. In this addressing process, if an area out of the actual memory space is addressed, an exceptional error signal is generated based on the 2~7~3~
memory configuration by the CPU, this function being called an "area protection break."
Next, the CPU of the 32 bit type according to the fifth preferred embodiment will be explained. The CP~ includes an instruction fetch unit (IFU3, an I/O control unit (IOU) and a memory control unit (MCU). The CPU has memory bus and I/O
spaces of 2G bytes.
In this embodiment, when data are written in a memory area with the address out of the actual memory, the current routine is transferred to an I/O error exceptional treatment in accordance with a break by an I/O error exception, as shown in Fig. 33. In this exceptional treatment routine, an arror message is generated, so that a user can find the error location by checking the instruction for accessing the memory or I/O
space and address data located around the instruction.
Fig. 34 shows the operation of a conventional system for the same processing as the fifth preferred embodiment, shown in Fig. 33. In the conventional system, a memory is addressed by a memory IC chip (address decoder), and therefore, it is not necessary to specify the configuration of the memory by a register. It is assumed that an instruction 200 is defective when data are written in a memory area with the address out of the actual memory. When the defective instruction is fetched by the ~PU, it is judged that the instruction does not exist there because the instruction is defective, as shown in Fig. 34.
After that, the current routine is transferred for non-21074~7 instruction exceptional treatment in accordance with the errorexception. In this exceptional treatment routine, an error message is generated to finish the program. It is possible to find that instruction 200 is not normal, based on the error message. However, the instruction is normal in a source program list, because the instruction is defective in processing.
Therefore, it is difficult to find the error (bug).
According to the fifth preferred embodiment, it is easy to debug the program, because the error message shows the position where the error has occurred. This system is succes~ful especially for a game computer, in which addresses are handles by using an assembler or C-language directl~.
Claims (5)
1. An information processing system, comprising:
a CPU (Central Processing Unit) for controlling the system;
a memory for storing data;
an I/O device;
a memory bus for connecting the memory to the CPU;
an I/O bus for connecting the I/O device to the CPU;
means for generating RDY signal, according to which data are transmitted through the memory and I/O buses; and means for generating wait state signals to be inserted into the RDY signal;
wherein the CPU controls the number of wait state signals to adjust difference of transfer speeds of the memory and I/O buses.
a CPU (Central Processing Unit) for controlling the system;
a memory for storing data;
an I/O device;
a memory bus for connecting the memory to the CPU;
an I/O bus for connecting the I/O device to the CPU;
means for generating RDY signal, according to which data are transmitted through the memory and I/O buses; and means for generating wait state signals to be inserted into the RDY signal;
wherein the CPU controls the number of wait state signals to adjust difference of transfer speeds of the memory and I/O buses.
2. An information processing system, by which a variety types of memories are managed, comprising:
an MCU (Memory Controller Unit);
the MCU being provided with configuration and refresh timer registers for specifying the configuration and the refresh cycle of a memory to be accessed, respectively.
an MCU (Memory Controller Unit);
the MCU being provided with configuration and refresh timer registers for specifying the configuration and the refresh cycle of a memory to be accessed, respectively.
3. An information processing system, comprising:
a memory for storing data at predetermined addresses;
means for generating an address signal specifying data to be accessed in the memory;
an MCU (Memory Controller Unit) for dividing the address signal into row and column addresses; and means for holding the first row address of a series of data with the same row address so that the addresses of the series of data in the memory are addressed by changing only the column address after that continuously.
a memory for storing data at predetermined addresses;
means for generating an address signal specifying data to be accessed in the memory;
an MCU (Memory Controller Unit) for dividing the address signal into row and column addresses; and means for holding the first row address of a series of data with the same row address so that the addresses of the series of data in the memory are addressed by changing only the column address after that continuously.
4. An information processing system, comprising:
means for detecting a type of a device to which data are transmitted; and means responsive to the detecting means for adjusting the width (number of bits) of data to be transmitted to the device;
wherein the adjusting means divides or combines data to adjust the width of the data.
means for detecting a type of a device to which data are transmitted; and means responsive to the detecting means for adjusting the width (number of bits) of data to be transmitted to the device;
wherein the adjusting means divides or combines data to adjust the width of the data.
5. An information processing system, in which an actual memory area forms a part of a whole memory space, comprising:
a memory specifying register for specifying the configuration of a memory to be accessed;
means for generating an error signal when an area out of the actual memory area is addressed; and means responsive to the error signal for performing memory I/O error exceptional treatment.
a memory specifying register for specifying the configuration of a memory to be accessed;
means for generating an error signal when an area out of the actual memory area is addressed; and means responsive to the error signal for performing memory I/O error exceptional treatment.
Applications Claiming Priority (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28498392A JPH06180647A (en) | 1992-10-01 | 1992-10-01 | Central processing unit with bus transfer speed adjusting function |
| JP4-284984 | 1992-10-01 | ||
| JP28498692A JPH06180681A (en) | 1992-10-01 | 1992-10-01 | Central processing unit |
| JP4284987A JPH06180673A (en) | 1992-10-01 | 1992-10-01 | Information processor |
| JP4-284986 | 1992-10-01 | ||
| JP4-284983 | 1992-10-01 | ||
| JP4284984A JPH06180986A (en) | 1992-10-01 | 1992-10-01 | Memory controller unit |
| JP4-284987 | 1992-10-01 | ||
| JP4293767A JPH06180984A (en) | 1992-10-07 | 1992-10-07 | Central processing unit |
| JP4-293767 | 1992-10-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2107437A1 true CA2107437A1 (en) | 1994-04-02 |
Family
ID=27530739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002107437A Abandoned CA2107437A1 (en) | 1992-10-01 | 1993-09-30 | Information processing system |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5822753A (en) |
| EP (1) | EP0590967B1 (en) |
| CA (1) | CA2107437A1 (en) |
| DE (1) | DE69322051T2 (en) |
| TW (1) | TW390446U (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW390446U (en) * | 1992-10-01 | 2000-05-11 | Hudson Soft Co Ltd | Information processing system |
| JP4154010B2 (en) * | 1997-07-17 | 2008-09-24 | キヤノン株式会社 | Memory control device and memory control method |
| US6928653B1 (en) | 1997-11-06 | 2005-08-09 | United Video Properties, Inc. | Interactive electronic television program guide with database configurability |
| US6728862B1 (en) * | 2000-05-22 | 2004-04-27 | Gazelle Technology Corporation | Processor array and parallel data processing methods |
| JP2002023881A (en) * | 2000-07-12 | 2002-01-25 | Sony Corp | Information processor and information processing method and program storage medium |
| US7032119B2 (en) * | 2000-09-27 | 2006-04-18 | Amphus, Inc. | Dynamic power and workload management for multi-server system |
| US6889335B2 (en) * | 2001-04-07 | 2005-05-03 | Hewlett-Packard Development Company, L.P. | Memory controller receiver circuitry with tri-state noise immunity |
| US6633965B2 (en) * | 2001-04-07 | 2003-10-14 | Eric M. Rentschler | Memory controller with 1×/M× read capability |
| US6678811B2 (en) * | 2001-04-07 | 2004-01-13 | Hewlett-Packard Development Company, L.P. | Memory controller with 1X/MX write capability |
| US6625702B2 (en) * | 2001-04-07 | 2003-09-23 | Hewlett-Packard Development Company, L.P. | Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices |
| US20030196126A1 (en) * | 2002-04-11 | 2003-10-16 | Fung Henry T. | System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment |
| DE102005054347A1 (en) * | 2005-11-15 | 2007-05-24 | Atmel Duisburg Gmbh | Electronic circuit and method for operating an electronic circuit |
| US7539050B2 (en) * | 2006-11-22 | 2009-05-26 | Qimonda North America Corp. | Resistive memory including refresh operation |
| KR102036514B1 (en) * | 2015-07-13 | 2019-10-28 | 엘에스산전 주식회사 | Data access apparatus using memory device |
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| IT1142074B (en) * | 1981-11-24 | 1986-10-08 | Honeywell Inf Systems | DATA PROCESSING SYSTEM WITH AUTOMATIC ALLOCATION OF THE ADDRESS IN A MODULAR MEMORY |
| US4509113A (en) * | 1982-02-02 | 1985-04-02 | International Business Machines Corporation | Peripheral interface adapter circuit for use in I/O controller card having multiple modes of operation |
| EP0164735A3 (en) * | 1984-06-11 | 1988-11-09 | Nec Corporation | A microprocessor having a dynamic memory refresh circuit |
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| US5379400A (en) * | 1992-08-07 | 1995-01-03 | International Business Machines Corp. | Method and system for determining memory refresh rate |
| US5418924A (en) * | 1992-08-31 | 1995-05-23 | Hewlett-Packard Company | Memory controller with programmable timing |
| US5307320A (en) * | 1992-09-23 | 1994-04-26 | Intel Corporation | High integration DRAM controller |
| TW390446U (en) * | 1992-10-01 | 2000-05-11 | Hudson Soft Co Ltd | Information processing system |
| US5740404A (en) * | 1993-09-27 | 1998-04-14 | Hitachi America Limited | Digital signal processor with on-chip select decoder and wait state generator |
-
1993
- 1993-09-08 TW TW085200112U patent/TW390446U/en not_active IP Right Cessation
- 1993-09-29 EP EP93307737A patent/EP0590967B1/en not_active Expired - Lifetime
- 1993-09-29 DE DE69322051T patent/DE69322051T2/en not_active Expired - Fee Related
- 1993-09-30 CA CA002107437A patent/CA2107437A1/en not_active Abandoned
-
1997
- 1997-11-17 US US08/971,405 patent/US5822753A/en not_active Expired - Fee Related
-
1998
- 1998-05-27 US US09/084,385 patent/US6065132A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TW390446U (en) | 2000-05-11 |
| US6065132A (en) | 2000-05-16 |
| EP0590967B1 (en) | 1998-11-11 |
| US5822753A (en) | 1998-10-13 |
| DE69322051D1 (en) | 1998-12-17 |
| DE69322051T2 (en) | 1999-06-24 |
| EP0590967A1 (en) | 1994-04-06 |
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