CA2066611C - Error detection for fiber distributed interfaced optic link - Google Patents
Error detection for fiber distributed interfaced optic linkInfo
- Publication number
- CA2066611C CA2066611C CA002066611A CA2066611A CA2066611C CA 2066611 C CA2066611 C CA 2066611C CA 002066611 A CA002066611 A CA 002066611A CA 2066611 A CA2066611 A CA 2066611A CA 2066611 C CA2066611 C CA 2066611C
- Authority
- CA
- Canada
- Prior art keywords
- bits
- error
- check code
- data
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6575—Implementations based on combinatorial logic, e.g. Boolean circuits
Abstract
Error detection of digital data transmitted on an optic link (18a-18b) is accomplished by creating, before transmission, a check code comprising check bits that correspond to spaced one of the data bits forming the plurality of bits. The check code is then transmitted with the plurality of bits (Fig. 1) to a receiver (32), where the plurality of bits are used to create an error code in the same manner as the check code, the error and check codes compare, and an indication of error (64) generated when a miscompare is detected.
Description
WO91/04530 PCT/US90/05154 ~
ERROR DETECTION FOR FIBER DISTRIBUTED INTERFACED _OPTIC_LINK
BACKGROUND OF THE INVEMTION
The present invention relates qenerally to transmission of digital data. More particularly, the ; ;~
invention is a method and apparatus for error detection on such serial data transmission media as fiber optic links.
Communicating connections hetween various components of data processing equipment, e.q.~ the processor system itself and such peripherals as disk drives, are until `~ ~-recently usually effected by one or anotller form of `-~
electrically conductive media, i.e., metallic wires. -lS However, this form of communication connection is not without several problems. The physical makeup of the medium will often encounter electrical impedances of one type or another that place a limit on comm~nication speed. And, ;~
although data transmission speed can be overcome by various 20 techniques, such as transmitting data in parallel, other ~ -problems arise. For example, parallel d~ta tr~nsmissions ~ ~;
tend to create and/or exacerbate electlomag1l~tic radiation and cross-talk problems. -These and other reasons have led to the development of ``
various fiber optic materials for use as a data communications medium. Heretofore, data transmi.ssions using ~ ```
fiber optics were little used because early fiber optic material tended to be expensive and, therefore, economically non-competitive. However, recent advances in fiber optic materials have reduced the cost to the point t~lat fiber optics data~ communication can now compete realistically with conductive medium. Fiber optic material does not cause the electromagnetic radiation and cross talk problems encountered by metallic wiring. Further, fiber optic data 35 communication provides a better bandwidth (i~e.~ data can be; ~`
communicated faster), allows for lon~er lenqt~l of line with WO91/04~30 PCT/US90/05154 2Q~ S~ ~ 2 less signal attenuation, and reduces cable bulk over that of conductive medium. `~
However, irrespective of the particular communication medium needed, it is good practice to provide ;~
some form of detecting whether the received data transmitted was, in fact, transmitted correctly, i.e.~ error checking.
Recognizing the well-known phenomena th~t if anything can go wrong it will, results in use of vario~ls types of error detecting codes and techniques. Most error detection ;`;
techniques use some form of "red~lndancy," extra bits that form an error detection code (or error correction code) for transmission along with the informational data. The extra bit or bits can be used to detect errors that may llave occurred in the informational bits. The extra bit(s) are ;;~
15 used, when the transmitted data is received~ to determine if -the transmission~ corrupted the data. The simplistic form `~
of error chec~ing is parity, which adds to the end of a multibit data word a ONE or ZERO depending upon whether the number of ONEs of the data word is even or odd. ;~
While the various error-checking techniques -~
including parity chec~ing -- provide a modicum of confidence that received data is error free, as oppo~sed to no error checking at all, multiple errors, or adjacent bit errors, ` .:
may miss detection. To overcome these particular problems, more elaborate error checking (or correction) techniques are used, such as CRC check-sum methods, or fire co~e encoding.
However, these techniques can (and ~Isually do ~ to be effective) add a significant number of data bits to the transmitted information. The addition of extra bits to the transmitted information degrades the total bandwidth for information transmission.
~, . .
SUMMARY OF THE INVENTION
Therefore, the present invention provides an error ~ -checking techniq-le tllat uses a minimum ~lumber of extra bits (hereinafter~ "check code" bits) that attacll to the information bits covered by the error clleck. ~djacent bit , ~.,:;'~: :
, . '',; ~,`.-,.;
r 2 0 6 6 6 1 1 masking is minlmlzed by the manner ln whlch the check code ls created.
According to the method of the present lnventlon, a `~
packet of lnformatlon blts (whlch could be data or command or both) ls conceptually dlvlded lnto a plurallty of data bit groups. --~
Predetermined correspondlng bits from each of the data bit groups are associated with one another to create a check code for each ',.;"?~
such assoclatlon of blts. The information packet is transmitted serlally, immediately followed by the check code. At the -recelving end, an error code is developed from the lnformatlon ;~
packet in the same manner as the check code is created. The error and check code are then compared to one another, and an error slgnal generated if a mismatch is detected, indicating that an error may have occurred during transmisslon.
In the preferred ernbodiment of the invention, the `
. , .
lnformation packet ls twenty bits ln length. Each 4-bit nibble ;:
contributes a bit that is combined with correspondingly located ;~
bits of each other nibble to form a parity bit. The four parity `
bits so created form the check code for that information packet.
II1 an alternate embodiment of the lnventlon, the 20-bit information packet lncludes two ad~acent identification(ID) blts -`-that identify the packet as contalning either data or command ~ -lnformation. Corruption of these two bits, during transmlsslon could~cause erroneous lnterpretatlon of the content of the :
recelved packet. To minimize this potential problem, one of the ~ .
two blts is swapped wlth another of the blts in the lnformation packet before serial transmlssion thereof.
Several advantages of the present lnvention should now ,,,' ','.
be evldent to those skilled in thls art. One particular ls that -~;
the error checklng method of the present lnventlon, for flber ~;~
optlc serial transmlsslon of lnformatlon, uses a mlnimum-slzed check code. Thereby, informatlon transmission bandwldth is not -~
slgniflcantly affected, as lt would be if the check code size was larger. ~.
Yet another advantage of the present lnvention ls that the error detecting codes that cover the transmltted lnformatlon `~
are spatlally removed from the lnformation they cover. This advantage enhances the capablllty of detecting transmisslon errors.
According to a broad aspect of the invention there is provided a method for checklng for the occurrence of errors ln digital data packet contalning N serlally transmitted bits, the N
bits including two ad~acent bits indlcatlve of one of a plurallty of forms of the N bits, comprising the steps of~
swapping one of the two bit~s wlth one of the remalning N
blts; ;
creatlng a check code havlng at least one bit derlved from N/M blts occupying correspondlng blt positions of N/M e~ual-blt groups of the N bits;
serlally transmittlng the N bits together with the check :
code;
r~eceiving the N blts and check code, and creatlng from the received N blts an error code ln the same manner as the check code was created;
:~ .
comparlng the error and check codes to provide an indication of error when the error and check codes do not match. `
2066611 ~
4a 64157-378 , Accordlng to another broad aspect of the lnventlon there is provlded ln a data communlcatlon system for communlcatlng N-blt packets of dlgltal data, lncludlng at least two blts lndicatlve of one of a plurallty of data types, apparatus to detect the presence of data corruption that may occur durlng transmlsslon, the apparatus comprlsing:
first circult means for swapplng one of the two bits with one of the remainlng N bits, and includlng encoding means for creating a check code that ls derived from N~M blts that occupy corresponding blt posltions of N~M groups of the N blts;
transmlttlng means coupled to the flrst clrcult means for -receiving and serially transmitting the N blts and the check code ln a FDDI 4B/5B format;
recelving means coupled to recelve the 4B/5B encoded N bits and check code, including means to extract the N blts and the check code from the FDDI 4~5B format, and means for creating from the recelved N blts an error code in the same manner as the check code was created; and second circult means comparing the error and the check codes .-to provlde an indlcatlon of error when the error and the check does do not match.
According to another broad aspect of the lnventlon there is provided in a data communication system for communicating N-~ blt packets of dlgital data lncludlng at least two blts lndlcatlve : of one of a plurallty of data types, a method of detectlng the presence of data corruption may occur durlng transmlssion, the method comprlslng the steps of:
swapplng of one of the two blts wlth one of the 4b 64157-378 remalnlng N blts; `
creatlng a check code that ls derlved from N/M blts that occupy corresponding blt posltions of N~M groups of the N blts~
serlally transmlttlng the N bits and the check code ln a -FDDI 4B/5B format; j~-receivlng the 4B/-5B encoded N blts and check code, and extractlng the N blts and the check code from the FDDI 4B/5B
format; ~ `
creatlng from the recelved N bits an error code ln the same manner as the check code created; and comparing the error and the check codes to provide an lndicatlon of error when the error and check codes do not match.
These and other advantages and aspects of the present lnvent~lon wlll become evldent to those skllled ln the art upon a readlng of the following detailed descriptlon of the preferred embodlment of the lnventlon, which should be taken with the accompanying drawlngs. -.
BRIEF DESCRIPTION OF TH~ DRAWINGS
;
20 ~ Fig. l is a simpllfled block diagram lllustratlng use of ; the present lnventlon ln a data processlng system comprlsing at least a processor unit and an assoclated perlpheral device;
Fig. 2 is a more detalled block dlagram of the data ~;
trans~lssion apparatus lncorporatlng the error checklng method of the presènt inventlon;
~;: : .
Flg. 3 is a dlagrammatlc representatlon of the lnformatlon and error checklng code transmltted by the apparatus -.
~ ~ of Flg. 2;
, ::
:
2066611 :
4c 64157-378 -Flg. 4 ls an lllustration of the method used to create ~.
the check code used for detectlng errors occurrlng in transmlsslon of data; and Flg~ S ls an lllustratlon of a portlon of the circult ~`, used to create one blt of the check code lllustrated ln Flg. 4.
j~
DETAILED DESCRIPTION OF THE INVENTION
Referrlng now to the flgures, and wlth speclflc ;`
reference to Flg. 1, a data processlng system 10 is illustrated, lncluding a central processor unlt ~CPU)~ 12 and a perlpheral .
; ~ device 14, such as a dlsk drive storage unit. The devlce 14 couples to the CPU 12 by a communlcation llnk 16. In the preferred embodiment of the lnvention, communicatlon between the .
CPU l2 and the devlce 14 ls full `~
'`.
:
!' `:
-- duplex. This provides simultaneou.s datA tr~nsmissioll both ways between the CPU 12 and device 14~ Ising fiber optic `-~
media. Accordingly, the communication link 16 includes a pair of fiber optic cables 18a and 18b for respectively communicating data from and to the CPU 12, to and from the - device 14.
In addition, the communication of information between the CPU 12 and the device 14 preferably uses the physical standard described by ANSI standard X3T9.5, generally known 10 as the Fiber Distributed Data Interface (FDDI). As noted, -~
only the physical standard is used, and not the protocols described by the FDDI standard.
The CPU 12 and device 14 each respectively includes a fiber optic interface (~OI) 20, 22 that connects the communication link 16 to the other. Each ~OI 20, 22 operates to translate electrical si~nals to light signals when transmitting data, or to translate light signals to - electrical signals when receiving data, via the communication link.
20 ~ Referring now to Fig. 2, the F0l 20 of the CPU 18 is illustrated in greater detail. The ~0~ ~ of t.he device ~- 14 is of substantially identical design anci~ therefore, a description of the FOI 20 will be recogllized as also being a description of the FOI 22.
As Fig7 2 illustrates, the FOI 20 comprises a r'' transmitter section 30 and a receiver section 32.
Information packets of 20-bits~eacll~ as shown, containing either data or command information (b~lt not both), are applied to a 20-bit input bus 32 of the transmitter section ~ 30 30. The input bus 32 communicates tlle illformatioll packet to ,~ a multiplexer 34 and a code gener~tor 36. The code generator 36 is a combinatorial logic circ~lit th~t creates from the 20 bits applied thereto a 4-bit check code. The output of the code generator 36 communicates the check code to the multiplexer 34.
The multiplexer 34 operates to multiplex the 24 `~
bits of received data to three, one-byte (8 bit) segments .
:
~Q~6~-~ 6 that are coupled to a 4B/5B encoder 37. The ~R/5B encoder 37 encodes each 4-bit nibble of the received byte into S
bits, according to the FDDI standard mentiolled above, producing or each byte received a lO-bit data word.
S Each such lO-bit data word is comm~nicated to a non-returned-to-zero inverse (NRZI) encoder and serializer that, in effect, operates to convert the received data from parallel to serial form,;and then to convert it to the well known NRZI analog encoding (in which polarity transitions , represent a logical ONE, and the absence of A polarity ~ transition denotes a logical ZERO). ~rom tl~e NRZI encoder ~-- and serializer, each encoded lO-bit data word is ~`
communicated to a fiber optic link transmitter 40, converted r;
to light in conventional fashion, and applied to the fiber optics cable 18a.
At the other end of the fiber optic cable 18a is a `!
; receiver substantially in the form of the receiver 32. The communicated-light is received at a fiber optic link receiver 50 through a conventional arrangement of optic ; 2~0 detectlon, converting the received light to electrical energy. The output of the fiber optic link receiver 50 is communicated to a MRZI decoder and deseri~li7~er S~. The NRZI decoder recovers clock and dat~ signals from the received information.
The NRZI decoder 52 additionally operates to de-.
serialize the received analog inform~tion to 10-bit digital data words. Sequentially applied to a 4B/5B decoder 56, each~contiguous 5-bit groups of the dat~ words are converted back to their original 4-bit configl~ration~ and assembled as -i 30 an 8-bit byte. The 4B/SB decoder 56 A150 checks to determine the type of information in the received packet (i~e.~
whether FDDI data or command)~ atld si~nals the type to a packet assembly control checker 54 via sigllal lines 53. As noted above, three 8-bit bytes form eacll d~ta packet.
Thus~ the packet assembly control cl~ecke~ ~etet-mines whether, indeed~ in any sequencç of transmitted packets~ all .
WO91/04~30 PCT/US90/05154 ` - 2066611 were entirely received, as will be descri1~ed more ~1lly below.
Each 8-bit byte is then comm-~nic~ted from the 4B/5B decoder 56 to a demultiplexer 58 wheLe each 3 bytes received are assembled as a 20-bit data/comma1ld packet with 4 bits of check code. The 20-bit packet is applied to an oùtput bus, and to a code checker and ID comparator 62. The code checker and ID comparator 62 performs~three functions:
First, it creates a 4-bit error code from the received 20-bit packet in the same manner as the check~code by the code generator 36 (transmitter section 30). Second, the code checker 62 compares the error code so created with the . .
received *-bit check code. A favorable co~pare will provide a substantial confidence that the information transmitted by the transmitter 30 was correctly received by the receiver 32. A mismatch, however, will indicate the possibility that the transmitted data was incorrectly received, and an error flaq signal 64 will be asserted by the code checker 62.
Third, the code checker reads the two ID bits that identify ~whether the informatlon contained in the packet is data or - command information. These ID bits can tak~ Otl one of four states. However, only two of those states at~e valid.
Accordingly, if the 2 ID bits ass~1me an invalid statement~
the code checker 62 also wiLl assert the error flag signal ~ 64.
Illustrated in~Fig. 3 is a dia~r~mmatic representation of a typical 20-bit infoL-mation packet, together with the check code generated from that packet by the code generator 36. As Fig. 3 i].l~1str~tes~ the transmitted ol1tput of the multiplexer supplie.s the 20-bit information packet~ comprising bits D0-Dl~ ~nd the four bits of check code~ bits C0-C3. Bit Dl9 is the most significant bit (MSB)~ and bit C0 forms the least significant bit (LSB). This 24-bit packet~ aft¢r being encoded 4 bits to 5 bits (according to the FDDI standard mentioned above) is transmitted M~B first.
, .~ ' '.
ERROR DETECTION FOR FIBER DISTRIBUTED INTERFACED _OPTIC_LINK
BACKGROUND OF THE INVEMTION
The present invention relates qenerally to transmission of digital data. More particularly, the ; ;~
invention is a method and apparatus for error detection on such serial data transmission media as fiber optic links.
Communicating connections hetween various components of data processing equipment, e.q.~ the processor system itself and such peripherals as disk drives, are until `~ ~-recently usually effected by one or anotller form of `-~
electrically conductive media, i.e., metallic wires. -lS However, this form of communication connection is not without several problems. The physical makeup of the medium will often encounter electrical impedances of one type or another that place a limit on comm~nication speed. And, ;~
although data transmission speed can be overcome by various 20 techniques, such as transmitting data in parallel, other ~ -problems arise. For example, parallel d~ta tr~nsmissions ~ ~;
tend to create and/or exacerbate electlomag1l~tic radiation and cross-talk problems. -These and other reasons have led to the development of ``
various fiber optic materials for use as a data communications medium. Heretofore, data transmi.ssions using ~ ```
fiber optics were little used because early fiber optic material tended to be expensive and, therefore, economically non-competitive. However, recent advances in fiber optic materials have reduced the cost to the point t~lat fiber optics data~ communication can now compete realistically with conductive medium. Fiber optic material does not cause the electromagnetic radiation and cross talk problems encountered by metallic wiring. Further, fiber optic data 35 communication provides a better bandwidth (i~e.~ data can be; ~`
communicated faster), allows for lon~er lenqt~l of line with WO91/04~30 PCT/US90/05154 2Q~ S~ ~ 2 less signal attenuation, and reduces cable bulk over that of conductive medium. `~
However, irrespective of the particular communication medium needed, it is good practice to provide ;~
some form of detecting whether the received data transmitted was, in fact, transmitted correctly, i.e.~ error checking.
Recognizing the well-known phenomena th~t if anything can go wrong it will, results in use of vario~ls types of error detecting codes and techniques. Most error detection ;`;
techniques use some form of "red~lndancy," extra bits that form an error detection code (or error correction code) for transmission along with the informational data. The extra bit or bits can be used to detect errors that may llave occurred in the informational bits. The extra bit(s) are ;;~
15 used, when the transmitted data is received~ to determine if -the transmission~ corrupted the data. The simplistic form `~
of error chec~ing is parity, which adds to the end of a multibit data word a ONE or ZERO depending upon whether the number of ONEs of the data word is even or odd. ;~
While the various error-checking techniques -~
including parity chec~ing -- provide a modicum of confidence that received data is error free, as oppo~sed to no error checking at all, multiple errors, or adjacent bit errors, ` .:
may miss detection. To overcome these particular problems, more elaborate error checking (or correction) techniques are used, such as CRC check-sum methods, or fire co~e encoding.
However, these techniques can (and ~Isually do ~ to be effective) add a significant number of data bits to the transmitted information. The addition of extra bits to the transmitted information degrades the total bandwidth for information transmission.
~, . .
SUMMARY OF THE INVENTION
Therefore, the present invention provides an error ~ -checking techniq-le tllat uses a minimum ~lumber of extra bits (hereinafter~ "check code" bits) that attacll to the information bits covered by the error clleck. ~djacent bit , ~.,:;'~: :
, . '',; ~,`.-,.;
r 2 0 6 6 6 1 1 masking is minlmlzed by the manner ln whlch the check code ls created.
According to the method of the present lnventlon, a `~
packet of lnformatlon blts (whlch could be data or command or both) ls conceptually dlvlded lnto a plurallty of data bit groups. --~
Predetermined correspondlng bits from each of the data bit groups are associated with one another to create a check code for each ',.;"?~
such assoclatlon of blts. The information packet is transmitted serlally, immediately followed by the check code. At the -recelving end, an error code is developed from the lnformatlon ;~
packet in the same manner as the check code is created. The error and check code are then compared to one another, and an error slgnal generated if a mismatch is detected, indicating that an error may have occurred during transmisslon.
In the preferred ernbodiment of the invention, the `
. , .
lnformation packet ls twenty bits ln length. Each 4-bit nibble ;:
contributes a bit that is combined with correspondingly located ;~
bits of each other nibble to form a parity bit. The four parity `
bits so created form the check code for that information packet.
II1 an alternate embodiment of the lnventlon, the 20-bit information packet lncludes two ad~acent identification(ID) blts -`-that identify the packet as contalning either data or command ~ -lnformation. Corruption of these two bits, during transmlsslon could~cause erroneous lnterpretatlon of the content of the :
recelved packet. To minimize this potential problem, one of the ~ .
two blts is swapped wlth another of the blts in the lnformation packet before serial transmlssion thereof.
Several advantages of the present lnvention should now ,,,' ','.
be evldent to those skilled in thls art. One particular ls that -~;
the error checklng method of the present lnventlon, for flber ~;~
optlc serial transmlsslon of lnformatlon, uses a mlnimum-slzed check code. Thereby, informatlon transmission bandwldth is not -~
slgniflcantly affected, as lt would be if the check code size was larger. ~.
Yet another advantage of the present lnvention ls that the error detecting codes that cover the transmltted lnformatlon `~
are spatlally removed from the lnformation they cover. This advantage enhances the capablllty of detecting transmisslon errors.
According to a broad aspect of the invention there is provided a method for checklng for the occurrence of errors ln digital data packet contalning N serlally transmitted bits, the N
bits including two ad~acent bits indlcatlve of one of a plurallty of forms of the N bits, comprising the steps of~
swapping one of the two bit~s wlth one of the remalning N
blts; ;
creatlng a check code havlng at least one bit derlved from N/M blts occupying correspondlng blt positions of N/M e~ual-blt groups of the N bits;
serlally transmittlng the N bits together with the check :
code;
r~eceiving the N blts and check code, and creatlng from the received N blts an error code ln the same manner as the check code was created;
:~ .
comparlng the error and check codes to provide an indication of error when the error and check codes do not match. `
2066611 ~
4a 64157-378 , Accordlng to another broad aspect of the lnventlon there is provlded ln a data communlcatlon system for communlcatlng N-blt packets of dlgltal data, lncludlng at least two blts lndicatlve of one of a plurallty of data types, apparatus to detect the presence of data corruption that may occur durlng transmlsslon, the apparatus comprlsing:
first circult means for swapplng one of the two bits with one of the remainlng N bits, and includlng encoding means for creating a check code that ls derived from N~M blts that occupy corresponding blt posltions of N~M groups of the N blts;
transmlttlng means coupled to the flrst clrcult means for -receiving and serially transmitting the N blts and the check code ln a FDDI 4B/5B format;
recelving means coupled to recelve the 4B/5B encoded N bits and check code, including means to extract the N blts and the check code from the FDDI 4~5B format, and means for creating from the recelved N blts an error code in the same manner as the check code was created; and second circult means comparing the error and the check codes .-to provlde an indlcatlon of error when the error and the check does do not match.
According to another broad aspect of the lnventlon there is provided in a data communication system for communicating N-~ blt packets of dlgital data lncludlng at least two blts lndlcatlve : of one of a plurallty of data types, a method of detectlng the presence of data corruption may occur durlng transmlssion, the method comprlslng the steps of:
swapplng of one of the two blts wlth one of the 4b 64157-378 remalnlng N blts; `
creatlng a check code that ls derlved from N/M blts that occupy corresponding blt posltions of N~M groups of the N blts~
serlally transmlttlng the N bits and the check code ln a -FDDI 4B/5B format; j~-receivlng the 4B/-5B encoded N blts and check code, and extractlng the N blts and the check code from the FDDI 4B/5B
format; ~ `
creatlng from the recelved N bits an error code ln the same manner as the check code created; and comparing the error and the check codes to provide an lndicatlon of error when the error and check codes do not match.
These and other advantages and aspects of the present lnvent~lon wlll become evldent to those skllled ln the art upon a readlng of the following detailed descriptlon of the preferred embodlment of the lnventlon, which should be taken with the accompanying drawlngs. -.
BRIEF DESCRIPTION OF TH~ DRAWINGS
;
20 ~ Fig. l is a simpllfled block diagram lllustratlng use of ; the present lnventlon ln a data processlng system comprlsing at least a processor unit and an assoclated perlpheral device;
Fig. 2 is a more detalled block dlagram of the data ~;
trans~lssion apparatus lncorporatlng the error checklng method of the presènt inventlon;
~;: : .
Flg. 3 is a dlagrammatlc representatlon of the lnformatlon and error checklng code transmltted by the apparatus -.
~ ~ of Flg. 2;
, ::
:
2066611 :
4c 64157-378 -Flg. 4 ls an lllustration of the method used to create ~.
the check code used for detectlng errors occurrlng in transmlsslon of data; and Flg~ S ls an lllustratlon of a portlon of the circult ~`, used to create one blt of the check code lllustrated ln Flg. 4.
j~
DETAILED DESCRIPTION OF THE INVENTION
Referrlng now to the flgures, and wlth speclflc ;`
reference to Flg. 1, a data processlng system 10 is illustrated, lncluding a central processor unlt ~CPU)~ 12 and a perlpheral .
; ~ device 14, such as a dlsk drive storage unit. The devlce 14 couples to the CPU 12 by a communlcation llnk 16. In the preferred embodiment of the lnvention, communicatlon between the .
CPU l2 and the devlce 14 ls full `~
'`.
:
!' `:
-- duplex. This provides simultaneou.s datA tr~nsmissioll both ways between the CPU 12 and device 14~ Ising fiber optic `-~
media. Accordingly, the communication link 16 includes a pair of fiber optic cables 18a and 18b for respectively communicating data from and to the CPU 12, to and from the - device 14.
In addition, the communication of information between the CPU 12 and the device 14 preferably uses the physical standard described by ANSI standard X3T9.5, generally known 10 as the Fiber Distributed Data Interface (FDDI). As noted, -~
only the physical standard is used, and not the protocols described by the FDDI standard.
The CPU 12 and device 14 each respectively includes a fiber optic interface (~OI) 20, 22 that connects the communication link 16 to the other. Each ~OI 20, 22 operates to translate electrical si~nals to light signals when transmitting data, or to translate light signals to - electrical signals when receiving data, via the communication link.
20 ~ Referring now to Fig. 2, the F0l 20 of the CPU 18 is illustrated in greater detail. The ~0~ ~ of t.he device ~- 14 is of substantially identical design anci~ therefore, a description of the FOI 20 will be recogllized as also being a description of the FOI 22.
As Fig7 2 illustrates, the FOI 20 comprises a r'' transmitter section 30 and a receiver section 32.
Information packets of 20-bits~eacll~ as shown, containing either data or command information (b~lt not both), are applied to a 20-bit input bus 32 of the transmitter section ~ 30 30. The input bus 32 communicates tlle illformatioll packet to ,~ a multiplexer 34 and a code gener~tor 36. The code generator 36 is a combinatorial logic circ~lit th~t creates from the 20 bits applied thereto a 4-bit check code. The output of the code generator 36 communicates the check code to the multiplexer 34.
The multiplexer 34 operates to multiplex the 24 `~
bits of received data to three, one-byte (8 bit) segments .
:
~Q~6~-~ 6 that are coupled to a 4B/5B encoder 37. The ~R/5B encoder 37 encodes each 4-bit nibble of the received byte into S
bits, according to the FDDI standard mentiolled above, producing or each byte received a lO-bit data word.
S Each such lO-bit data word is comm~nicated to a non-returned-to-zero inverse (NRZI) encoder and serializer that, in effect, operates to convert the received data from parallel to serial form,;and then to convert it to the well known NRZI analog encoding (in which polarity transitions , represent a logical ONE, and the absence of A polarity ~ transition denotes a logical ZERO). ~rom tl~e NRZI encoder ~-- and serializer, each encoded lO-bit data word is ~`
communicated to a fiber optic link transmitter 40, converted r;
to light in conventional fashion, and applied to the fiber optics cable 18a.
At the other end of the fiber optic cable 18a is a `!
; receiver substantially in the form of the receiver 32. The communicated-light is received at a fiber optic link receiver 50 through a conventional arrangement of optic ; 2~0 detectlon, converting the received light to electrical energy. The output of the fiber optic link receiver 50 is communicated to a MRZI decoder and deseri~li7~er S~. The NRZI decoder recovers clock and dat~ signals from the received information.
The NRZI decoder 52 additionally operates to de-.
serialize the received analog inform~tion to 10-bit digital data words. Sequentially applied to a 4B/5B decoder 56, each~contiguous 5-bit groups of the dat~ words are converted back to their original 4-bit configl~ration~ and assembled as -i 30 an 8-bit byte. The 4B/SB decoder 56 A150 checks to determine the type of information in the received packet (i~e.~
whether FDDI data or command)~ atld si~nals the type to a packet assembly control checker 54 via sigllal lines 53. As noted above, three 8-bit bytes form eacll d~ta packet.
Thus~ the packet assembly control cl~ecke~ ~etet-mines whether, indeed~ in any sequencç of transmitted packets~ all .
WO91/04~30 PCT/US90/05154 ` - 2066611 were entirely received, as will be descri1~ed more ~1lly below.
Each 8-bit byte is then comm-~nic~ted from the 4B/5B decoder 56 to a demultiplexer 58 wheLe each 3 bytes received are assembled as a 20-bit data/comma1ld packet with 4 bits of check code. The 20-bit packet is applied to an oùtput bus, and to a code checker and ID comparator 62. The code checker and ID comparator 62 performs~three functions:
First, it creates a 4-bit error code from the received 20-bit packet in the same manner as the check~code by the code generator 36 (transmitter section 30). Second, the code checker 62 compares the error code so created with the . .
received *-bit check code. A favorable co~pare will provide a substantial confidence that the information transmitted by the transmitter 30 was correctly received by the receiver 32. A mismatch, however, will indicate the possibility that the transmitted data was incorrectly received, and an error flaq signal 64 will be asserted by the code checker 62.
Third, the code checker reads the two ID bits that identify ~whether the informatlon contained in the packet is data or - command information. These ID bits can tak~ Otl one of four states. However, only two of those states at~e valid.
Accordingly, if the 2 ID bits ass~1me an invalid statement~
the code checker 62 also wiLl assert the error flag signal ~ 64.
Illustrated in~Fig. 3 is a dia~r~mmatic representation of a typical 20-bit infoL-mation packet, together with the check code generated from that packet by the code generator 36. As Fig. 3 i].l~1str~tes~ the transmitted ol1tput of the multiplexer supplie.s the 20-bit information packet~ comprising bits D0-Dl~ ~nd the four bits of check code~ bits C0-C3. Bit Dl9 is the most significant bit (MSB)~ and bit C0 forms the least significant bit (LSB). This 24-bit packet~ aft¢r being encoded 4 bits to 5 bits (according to the FDDI standard mentioned above) is transmitted M~B first.
, .~ ' '.
As noted above, two blts of the 20-blt informatlon packet are used to identify whether the lnformation contalned in the packet ls data or command. These two blts are blts Dl9 and D18. If blts D19, D18 are a "00," the informatlon packet contalns command lnformatlon; conversely, lf these bits are a "11," the informatlon packet contains data information. If the blts Dl9, D18 are a "01" or "lO" it is assumed that a transmission error has occurred because these are invalid states for these data bits.
Considering that lt is not uncommon for ad~acent bits to incur slmilar errors, and as an additional fault protectlon technlque, one of the data bits Dl9, D18 is swapped with one of ;
the other~bits of the information packet. Thus, the data bit D6 is swapped wlth the data bit D18 in the multiplexer 34. This is done merely by auspiclous wirlng connections in the circult used ``~
to form the code multiplexer 34. The swapped blts are returned to ~;
thelr normal locations in the packet by the demultiplexer 58.
Refe~rring now to Fig. 4, lllustrated therein is the ~
manner in whlch the check code is generated by the generator 36. ;^
The bitæ of the 20-bit information packet that are received by the code generator 36 are conceptually grouped as 4-blt nibbles 72, ~`
73, 74, 75, 76, 77, 78, 79, 80. After the swap of the data blts `
D18 and D6, blts of corresponding blt posltlons (82, 83, 84, 85, 86, 87, 88) of each sequentlal 4-bit nlbble 72, 73, 74, 75, 76, 77, 78, 79, 80 are assoclated for generatlng a parlty bit that, together wlth the other parity blts of the other assoclated, correspondlng blts, form the 4-bit check code. Thus, for example, the data blts Dl9, D15, Dll, D7 and D3 m blt posltlons 82 are used to create a parlty blt that forms the check bit C3. Even parlty .,".....
2066611 ~::
8a 64157-378 ls used.
.
In slmilar fashion, a parlty bit generatlon over the .
data blts D18 (whlch ls swapped posltlon ln the packet wlth data blt D6 as described above), D14, D10, D6, and D2 develops the , check bit: C2. The remaining data bits are used in similar faæhion .:
..~
to generate the check code bits Cl and C0. ~:
As lndicated, the transmltter sectlon 30 receives data , ln the form of 20 bit lnformation packets. Those 20 `-.
:.
"
~, . .
':
~: . . ``,`
`'.
W O 91/04530 PC~r/US90/05154 bits are used to create the check code compri sins~ check code C0-C3 (Fig. 3) in the following manner: Conceptllally, each of the 4~bit "nibbles" of the information packet 70 are arranged in the columns 72,-80~ as illustrated in Fig. 4.
5 So arranged (with the data bits D6 and D18 of the information packet swapped~ as described above~ and indicated in Fig. 4), the data bits of the packet 70 form four rows 82-88. Thus, for example, the row 82 contains corresponding data bits from each of the five nibbles of the information packet 70, i . e, data bits Dl9 ~ D15, Dll ~ D7 ~ and D3. A parity bit (preferably, even parity) is generated for the data bits of each of the rows 82-88 that respectively become the check code bits C3-C0 of the check code .!
The parity generation uses conventional combinatorial logic techniques carry o~lt an excl~lsive-oring of each data bit with the corresponding other data bits in the~ row (e.g. ,~ row 82 ) . For example~ Fig. 5 illustrates a portlon of the combinatorial logic that makes up tlle code generator 36 ( Fig. 1 ) for generating parity ( i . e . ~ the check code bit C3 ) from the data bits Dl9 ~ D15 ~ D11~ D7 ~ and D3 of the informational packet 70. The circ~itry ~ at develops the check code bits C2~ Cl and C~ is s~lbstalltially identical ( except for the swap of bits D18, D6 ~ referred to above ) .
As Fig. 5 illustrates~ EXCLUSIVE-OR gates 36a, 36b, 36c, and 36d form that section of the code generator 36 that creates .
the check code bit C3 from bits Dl9 . D15 ~ Dl l; D7, D3 .
Turning now to Fig. 6, the packst assembly control checker 54 (Fig. 1) is illustrated in greater detail. As shown, the packet assembly control cllecker 54 includes three D-type flip-flops 90, 92, and 94 arranged in a shift register config~tration to receive~ at the c~ oc)c inp~lt of each, a FDDI data strobe signal from th~ 4BJ5B decoder 56 of the receiver 32 (Fig. 1). Connected to the preset (PR) inputs of the flip-flops go, a2 and tl~e clear (CL) inp~lt of -, the flip-flop 94, by a resistance R~ is a positive voltage so~rce Vcc.
WO91/04530 PCT/US~0/051~4 6~ lo The packet assembly control c]leckel- 5~ also includes a J/K flip-flop 96, whose preset (PR) input is also connected to the Vcc trough the resistor R. As will be seen, the J/K flip flop 96 functions to latcll and hold an error signal, producing therefrom an error fl~ indicative thereo.
The operation of the packet assembly control checker 54 is based on the requirement that there be transmitted three (lO-bit) data words for every packet. As the serial information is received and converted from (NRZI) anaIog to digital form by the NRZI d~ecoder 52, it is reassembled into the FDDI encoded lO-bit data words. Each reassembled data word is applied to the 4B/SB decoder S6.
The decoder 56 asserts the FDDI data strobe signal (communicated on one of the two strobe lines 53) for each received~data word.
Digressing a moment, whsn the transmitter section 30 of the FOI 20 is not sendin~ information packets, it is au~tonomously sending sync bytes at a regular rate (the same rate as data transmission). This ensures that t~le clocX of the receiver section 32 remains in syncllrolliz~tion. Each received sync byte is detected as s~lch ~y the 4B/5B decoder 56, and the FDDI command strobe sign~l is asserted and communicated on the other of the two signal lines 53 to the 2~5 packet assembly control checker 54. The sync byte is not fo~rwarded to the demultiplexer 58.
The packet assembly control checker 54 receives these two FDDI strobes (data and command)~ alld the FDDI data strobe is, in effect, counted by the shift register 30 ~ arrangement 9~, 92 and q4 as follows:
Assume that no packets have been transmitted, ; resulting in transmission of one or more sync bytes by the transmitter section of one of tl-e FOIs 20,22, and received " ~ .
by the recelver section 32 of the other. The decoder 56 of the receiver section 32 has issued~ or each received sync byte, a FDDI command strobe~ which is co~lpled via the NOR
gate lOO to preset the flip-flop 94. As ~ ~esult, the D
- .
WO91/04~30 PCT~US90/OS154 `-`;
11 2B66G11 :~
input of the flip-flop 9O receives a log.ic ~NE a.sserted by the Q output of the flip flop 94; the D .inp~lts of the flip- ~
flops 92 and 94 receive logic ZERO s. ~`!`;
- Assume ~ow that the receiver 32 ~egi~-s receiving transmitted packets. The FDDI data str~be is asserted for each data word of the received packets. The first occurrence of the FDDI data strobe will ca~lse t3-e flip-flop 90 to be set to a ONE, while the flip-flop 94 is set to a ~i~
ZERO ~flip-flop 92 remains a ZERO). The second occurrence of FDDI data strobe will cause the flip-flop 92 to be set to a ONE, while flip flop 94 rem~ins ZERO and flip flop 90 is reset to ZERO. As can be seen~ ~he third FDDI data strobe will reset the flip-flop 92 to a ZERO~ and set the flip-flop 94 to a ONE. In effect, a logic ONE h2- ~een shifted into~ and through the flip-flop chain 90, 92, ~4. As a result of this shift operation~ the Q O~ltp~it of the flip-flop 94 is set to a logic ONE, and the ~ output is set to a logic ZERO. With the Q output applied to the J input of the J/K flip flop 96, clocking of this flip-flop is inhibited ;`
20 or~reasons that wiLl be made clear below. This process ;~
; ~
continues for each packet received~ ~Intil ~ll packets have been sent. Termination of communic~tion of ~ackets will restllt in transmission of sync bytes until anotller packet is sent. Thus~ after receipt of three, or any m~lltiple of three~ data words, the J input of the J/K flip-flop 96 will have a logic ZERO applied its J inpt~t. Receipt of an FDDI
, command stro~e signal at the clock of the flip flop 96 will be ignored~ and the Q output of the flip flop 96 will remain at ZERO.
However, if at any time the F~DI command strobe is asserted (i.e., a logic ONE~ at the J inp~lt of the JfK, indicating that something other than thIee~ or a multiple of `~
three data~words was not received ~efore A sync ~yte, the Q
~ output of the J/K flip-flop 96 will be set to a OME~
- ~ ~ 35 asserting (and latclling) the ERROR FL~G~ Setting the ERROR
FL~G indicates the possibility o lo~ss of a packet in .
~ . ~
~6~ 12 ~
transmission ~Ipstream of the 4B/5B/ decode~ 56~ thereby -~
providing a form of fault isolation.
A system RESET command can be gener~ted to reset the packet assembly control checker 54 ~ia the OR gate 100 (to the flip flop 90-94) and the INVERTOR 102 (for flip flop :~
96). , ~`
,~ The transmitter,"receiver pair (30,~32) that forms ....
the fiber optic interface may be constructed from commercially available, off-the-shelf elements. ~or example, the 4B/5B encoder 36 and NRZ~I encoder 38 of the ~rèceiver 30, and the 4B/5B decoder 56 and NRZI decoder 52, "~
are separately sold as single integrated cIrc~lit packaged devices by Advanced Micro Devices, 9OI Thompson Place, Sunnyvale,~ California 94088 ~Inder the part n~lmbers AM7968 and AM7969, respectively. These devicefi are constr~lcted to generate,~autonomously, the sync byte described above when not transmitting packets.
Similarly, the fiber optic link transmitter 50 and fiber optic link receiver 52 are conventional electro-optic 20~ d`e~vlceo conotructed to convert electrical energy to light ;~
s~ energy,~or b~ack.
The multiplexer 34 and dem~lltipIexer 56 are of convent~ional design. They are each constructed and configured, for example, to include a state machine (not ~; ~ 25; shown) that contro;ls a~conventlonal m~lltiplex~ demultiplex circui~t to perform~the~operations required of the ?~
mutiplexer, demuLtiplexer 34, 56, respectively. The system provideo a clock (CLK) signal for syIlchrono~ls operation `~
thereof, and a control (CTL) signal to various control ~-functions that may need such signals.
' :~ : ' ` ., , ., '':~:
,
Considering that lt is not uncommon for ad~acent bits to incur slmilar errors, and as an additional fault protectlon technlque, one of the data bits Dl9, D18 is swapped with one of ;
the other~bits of the information packet. Thus, the data bit D6 is swapped wlth the data bit D18 in the multiplexer 34. This is done merely by auspiclous wirlng connections in the circult used ``~
to form the code multiplexer 34. The swapped blts are returned to ~;
thelr normal locations in the packet by the demultiplexer 58.
Refe~rring now to Fig. 4, lllustrated therein is the ~
manner in whlch the check code is generated by the generator 36. ;^
The bitæ of the 20-bit information packet that are received by the code generator 36 are conceptually grouped as 4-blt nibbles 72, ~`
73, 74, 75, 76, 77, 78, 79, 80. After the swap of the data blts `
D18 and D6, blts of corresponding blt posltlons (82, 83, 84, 85, 86, 87, 88) of each sequentlal 4-bit nlbble 72, 73, 74, 75, 76, 77, 78, 79, 80 are assoclated for generatlng a parlty bit that, together wlth the other parity blts of the other assoclated, correspondlng blts, form the 4-bit check code. Thus, for example, the data blts Dl9, D15, Dll, D7 and D3 m blt posltlons 82 are used to create a parlty blt that forms the check bit C3. Even parlty .,".....
2066611 ~::
8a 64157-378 ls used.
.
In slmilar fashion, a parlty bit generatlon over the .
data blts D18 (whlch ls swapped posltlon ln the packet wlth data blt D6 as described above), D14, D10, D6, and D2 develops the , check bit: C2. The remaining data bits are used in similar faæhion .:
..~
to generate the check code bits Cl and C0. ~:
As lndicated, the transmltter sectlon 30 receives data , ln the form of 20 bit lnformation packets. Those 20 `-.
:.
"
~, . .
':
~: . . ``,`
`'.
W O 91/04530 PC~r/US90/05154 bits are used to create the check code compri sins~ check code C0-C3 (Fig. 3) in the following manner: Conceptllally, each of the 4~bit "nibbles" of the information packet 70 are arranged in the columns 72,-80~ as illustrated in Fig. 4.
5 So arranged (with the data bits D6 and D18 of the information packet swapped~ as described above~ and indicated in Fig. 4), the data bits of the packet 70 form four rows 82-88. Thus, for example, the row 82 contains corresponding data bits from each of the five nibbles of the information packet 70, i . e, data bits Dl9 ~ D15, Dll ~ D7 ~ and D3. A parity bit (preferably, even parity) is generated for the data bits of each of the rows 82-88 that respectively become the check code bits C3-C0 of the check code .!
The parity generation uses conventional combinatorial logic techniques carry o~lt an excl~lsive-oring of each data bit with the corresponding other data bits in the~ row (e.g. ,~ row 82 ) . For example~ Fig. 5 illustrates a portlon of the combinatorial logic that makes up tlle code generator 36 ( Fig. 1 ) for generating parity ( i . e . ~ the check code bit C3 ) from the data bits Dl9 ~ D15 ~ D11~ D7 ~ and D3 of the informational packet 70. The circ~itry ~ at develops the check code bits C2~ Cl and C~ is s~lbstalltially identical ( except for the swap of bits D18, D6 ~ referred to above ) .
As Fig. 5 illustrates~ EXCLUSIVE-OR gates 36a, 36b, 36c, and 36d form that section of the code generator 36 that creates .
the check code bit C3 from bits Dl9 . D15 ~ Dl l; D7, D3 .
Turning now to Fig. 6, the packst assembly control checker 54 (Fig. 1) is illustrated in greater detail. As shown, the packet assembly control cllecker 54 includes three D-type flip-flops 90, 92, and 94 arranged in a shift register config~tration to receive~ at the c~ oc)c inp~lt of each, a FDDI data strobe signal from th~ 4BJ5B decoder 56 of the receiver 32 (Fig. 1). Connected to the preset (PR) inputs of the flip-flops go, a2 and tl~e clear (CL) inp~lt of -, the flip-flop 94, by a resistance R~ is a positive voltage so~rce Vcc.
WO91/04530 PCT/US~0/051~4 6~ lo The packet assembly control c]leckel- 5~ also includes a J/K flip-flop 96, whose preset (PR) input is also connected to the Vcc trough the resistor R. As will be seen, the J/K flip flop 96 functions to latcll and hold an error signal, producing therefrom an error fl~ indicative thereo.
The operation of the packet assembly control checker 54 is based on the requirement that there be transmitted three (lO-bit) data words for every packet. As the serial information is received and converted from (NRZI) anaIog to digital form by the NRZI d~ecoder 52, it is reassembled into the FDDI encoded lO-bit data words. Each reassembled data word is applied to the 4B/SB decoder S6.
The decoder 56 asserts the FDDI data strobe signal (communicated on one of the two strobe lines 53) for each received~data word.
Digressing a moment, whsn the transmitter section 30 of the FOI 20 is not sendin~ information packets, it is au~tonomously sending sync bytes at a regular rate (the same rate as data transmission). This ensures that t~le clocX of the receiver section 32 remains in syncllrolliz~tion. Each received sync byte is detected as s~lch ~y the 4B/5B decoder 56, and the FDDI command strobe sign~l is asserted and communicated on the other of the two signal lines 53 to the 2~5 packet assembly control checker 54. The sync byte is not fo~rwarded to the demultiplexer 58.
The packet assembly control checker 54 receives these two FDDI strobes (data and command)~ alld the FDDI data strobe is, in effect, counted by the shift register 30 ~ arrangement 9~, 92 and q4 as follows:
Assume that no packets have been transmitted, ; resulting in transmission of one or more sync bytes by the transmitter section of one of tl-e FOIs 20,22, and received " ~ .
by the recelver section 32 of the other. The decoder 56 of the receiver section 32 has issued~ or each received sync byte, a FDDI command strobe~ which is co~lpled via the NOR
gate lOO to preset the flip-flop 94. As ~ ~esult, the D
- .
WO91/04~30 PCT~US90/OS154 `-`;
11 2B66G11 :~
input of the flip-flop 9O receives a log.ic ~NE a.sserted by the Q output of the flip flop 94; the D .inp~lts of the flip- ~
flops 92 and 94 receive logic ZERO s. ~`!`;
- Assume ~ow that the receiver 32 ~egi~-s receiving transmitted packets. The FDDI data str~be is asserted for each data word of the received packets. The first occurrence of the FDDI data strobe will ca~lse t3-e flip-flop 90 to be set to a ONE, while the flip-flop 94 is set to a ~i~
ZERO ~flip-flop 92 remains a ZERO). The second occurrence of FDDI data strobe will cause the flip-flop 92 to be set to a ONE, while flip flop 94 rem~ins ZERO and flip flop 90 is reset to ZERO. As can be seen~ ~he third FDDI data strobe will reset the flip-flop 92 to a ZERO~ and set the flip-flop 94 to a ONE. In effect, a logic ONE h2- ~een shifted into~ and through the flip-flop chain 90, 92, ~4. As a result of this shift operation~ the Q O~ltp~it of the flip-flop 94 is set to a logic ONE, and the ~ output is set to a logic ZERO. With the Q output applied to the J input of the J/K flip flop 96, clocking of this flip-flop is inhibited ;`
20 or~reasons that wiLl be made clear below. This process ;~
; ~
continues for each packet received~ ~Intil ~ll packets have been sent. Termination of communic~tion of ~ackets will restllt in transmission of sync bytes until anotller packet is sent. Thus~ after receipt of three, or any m~lltiple of three~ data words, the J input of the J/K flip-flop 96 will have a logic ZERO applied its J inpt~t. Receipt of an FDDI
, command stro~e signal at the clock of the flip flop 96 will be ignored~ and the Q output of the flip flop 96 will remain at ZERO.
However, if at any time the F~DI command strobe is asserted (i.e., a logic ONE~ at the J inp~lt of the JfK, indicating that something other than thIee~ or a multiple of `~
three data~words was not received ~efore A sync ~yte, the Q
~ output of the J/K flip-flop 96 will be set to a OME~
- ~ ~ 35 asserting (and latclling) the ERROR FL~G~ Setting the ERROR
FL~G indicates the possibility o lo~ss of a packet in .
~ . ~
~6~ 12 ~
transmission ~Ipstream of the 4B/5B/ decode~ 56~ thereby -~
providing a form of fault isolation.
A system RESET command can be gener~ted to reset the packet assembly control checker 54 ~ia the OR gate 100 (to the flip flop 90-94) and the INVERTOR 102 (for flip flop :~
96). , ~`
,~ The transmitter,"receiver pair (30,~32) that forms ....
the fiber optic interface may be constructed from commercially available, off-the-shelf elements. ~or example, the 4B/5B encoder 36 and NRZ~I encoder 38 of the ~rèceiver 30, and the 4B/5B decoder 56 and NRZI decoder 52, "~
are separately sold as single integrated cIrc~lit packaged devices by Advanced Micro Devices, 9OI Thompson Place, Sunnyvale,~ California 94088 ~Inder the part n~lmbers AM7968 and AM7969, respectively. These devicefi are constr~lcted to generate,~autonomously, the sync byte described above when not transmitting packets.
Similarly, the fiber optic link transmitter 50 and fiber optic link receiver 52 are conventional electro-optic 20~ d`e~vlceo conotructed to convert electrical energy to light ;~
s~ energy,~or b~ack.
The multiplexer 34 and dem~lltipIexer 56 are of convent~ional design. They are each constructed and configured, for example, to include a state machine (not ~; ~ 25; shown) that contro;ls a~conventlonal m~lltiplex~ demultiplex circui~t to perform~the~operations required of the ?~
mutiplexer, demuLtiplexer 34, 56, respectively. The system provideo a clock (CLK) signal for syIlchrono~ls operation `~
thereof, and a control (CTL) signal to various control ~-functions that may need such signals.
' :~ : ' ` ., , ., '':~:
,
Claims (9)
1. A method for checking for the occurrence of errors in digital data packet containing N serially transmitted bits, the N bits including two adjacent bits indicative of one of a plurality of forms of the N
bits, comprising the steps of:
swapping one of the two bits with one of the remaining N bits;
creating a check code having at least one bit derived from N/M bits occupying corresponding bit positions of N/M equal-bit groups of the N bits;
serially transmitting the N bits together with the check code;
receiving the N bits and check code, and creating from the received N bits an error code in the same manner as the check code was created;
comparing the error and check codes to provide an indication of error when the error and check codes do not match.
bits, comprising the steps of:
swapping one of the two bits with one of the remaining N bits;
creating a check code having at least one bit derived from N/M bits occupying corresponding bit positions of N/M equal-bit groups of the N bits;
serially transmitting the N bits together with the check code;
receiving the N bits and check code, and creating from the received N bits an error code in the same manner as the check code was created;
comparing the error and check codes to provide an indication of error when the error and check codes do not match.
2. The method of claim 1, wherein the check code created is a plurality of parity bits, each parity bit being calculated over the N/M bits occupying corresponding bit positions.
3. The method of claim 1, wherein the check code is transmitted following transmission of the plurality of bits.
4. In a data communication system for communicating N-bit packets of digital data, including at least two bits indicative of one of a plurality of data types, apparatus to detect the presence of data corruption that may occur during transmission, the apparatus comprising:
first circuit means for swapping one of the two bits with one of the remaining N bits, and including encoding means for creating a check code that is derived from N/M bits that occupy corresponding bit positions of N/M groups of the N bits;
transmitting means coupled to the first circuit means for receiving and serially transmitting the N
bits and the check code in a FDDI 4B/5B format;
receiving means coupled to receive the 4B/5B
encoded N bits and check code, including means to extract the N bits and the check code from the FDDI
4B/5B format, and means for creating from the received N bits an error code in the same manner as the check code was created; and second circuit means comparing the error and the check codes to provide an indication of error when the error and the check codes do not match.
first circuit means for swapping one of the two bits with one of the remaining N bits, and including encoding means for creating a check code that is derived from N/M bits that occupy corresponding bit positions of N/M groups of the N bits;
transmitting means coupled to the first circuit means for receiving and serially transmitting the N
bits and the check code in a FDDI 4B/5B format;
receiving means coupled to receive the 4B/5B
encoded N bits and check code, including means to extract the N bits and the check code from the FDDI
4B/5B format, and means for creating from the received N bits an error code in the same manner as the check code was created; and second circuit means comparing the error and the check codes to provide an indication of error when the error and the check codes do not match.
5. The apparatus of claim 4, wherein N = 20.
6. The apparatus of claim 5, wherein M = 5
7. The apparatus of claim 4, wherein the transmitting means includes means for transmitting the FDDI 4B/5B encoded N bits and check code as a number of individual data words.
8. The apparatus of claim 5, wherein the receiving means includes means for returning the swapped bits to the original locations in the N-bit packets prior to creating the error code.
9. In a data communication system for communicating N-bit packets of digital data including at least two bits indicative of one of a plurality of data types, a method of detecting the presence of data corruption may occur during transmission, the method comprising the steps of:
swapping of one of the two bits with one of the remaining N bits;
creating a check code that is derived from N/M
bits that occupy corresponding bit positions of N/M
groups of the N bits;
serially transmitting the N bits and the check code in a FDDI 4B/5B format;
receiving the 4B/5B encoded N bits and check code, and extracting the N bits and the check code from the FDDI 4B/5B format;
creating from the received N bits an error code in the same manner as the check code created; and comparing the error and the check codes to provide an indication of error when the error and check codes do not match.
swapping of one of the two bits with one of the remaining N bits;
creating a check code that is derived from N/M
bits that occupy corresponding bit positions of N/M
groups of the N bits;
serially transmitting the N bits and the check code in a FDDI 4B/5B format;
receiving the 4B/5B encoded N bits and check code, and extracting the N bits and the check code from the FDDI 4B/5B format;
creating from the received N bits an error code in the same manner as the check code created; and comparing the error and the check codes to provide an indication of error when the error and check codes do not match.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/406,012 US5068854A (en) | 1989-09-12 | 1989-09-12 | Error detection for fiber distributed interfaced optic link |
| US406,012 | 1989-09-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2066611A1 CA2066611A1 (en) | 1991-03-13 |
| CA2066611C true CA2066611C (en) | 1994-04-12 |
Family
ID=23606171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002066611A Expired - Fee Related CA2066611C (en) | 1989-09-12 | 1990-09-12 | Error detection for fiber distributed interfaced optic link |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5068854A (en) |
| EP (1) | EP0491868B1 (en) |
| JP (1) | JPH0813027B2 (en) |
| AT (1) | ATE144665T1 (en) |
| AU (1) | AU633642B2 (en) |
| CA (1) | CA2066611C (en) |
| DE (1) | DE69028992T2 (en) |
| WO (1) | WO1991004530A1 (en) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL9101376A (en) * | 1990-08-16 | 1992-03-16 | Digital Equipment Corp | AN IMPROVED ERROR DETECTION CODING SYSTEM. |
| FR2688109B1 (en) * | 1992-02-28 | 1994-12-30 | Cit Alcatel | SYSTEM FOR TRANSMITTING DIGITAL INFORMATION ON AN OPTICAL LINK WITH REPEATERS WITH OPTICAL AMPLIFIERS. |
| GB9213272D0 (en) | 1992-06-23 | 1992-08-05 | Digital Equipment Int | Check sequence preservation |
| US5524218A (en) * | 1993-12-23 | 1996-06-04 | Unisys Corporation | Dedicated point to point fiber optic interface |
| JP2611667B2 (en) * | 1994-07-27 | 1997-05-21 | 日本電気株式会社 | Heterogeneous frame format mixed communication system |
| US5644593A (en) * | 1994-09-02 | 1997-07-01 | Microcom Systems, Inc. | High performance communications interface |
| US5581566A (en) * | 1995-01-06 | 1996-12-03 | The Regents Of The Univ. Of California Office Of Technology Transfer | High-performance parallel interface to synchronous optical network gateway |
| NL1000669C2 (en) * | 1995-06-26 | 1996-12-31 | Nederland Ptt | Method and devices for transferring data with control for transmission errors. |
| US5659552A (en) * | 1995-10-17 | 1997-08-19 | Lucent Technologies Inc. | Method and apparatus for verifying test information on a backplane test bus |
| US5768300A (en) * | 1996-02-22 | 1998-06-16 | Fujitsu Limited | Interconnect fault detection and localization method and apparatus |
| US5931967A (en) * | 1996-02-22 | 1999-08-03 | Fujitsu, Ltd. | Method and apparatus for detection of errors in multiple-word communications |
| JPH11196070A (en) * | 1997-12-27 | 1999-07-21 | Sony Corp | Transmitter, receiver, communication system and communication method |
| US6112262A (en) * | 1998-08-03 | 2000-08-29 | S3 Incorporated | System and method for efficiently transferring information between processors |
| US6574016B1 (en) * | 1998-11-25 | 2003-06-03 | Nortel Networks Limited | Method and apparatus for ancillary data in a wavelength division multiplexed system |
| US6851086B2 (en) | 2000-03-31 | 2005-02-01 | Ted Szymanski | Transmitter, receiver, and coding scheme to increase data rate and decrease bit error rate of an optical data link |
| US7310762B2 (en) * | 2004-01-12 | 2007-12-18 | Hewlett-Packard Development Company, L.P. | Detection of errors |
| US7672222B2 (en) * | 2004-01-12 | 2010-03-02 | Hewlett-Packard Development Company, L.P. | Link failures |
| US7436777B2 (en) | 2004-01-12 | 2008-10-14 | Hewlett-Packard Development Company, L.P. | Failed link training |
| US7606253B2 (en) * | 2004-01-12 | 2009-10-20 | Hewlett-Packard Development Company, L.P. | Successful transactions |
| US7613958B2 (en) | 2004-01-12 | 2009-11-03 | Hewlett-Packard Development Company, L.P. | Error detection in a system having coupled channels |
| US7721159B2 (en) * | 2005-02-11 | 2010-05-18 | Hewlett-Packard Development Company, L.P. | Passing debug information |
| US7624213B2 (en) * | 2005-02-11 | 2009-11-24 | Hewlett-Packard Development Company, L.P. | Passing identification information |
| JP5532030B2 (en) * | 2011-09-07 | 2014-06-25 | 株式会社デンソー | Data communication method and data communication apparatus |
| US10164737B2 (en) * | 2015-03-18 | 2018-12-25 | Infineon Technologies Ag | SPC sensor interface with partial parity protection |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3037697A (en) * | 1959-06-17 | 1962-06-05 | Honeywell Regulator Co | Information handling apparatus |
| US3718903A (en) * | 1970-11-18 | 1973-02-27 | Fujitsu Ltd | Circuit arrangement for checking stored information |
| US3831144A (en) * | 1973-06-11 | 1974-08-20 | Motorola Inc | Multi-level error detection code |
| US4156867A (en) * | 1977-09-06 | 1979-05-29 | Motorola, Inc. | Data communication system with random and burst error protection and correction |
| US4312070A (en) * | 1979-12-07 | 1982-01-19 | Motorola, Inc. | Digital encoder-decoder |
| US4371963A (en) * | 1980-12-24 | 1983-02-01 | Ncr Corporation | Method and apparatus for detecting and correcting errors in a memory |
| US4453251A (en) * | 1981-10-13 | 1984-06-05 | Burroughs Corporation | Error-correcting memory with low storage overhead and fast correction mechanism |
| US4464747A (en) * | 1982-02-18 | 1984-08-07 | The Singer Company | High reliability memory |
| EP0155455B1 (en) * | 1984-02-25 | 1988-06-22 | ANT Nachrichtentechnik GmbH | Arrangement for coding a digital signal |
| FR2606239A1 (en) * | 1986-10-30 | 1988-05-06 | Bull Sa | METHOD AND DEVICE FOR TRANSMITTING DIGITAL DATA |
| JPH0691512B2 (en) * | 1987-05-29 | 1994-11-14 | 富士通株式会社 | Method and apparatus for detecting error in data transferred on transmission line |
| US4849969A (en) * | 1988-05-19 | 1989-07-18 | Advanced Micro Devices, Inc. | Implementation of smoothing apparatus for an independently clocked network |
-
1989
- 1989-09-12 US US07/406,012 patent/US5068854A/en not_active Expired - Lifetime
-
1990
- 1990-09-12 EP EP90915244A patent/EP0491868B1/en not_active Expired - Lifetime
- 1990-09-12 DE DE69028992T patent/DE69028992T2/en not_active Expired - Fee Related
- 1990-09-12 AU AU65290/90A patent/AU633642B2/en not_active Ceased
- 1990-09-12 CA CA002066611A patent/CA2066611C/en not_active Expired - Fee Related
- 1990-09-12 WO PCT/US1990/005154 patent/WO1991004530A1/en active IP Right Grant
- 1990-09-12 JP JP2514171A patent/JPH0813027B2/en not_active Expired - Lifetime
- 1990-09-12 AT AT90915244T patent/ATE144665T1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| DE69028992D1 (en) | 1996-11-28 |
| JPH04505692A (en) | 1992-10-01 |
| ATE144665T1 (en) | 1996-11-15 |
| JPH0813027B2 (en) | 1996-02-07 |
| WO1991004530A1 (en) | 1991-04-04 |
| AU6529090A (en) | 1991-04-18 |
| CA2066611A1 (en) | 1991-03-13 |
| EP0491868B1 (en) | 1996-10-23 |
| EP0491868A4 (en) | 1992-10-21 |
| DE69028992T2 (en) | 1997-05-28 |
| US5068854A (en) | 1991-11-26 |
| EP0491868A1 (en) | 1992-07-01 |
| AU633642B2 (en) | 1993-02-04 |
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