CA2042009A1 - Video interface circuit - Google Patents
Video interface circuitInfo
- Publication number
- CA2042009A1 CA2042009A1 CA002042009A CA2042009A CA2042009A1 CA 2042009 A1 CA2042009 A1 CA 2042009A1 CA 002042009 A CA002042009 A CA 002042009A CA 2042009 A CA2042009 A CA 2042009A CA 2042009 A1 CA2042009 A1 CA 2042009A1
- Authority
- CA
- Canada
- Prior art keywords
- circuit
- video
- colour
- channel
- green
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/74—Circuits for processing colour signals for obtaining special effects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
- G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
- G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables
Abstract
Abstract Video Interface Circuit A video circuit which enables three full colour VDU's (6a, 6b, 6c) to be driven by only one colour graphics generator (2). The Circuit has many uses including the generation of head down displays for flight simulators.
Description
Video Interface Circuit Background of the Invention This invention relates to video circuitry and has a particular application to the generation of colour displays for instrument panels used on flight simulators.
It ls usual when generating full colour dlsplays for slmulator use, to -ëmploy one colour graphics gëné~ator per visual display unit (VDU). However, graphics generators are expensive items of equipment to purchase and maintain and therefore where several displays are required, this practice has the disadvantage of high cost.
This invention aims to provide a means whereby only one colour graphics generator is required in order to drive a multiplicity of full colour VDU's, thereby significantly reducing the cost of visual display generation.
Summary of the Invention The invention thus comprises a video circuit for connection to a colour graphics generator which has red, green and blue video output channels of variable amplitude, the video circuit consisting of a first circuit, whose outputs are connected to a second circuit, in which the first circuit assigns a colour value to the incomlng signal on each video channel, dependent on the instantaneous amplitude of sald signal, and the second circuit converts the assigned colour values to red, green and blue video signals for connection to VDU's.
Hence three full colour YDU's can be driven from ~ust one colour graphics generator. Each display can be unlque by programming -the graphics generator to generake three different formats in each of the three primary colours, red, green and blue. Colour variations within each format are achieved by varying the intensity of each primary colour as desired. ~ ,h~ J~
The first circuit may, or example, consist of a three-channel analogue to digital converter (ADC) and a colour palette. The colour palette may be controlled by a microprocessor 50 that one set of assigned colours may be quickly and conveniently changed to another set, if desired.
The second circuit may consist of a three channel video digital to analogue converter (DAC).
The graphics generator could be programmed to generate a single format using all three primary colours. In this case all three VDU's display the same format. However, the colours on the VDU's could differ depending on how the colour palette was programmed.
Brief Description of the Drawin~
An embodiment of the invention will now be described, by way of example only, with reference to the drawlng whlch is a block diagram of a video circuit in accordance with the invention.
~etailed Description of the Preferred Embodiment i,t .3 .1. j~, ~,~ ~,3 fl The diagram shows an 8-bit three channel, high speed ADC 1 whose inputs are the red, green and blue output video channels from a graphics generator 2. The outputs from the ADC 1 are connected to a colour palette 3 which is under the control of a microprocessor 4. A three-channel high speed DAC 5 converts the outputs from the colour palette 3 to red, green and `blue v~deo signals which ln turn are connected to VDU's 6a, 6b, and 6c. A sync separa~or 7 and clock generator 8 ensure synchronisation between the rest of the circuitry.
In use the graphics generator 2 is programmed to generate three distinct formats in each primary colour. The intensities of each colour are varied across the formats as desired.
The colour palette 3 is programmed by the microprocessor 4 so that the afore-mentioned intensity variations can be translated by the palette into the desired colours for final display on each VDU 6a, 6b, and 6c.
Signals from the red, green and blue video output channels from the graphics generator 2 are then digltlsed by the ADC 1. The ADC 1 produces 8-bit data corresponding to the instantaneous amplitude of the video signal on each channel. The ADC 1 is clocked at the appropriata pixel rate by the clock generator 8.
The clock generator 8 15 in turn synchronised to the video output channels by the sync separator 7 whlch recelves its sync signal from the green video channel.
Alternatively, the synch signal could be supplied from a separate output of the graphics generator 2.
Digital data from the ADC 1 is passed on to the palette 3. The palette allows selection of any 256 colour8 out of the 262,144 colours which are available on current commerclally producea palettes.
Data in the palette relating colours to dlgitised amplitude values of the lncominy video slgnals is contxolled by the microprocessor ~ which itself is under operator control.
Signals relating to discrete colours are fed from the output of the colour palette 3 to the inputs of the three channel DAC 5. The DAC 5 reconstructs the signals on its inputs into three video channels each having red, green and blue components and sync.
Input sync, blanking data and a clock signal are supplied to the DAC 5 by the clock generator 8.
Each channel is fed to a VDU 6a, 6b or 6c. Thus each of the three form3ts originally generated by the graphics generator are displayed on one of the VDU's 6a, 6b and 6c.
Each VDU presents a full colour display.
It ls usual when generating full colour dlsplays for slmulator use, to -ëmploy one colour graphics gëné~ator per visual display unit (VDU). However, graphics generators are expensive items of equipment to purchase and maintain and therefore where several displays are required, this practice has the disadvantage of high cost.
This invention aims to provide a means whereby only one colour graphics generator is required in order to drive a multiplicity of full colour VDU's, thereby significantly reducing the cost of visual display generation.
Summary of the Invention The invention thus comprises a video circuit for connection to a colour graphics generator which has red, green and blue video output channels of variable amplitude, the video circuit consisting of a first circuit, whose outputs are connected to a second circuit, in which the first circuit assigns a colour value to the incomlng signal on each video channel, dependent on the instantaneous amplitude of sald signal, and the second circuit converts the assigned colour values to red, green and blue video signals for connection to VDU's.
Hence three full colour YDU's can be driven from ~ust one colour graphics generator. Each display can be unlque by programming -the graphics generator to generake three different formats in each of the three primary colours, red, green and blue. Colour variations within each format are achieved by varying the intensity of each primary colour as desired. ~ ,h~ J~
The first circuit may, or example, consist of a three-channel analogue to digital converter (ADC) and a colour palette. The colour palette may be controlled by a microprocessor 50 that one set of assigned colours may be quickly and conveniently changed to another set, if desired.
The second circuit may consist of a three channel video digital to analogue converter (DAC).
The graphics generator could be programmed to generate a single format using all three primary colours. In this case all three VDU's display the same format. However, the colours on the VDU's could differ depending on how the colour palette was programmed.
Brief Description of the Drawin~
An embodiment of the invention will now be described, by way of example only, with reference to the drawlng whlch is a block diagram of a video circuit in accordance with the invention.
~etailed Description of the Preferred Embodiment i,t .3 .1. j~, ~,~ ~,3 fl The diagram shows an 8-bit three channel, high speed ADC 1 whose inputs are the red, green and blue output video channels from a graphics generator 2. The outputs from the ADC 1 are connected to a colour palette 3 which is under the control of a microprocessor 4. A three-channel high speed DAC 5 converts the outputs from the colour palette 3 to red, green and `blue v~deo signals which ln turn are connected to VDU's 6a, 6b, and 6c. A sync separa~or 7 and clock generator 8 ensure synchronisation between the rest of the circuitry.
In use the graphics generator 2 is programmed to generate three distinct formats in each primary colour. The intensities of each colour are varied across the formats as desired.
The colour palette 3 is programmed by the microprocessor 4 so that the afore-mentioned intensity variations can be translated by the palette into the desired colours for final display on each VDU 6a, 6b, and 6c.
Signals from the red, green and blue video output channels from the graphics generator 2 are then digltlsed by the ADC 1. The ADC 1 produces 8-bit data corresponding to the instantaneous amplitude of the video signal on each channel. The ADC 1 is clocked at the appropriata pixel rate by the clock generator 8.
The clock generator 8 15 in turn synchronised to the video output channels by the sync separator 7 whlch recelves its sync signal from the green video channel.
Alternatively, the synch signal could be supplied from a separate output of the graphics generator 2.
Digital data from the ADC 1 is passed on to the palette 3. The palette allows selection of any 256 colour8 out of the 262,144 colours which are available on current commerclally producea palettes.
Data in the palette relating colours to dlgitised amplitude values of the lncominy video slgnals is contxolled by the microprocessor ~ which itself is under operator control.
Signals relating to discrete colours are fed from the output of the colour palette 3 to the inputs of the three channel DAC 5. The DAC 5 reconstructs the signals on its inputs into three video channels each having red, green and blue components and sync.
Input sync, blanking data and a clock signal are supplied to the DAC 5 by the clock generator 8.
Each channel is fed to a VDU 6a, 6b or 6c. Thus each of the three form3ts originally generated by the graphics generator are displayed on one of the VDU's 6a, 6b and 6c.
Each VDU presents a full colour display.
Claims (4)
1. A video circuit for connection to a colour graphics generator which has red, green and blue video output channels of variable amplitude, the video circuit consisting of a first circuit, whose outputs are connected to a second circuit, in which the first circuit assigns a colour value to the incoming signal on each video channel, dependent on the instantaneous amplitude of said signal, and the second circuit converts the assigned colour values to red, green and blue video signals for connection to visual display units.
2. A video circuit as claimed in Claim 1 in which the first circuit consists of a three-channel analogue to digital converter and a colour palette.
3. A video circuit as claimed in Claim 2 in which the colour palette is controlled by a microprocessor.
4. A video circuit as claimed in any preceding claim in which the second circuit consists of a three-channel video digital to analogue converter.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB909013300A GB9013300D0 (en) | 1990-06-14 | 1990-06-14 | Video interface circuit |
| GB9013300.0 | 1990-06-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2042009A1 true CA2042009A1 (en) | 1991-12-15 |
Family
ID=10677623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002042009A Abandoned CA2042009A1 (en) | 1990-06-14 | 1991-05-07 | Video interface circuit |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5227768A (en) |
| EP (1) | EP0461368B1 (en) |
| JP (1) | JPH05134639A (en) |
| CA (1) | CA2042009A1 (en) |
| DE (1) | DE69113322T2 (en) |
| GB (1) | GB9013300D0 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5576723A (en) * | 1987-09-11 | 1996-11-19 | Cybex Computer Products Corporation | VGA signal converter for converting VGA color signals to VGA monochrome signals |
| DE69324899T2 (en) * | 1992-12-15 | 1999-10-21 | Du Pont | Color matching method and device |
| US6507810B2 (en) | 1999-06-14 | 2003-01-14 | Sun Microsystems, Inc. | Integrated sub-network for a vehicle |
| US6975612B1 (en) | 1999-06-14 | 2005-12-13 | Sun Microsystems, Inc. | System and method for providing software upgrades to a vehicle |
| US6253122B1 (en) * | 1999-06-14 | 2001-06-26 | Sun Microsystems, Inc. | Software upgradable dashboard |
| US6754183B1 (en) | 1999-06-14 | 2004-06-22 | Sun Microsystems, Inc. | System and method for integrating a vehicle subnetwork into a primary network |
| US6362730B2 (en) | 1999-06-14 | 2002-03-26 | Sun Microsystems, Inc. | System and method for collecting vehicle information |
| US6370449B1 (en) | 1999-06-14 | 2002-04-09 | Sun Microsystems, Inc. | Upgradable vehicle component architecture |
| US7825921B2 (en) * | 2004-04-09 | 2010-11-02 | Samsung Electronics Co., Ltd. | System and method for improving sub-pixel rendering of image data in non-striped display systems |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2056813B (en) * | 1979-05-03 | 1983-06-22 | Standard Telephones Cables Ltd | Data transmission and display |
| JPS60134336A (en) * | 1983-12-23 | 1985-07-17 | Hitachi Ltd | Display control device |
| JPS60254190A (en) * | 1984-05-31 | 1985-12-14 | 株式会社 アスキ− | Display controller |
| US4868552A (en) * | 1986-08-25 | 1989-09-19 | Rohde & Schwartz-Polarad | Apparatus and method for monochrome/multicolor display of superimposed images |
| EP0295689B1 (en) * | 1987-06-19 | 1995-03-29 | Kabushiki Kaisha Toshiba | Display controller for CRT/plasma display apparatus |
| US4965559A (en) * | 1988-05-31 | 1990-10-23 | Motorola, Inc. | Multi-channel graphics controller |
| US4894653A (en) * | 1988-06-24 | 1990-01-16 | Hughes Aircraft Company | Method and apparatus for generating video signals |
-
1990
- 1990-06-14 GB GB909013300A patent/GB9013300D0/en active Pending
-
1991
- 1991-04-22 EP EP91106465A patent/EP0461368B1/en not_active Expired - Lifetime
- 1991-04-22 DE DE69113322T patent/DE69113322T2/en not_active Expired - Fee Related
- 1991-05-02 JP JP3100811A patent/JPH05134639A/en active Pending
- 1991-05-07 CA CA002042009A patent/CA2042009A1/en not_active Abandoned
- 1991-05-07 US US07/697,024 patent/US5227768A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0461368B1 (en) | 1995-09-27 |
| EP0461368A3 (en) | 1993-06-09 |
| DE69113322D1 (en) | 1995-11-02 |
| JPH05134639A (en) | 1993-05-28 |
| US5227768A (en) | 1993-07-13 |
| DE69113322T2 (en) | 1996-03-07 |
| EP0461368A2 (en) | 1991-12-18 |
| GB9013300D0 (en) | 1990-08-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Discontinued |