CA2032549C - Drop testing in fiber to the home systems - Google Patents
Drop testing in fiber to the home systemsInfo
- Publication number
- CA2032549C CA2032549C CA002032549A CA2032549A CA2032549C CA 2032549 C CA2032549 C CA 2032549C CA 002032549 A CA002032549 A CA 002032549A CA 2032549 A CA2032549 A CA 2032549A CA 2032549 C CA2032549 C CA 2032549C
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- CA
- Canada
- Prior art keywords
- wires
- coupled
- circuit
- voltage
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
- H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
- H04M3/30—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop
- H04M3/302—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop using modulation techniques for copper pairs
- H04M3/303—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop using modulation techniques for copper pairs and using PCM multiplexers, e.g. pair gain systems
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/58—Testing of lines, cables or conductors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
- H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
- H04M3/30—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop
Abstract
Disclosed is a means for testing drop wires in digital loop systems which employ optical fiber up to a distant terminal near the subscriber's premises. A
test module is provided at the distant terminal to determine the presence or absence of faults on the wires to the customer premises. The results of the test are transmitted via an optical data link to the remote terminal where the results can be accessed by a loop tester at the central office.
test module is provided at the distant terminal to determine the presence or absence of faults on the wires to the customer premises. The results of the test are transmitted via an optical data link to the remote terminal where the results can be accessed by a loop tester at the central office.
Description
DROP TESTING IN FIBER TO THE HOME SYSTEMS
Back~round of the Il~vw~lion The invention relates to digital loop tr~n~mi~ion ~y~Lellls employing optical fibers, and in particular to a means for testing wire pairs which extend beyond 5 the last fiber link into subscriber premises.
Optical fiber has become the m~-lium of choice for sending digital signals belwæn dhe central office and remote termin~l~. Recendy the telephone service providers have extended the use of fiber optics beyond the remote terminal by setting up distant terminals on or near the subscriber premises and conn.o,cting 10 dhese distant terminals to the remote terminal by a fiber optic link. The distant tPrmin~l coll~,wl~ the digital signals from the fiber into normal analog signals.
Beyond dhe distant terminals, wire pairs, or "drop" wires extend into dhe customer premises to provide service. While a fiber optic link between remote and distanttçrmin~l~ will greatly increase the information capacity to the subscriber, it also 15 creates a problem in that it elimin;~tes electrical access to the customer's wire pair for determination of fault conditions.
The present method for electrical testing of the subscriber's line utilizes a wire pair e~ctçn-ling between the central office and remote terminal which can by-pass the digital link when testing is required (see, for example, U.S. Pat. No.
20 4,270,030). This technique is acceptable where thousands of cuslo.mel~ are being serviced, as is usually the case between the central office and remote tçrmin~
However, it becomes prohibitively expensive to provide wire pairs along with each fiber out to the distant terminals.
It is, thelefole, an object of the invention to provide a means for testing 25 the wire pair to customer premises in systems employing optical fiber up to the distant t~rmin~l S -mmqry of the Invention This and other objects are achieved in accordance with the invention which, in one aspect, is a digital loop tr~nsmi~sion system comprising a central30 office tçrmin~l, a remote termin~l optically and electrically coupled to the central office termin~l~ and a distant terminal which is optically coupled to the remoteterminal. The system further inciudes means in the distant termin~l for testing electrical wires extçn-ling beyond the distant termin~l and for optically tr~n~mitting the results of said test to the remote terminal. The remote termin~l further comprises means for CO~ ing said results into characteristic resi~t~nces which can be electrically aecesse~l by said central office terminal.
In accordance with a further aspect, the invention is a circuit for electrically testing a pair of wires. Circuit means are provided for ge~ratin~ a5 con~t~nt current having at least two values. Also provided is a bridge circuit having two legs and including means for comparing voltages at the two legs of the circuit.
The circuit further includes means for coupling at least one of the wires to a leg of the bridge circuit.
Brief Description of the Drawin~
These and other features of the invention are deline~ted in detail in the following description. In the drawing:
FM. 1 is a schem~tic block diagram illustrating a digital loop tr~n~mi~ion system in accordance with an embodiment of the invention;
FIG. 2 is a flow diagram illustrating a testing sequence in accordance 15 with an embodiment of the invention;
FIGS. 3-5 are schem~tic diagrams of a circuit for testing drop wires in accordance with an embodiment of the invention;
FM. 6 is a schematic block diagram of a circuit for tr~n~mitting test signals in accordance with an embodiment of the invention;
- 20 FM. 7 is a schematic block diagram of a circuit for receiving test result signals and tr~n~mitting test control information in accordance with the same embo lim~-nt; and FIG. 8 is a schematic diagram of a circuit for exhibiting resist~n-~es in accol~lce with the same embodiment.
25 Detailed Description FM. 1 illustrates in block diagram form a basic digital loop tr~n~mi~sion system in accordance with an aspect of the invention. A central office includes a central office switch 10 and a terminal 11 which is optically and electrically coupled to a remote terminal 12 for providing bidirectional digital30 tr~n~mi~sion. The digital signals are usually carried by optical fibers, but a wire pair 13 is also included between the terminals providing an electrical by-pass for the purpose of testing. This wire pair is coupled to a pair gain test controller 14 which is controlled by a mPch~ni7~d loop tester (MLT) 15. (For more details concerning the pair gain test control arr~ngement, see U.S. Pat. No. 4,270,030.) An optical link 17 20325~9 comlec~ the remote terminal to a distant terminal 16 which is coupled to a plurality of subscribers by wire pairs, only one of which is illustrated as 18.
In accordance with a main feature of the invention, a drop test module 20 is included as a plug-in circuit card at the distant termin~l~ This circuit, as S described in more detail below, is designed to test the wire pairs, e.g. 18, to the various subscribers, and transmit the results in the form of optical data bits through the distant terminal by means of a data link 21 and an opticaVelectronic intPrf~ce 22 back to the remote terrnin~l The remote termin~l in~ludes an O/E interf~ce 24 and data link 23 for receiving the signals and a plurality of resistors which can be10 coupled to the tip and ring conductors of the wire pair 13 by means of relays which are responsive to the data bits from the distant terminal. The MLT lS thereby has electrical access to the results of the drop wire testing in the form of these resistors.
FIG. 2 illustrates a typical testing sequence p~,lro~ ed by the drop test module 20. The first test (designated FEMF) dele~ les the extent of any voltage on lS the line when the distant terrninal is ~i~connçcted (also known as "foreign voltage").
If there is a voltage, typically, of at least 10 volts, the wires fail and no more testing is conducted. If the wires pass that test, they are then tested for any leakage in the wires resulting from faults. This is accomplished in the next step of the diagram by coupling the tip and ring conductors of the wire pair together and dete~ inillg if the 20 colllbined resi~t~nce from the tip and ring conductors to ground is greater than SOK Q. If it is not, the wires fail this first leakage test and the testing is termin~teA
If the wires pass the test (RT R~RD > 50K Q), the wires are subjected to a second leakage test in step three of the diagram. Here, the tip conductor is coupled toground and the resi~t~n~e from ring-to-tip is measured. If this resi~t~n-~e is, again, 25 greater than SOK Q, the wires pass and the next test is pe~rwllled. This test, also known as a "continuity test" deterrnines if the ringer in the c~lstom~r~s telephone is c~ r,d by measuring the c~pacit~nce of the CU~ilQl~f ~ 'S ringer. If the ringer is connected, the wires pass all tests; if not, the wires fail and an in~ tiQn of "no ringer" is given. Going back to step 3, if the resistance is not greater than SOK Q, the 30 wires must be tested further to deterrnine if there is, in fact, a leak or if the cus~ el's receiver is off-hook. These tests are illustrated in the right-hand leg of the diagram. Thus, in the next test, with the tip conductor again grounded, resi~t~nce is measured with a lS milli~mp current applied. If the measured resistance is not less than 650 Q, the wires fail the leak test since the receiver could not exhibit this 35 resi~t~nce if the receiver were off-hook. If the resistance is less than 650 Q, the resistance of ring-to-tip is again measured, since there still might be an off-hook - 2032~4g con~lition, but this time with 1 milli~mr of current through the wires. If the resi~t~n-~e is not greater than 200 Q, the wires fail the leak test since, again, there cannot be an off-hook condition exhibiting this resi~t~nce If the resict~nce is greater than 200 Q, the wires are tested one more time to determine if the resi~t~nce at5 1 milli~mr is more than 60 Q grea-er than the resi~t~nce at 15 milli~mrs If it is, the ~ cei~t~r is off-hook. If it is not, th~ receiver cannot be off-hook and so there must be l.oslc~ge which would result in the wires failing the test. This concl~ldes the testing procedure.
One example of a circuit which is capable of p~_lrolmillg these tests is 10 shown in FIGS. 3-5. FIG. 3 essen~i:llly illustrates the driver section of the circuit.
CMOS switches 100 and 101 will alternatively be enabled to sink either a 1 milli~mp or 15 milli~mp current, respectively, from the tip and ring conductors. The outputs of the switches provide a 2.5 volt reference voltage (generated across diode Dl ) across resistors R2 and R3 to the inverting input of an operational amplifier 102. The 15 non-in~,~,.Ling input of the Op Amp is grounded. The feedb~c~ loop of the Op Amp includes resistors R7, R6 and R4 as well as a pair of Darlington-coupled bipolartransistors, Ql and Q2. In order to drive the voltage at the invelLillg input of the Op Amp to zero volts, a current is drawn through resistor R6 and the tr~nsi~tors Ql and Q2. This current is supplied through resistor R8 to point A of the circuit which has a 20 voltage of -30 volts applied thereto.
A reference current of 0.1 milli~mr or 1.5 milli~mrs is thereby created depending upon which of ~witches 100 or 101 is enabled. Applying this current toR8 activates a x10 current mirror formed by Op Amp 103, resistor Rg and Darlington-coupled bipolar transistors Q3 and Q4. This produces the desired 25 1 milli~mp or 15 milli~mrs current from the cond~lctor labeled Iso~rce through resistor Rlo to point B which is at -30 volts.
As shown in FIG. 4, the drawing of a constant current at the conductor Iso~rCe will establish a voltage Vs at one node of a bridge circuit where resistors Rls and Rl6 constitute one leg. The other leg is formed by either R24 or R2s, depen-ling 30 upon which of solid state relays 104 or 105 is enabled, and the load re~i~t~nce, RL~
formed by the c~lstomer equipment on the conductors labeled Tip and Ring. The tip com1~1ctor is coupled to the node connecting R24 and R2s (labeled Vl ) through a fuse Fl, a relay contact K1B~ a resistor R42 and another relay contact K2. The ring conductor is coupled to the node through fuse F2, relay contact KlC and resistor R43.
35 The voltage Vl at this node is compared with the voltage V2 at the node coupling Rls and Rl6 by means of a differential amplifier including Darlington-coupled ~0~2549 bipolar transistors Q7 and Q8 and resistor Rl8 in one leg, and Darlington-coupled bipolar tr~n~i~tors Qg and Qlo and resistor Rlg in another leg. The output of this dirr~ntial amplifier appears as a high or low voltage on the con(luctor labeled "COMP." A constant current is drawn through the amplifier by a co~ . t current 5 source including bipolar transistors Q5 and Q6 having their base regions coupled in co~ ,on to resistor R2l and their emitters coupled to voltages of -30 volts through resistors R22 (for Q5) and R23 (for Q6).
In order to conduct the foreign voltage test (FEMF < 10V), referring to FIG. 3, a 1 milli:3mr current is established at Iso~rCe by activating switch 100. Also, 10 relay 106 is enabled to connect a 20 volt zener diode, D2, to the same con~ tnr.
Returning to FIG. 4, this establishes a Vs on the cnnl1uctor Is~ rCe of -20 volts. With switches 104 and 105 both disabled, V2 will be equal to -10 volts since Rls and Rl6 are equal. The tip and ring conductors are tied together by closing relay cont~cK1B and KlC and opening relay contact K2. The voltage V1 on the tip and ring 15 conductors is CO~ ,d with the voltage V2 of -10 volts by the dirrelenlial amplifier inslu~ling transistors Q7-Qlo as previously described. If Vl < -10 volts, current in the dirr~ ial amplifier will flow through the Q7-Q8 leg and the output at the COMP conductor will be high, while if Vl 2 -10 volts, the current will flow through Qs-Qlo and the output will be low.
The next few leakage tests can also be pelrolllled by basically the same portion of the circuit described so far. Thus, in the first leakage test shown in FIG. 2 (RT,R~RD ~ SOK Q), tip and ring conductors are again tied together by closing relay contacts K1B and KlC and opening relay contact K2. Switch 100 (of FIG. 3) is enabled to genel~t~ a 1 milli~mr current, while switch 106 (of FIG. 3) is disabled and switch 104 is enabled in order to connect R24, which is a~l,lo~illlately 50K Q, to the tip and ring conductors. Therefore, the voltage Vl will be greater than or equal to V2 if the resistance of the subscriber's line, RL. is less than or equal to 50K Q, and, conversely, V1 will be less than V2 if the subscriber's line resi~t~n5e, RL. is greater than 50K Q. As before, if Vl < V2, current in the differential amplifier will 30 flow through Q7-Q8 and the output at COMP will be high, while if Vl 2 V2, thecurrent will flow through Qg-Qlo and the output will be low. For the second leakage test (RTR ~ 50K Q), the procedure is the same except that relay contact K2 is closed so that the tip con-luctor is grounded.
For the next leakage test (RTR < 650 Q), switch 101 of FIG. 3 is enabled 35 to produce a con~t~nt current of 15 milli~mps at Isource~ Switch 105 (FIG. 4) is also enabled and switch 104 disabled so that now resistor R2s is coupled to the ring -con-luctor (while tip remains grounded by relay contact K2). Since R2s is applu~ tely 650 Q, the output appearing at COMP, which colllp~,s the two voltages Vl and V2 as previously described, will in~ ate whether the resi~t~nce on the subscriber's line is greater than or less than 650 Q.
For purposes of later testing, the voltage Vl appearing when R2s is coupled to tip and ring is coupled to an input of Op Amp 107 by enabling switch 117. The output of Op Amp 107 is coupled to a sample and hold integrated circuit108 after being divided (by 15 in this case) by the resistors R32 and R33. The reslllting voltage is stored on capacitor Clo for later use.
For the next leakage test (RTR > 200 Q), the current at Iso~lrCe is returned to 1 milli~mr~ and R2s continues to be coupled to the tip and ring con~luctors. The resulting voltage Vl is still coupled by switch 117 to Op Amp 107, but the output of the Op Amp is also connected to the non-inverting input of colnp~lor 109. The compdlator co~ es this input with the ratio of resistors R30 to R3l, which in this example is approximately 8.7. With R30 and R3l coupled to a voltage of -5 volts,the co~ tol will produce a signal on the conductor labeled "short" if RL is lessthan or equal to 200 ohms, while no signal will be produced if RL is greater than 200 Q.
The last leakage test (Rl -Rls > 60 Q) is con-lucted by co...l~. ;ng this 20 output of Op Amp 107 with the voltage stored in C~p~Git( r Clo from the previous leakage test which was conducted at 15 millim~ps (RTR < 650 Q). A reference voltage of +2.5 volts applied to resistor R3s subtracts from the output of 107 the equivalent of 60 Q of resistance. The resulting signal is then applied to the inverting input of colllpalator 110, while the voltage stored in c~p~citor C10 is applied to the 25 non-in~,~Ling input through the sample and hold circuit 108. If the signal at the hl~e.ling (-) input is less than that at the non-inverting (+) input, a signal will appear at the conduct-~r labeled ROH to infli~te the receiver is off-hook. If the signal at the in~,~ling input is greater than or equal to that at the non-inverting input, no signal will appear at ROH, thus in-lic~ting that the problem was a leak.
The test for the presence of a ringer on the cu~tomer~s line is made by m~ uring the capacitance between tip and ring. This test makes use of the high voltage which is derived by taking the ringing supply (an AC signal of a~plo~illl&l~ly 20 Hz which is continuously applied to the conductor "20 HZ~ of FIG. 3) and rectifying it by diode D3 to store a voltage of applo~ ly -120 volts35 on c~p~citor C3. This voltage is discharged onto Isource by enabling switch 112 while the energy delivered to the load is restricted by Rll to prevent the telephone from acci~lent~lly ringing. This voltage charges the c~p~it~nre~ CL, on the customer's line (FIG. 4) through resistor R2s by activating switch 105. Zener diodes D4 and Ds limit the voltage stored on the line to -75 volts. The large voltage used (-75V) allows sl~ffiçient charge to be stored on electronic ringers that have zener 5 diodes in series with the capacitor. At the same time, reference c~p~rit~rS C18 and C8 are also charged to the same voltage Vs by enabling switch 111. When ~wilches112, 105, and 111 are disabled, the c~p~itors are disconnected from the voltage Vs.
Enabling switch 1 17 causes the ringer capacitance, CL, to discharge through l~ OlS
R26 and R27 which have a combined resistance of approximately 50K Q. At the 10 same time, reference c~pacitors Cl8 and C8 will discharge through resistor Rl6 which is also equal to approximately 50K Q. After a specified interval, usually a~l.~ tely 10 milli~econds, the voltages Vl and V2 are co~ d by the compal~lor elem~ont as previously described. If Vl is greater than V2, there is a ringer on the line.
It is also desirable in a testing circuit of this type to insure that there are no excessive AC or positive voltages on the tip and ring conductors which could ~m~ge the components of the circuit. Thus, the circuit also provides a means forpre-s.;l~nillg the tip and ring conductors for high voltage prior to the series of tests previously described. This pre-screening is ~ccomplished by routing the tip and ring 20 conductors through relay contacts K1B and KlC of FM. 4 and resistors R46, R47, and R44, R4s to conductr r HV. Any positive voltage on HV will be inverted to a negative voltage by inverter 120 of FIG. 5. As also shown in FIG. 5, the peak value of any AC signal or the DC signal will appear as a negative voltage Vp applied to the hl~ hlg (-) input of coll~arator 114. This voltage, Vp, gets compared with the 25 voltage at the non-inverting (+) input produced by resistors R49 and Rso coupled to a source of -5 volts. Thus, if the absolute m~nitude of the voltage on tip and ring is greater than 10 volts, the output of comparator 114 produces a flag (PRESCREEN) at the pro~;l~lllllable array logic (PAL) chip 115 and the testing will be tern~in~te l As further shown in FIG. 5, the signal on the COMP conductor from the 30 previously-described tests utilizing the comparator including Q7-Qlo of FIG. 4 is coupled to colll~ tor 113 to provide gain and convert to a logic level signal oncon~luctor COMP IN which can be utilized by the PAL 115. That signal as well as the signals previously described which are produced on the ROH, PRESCREEN, and SHORT cond~lctors are all applied to the input portion of the PAL 115. The test 35 results appear as one bit on each of the output leads DTRl, DTR2, and DTR3. The conductor DT DONE in(~ tes when a test is completed. The rem~in-ler of the ` -output conductors are each coupled to one of the switches of the circuit as inrli~ated The conductors labeled Relay 1 and Relay 2 operate, respectively, the relays K1Aand K2A which are associated, respectively, with the relay contacts K1B, KlC, and K2 of FIG. 4. A monostable oscill~tor 116 is also coupled to the PAL to adjust the 5 normal clocking of the PAL during the ringer test to produce the 10 milli~ec period for sampling the discharging car~cit;~nce The outputs from the PAL 115 are then coupled to the data link, 21 of FIG. 1, at the distant termin~l This data link is illustrated in more detail in the block diagram of FIG. 6. As shown, the drop test module 20 is controlled by a 10 microprocessor 201 which initi~tes testing by providing a signal on the TEST lead through a latch 202 after receiving a command (test code) from the central of fice as part of the normal digital stream on data bus 208. This co,.",.~n(l, along with a con~lllalol~ signal (OTR) from the remote termin~l, is coupled to the micluplucessor 201 through latch 210 and specifies which of the channel units 203 15 are to be tested. The test module is coupled to the drop wires through the channel unit 203 serving the subscriber when a relay K10A is operated to close contact K10B-This relay is operated when microprocessor 201 sends a signal through latch 212 and relay driver 213 which is coupled to the relay. (It will be appreciated that only one relay driver and relay are shown, but there typically would be one of each for every 20 channel unit.) The test results from the module are tr~n~mittecl as sepd~aLe bits on leads DTRl, DTR2 and DTR3 to the microprocessor 201 through a latch 204. The test bits are then tr~n~mitted along with other data to separate latches 205, 206 and 207 onto the data bus 208. A multiplexer 209 frames the data bits and scrambles the signal according to well-known techniques. The signal is then coupled to a standard 25 opticaVelectronic interface 22, which comprises a laser and photodetector, for optical tr~nsmi~sion to the remote termin~l The optical data signal is Ll~lsre.~ed via optical link 17 of FIG. 1 from the distant terrnin~l to the O/E interf~ce 24 and data link 23 of FIG. 1 at the remote terminal.
As illustrated in more detail in the block diagram of FIG. 7, the remote 30 termin~l converts the optical signal to an electronic signal by means of a standard opticaVelectronic interf~ce circuit shown as 24. The signals are coupled to a standard protection circuit, illustrated by block 302, and fed to a skew cwllpensator 303 to set the incoming data to the clock (not shown) at the remote termin~l. The skew coll~ellsator can be the type including a programmable array logic chip which 35 is described in U.S. Pat. No. 4,839,907. The signals are then descrambled by standard means 304, such as a custom IC chip which is part of a multiplexer/demultiplexer 309, and coupled to the input of a pro~~ able array logic chip 305 which picks out the bits related to the drop testing and produces them on the lines labeled RLYl, RLY2 and RLY3. These bits are coupled to a standard relay driver 306 which operates relay contacts K4A-K7A. These relays operate the S COnt~Gt~ K4B. KSB. K6B. K7B. K4C. KSC. K6C~ and K7c illustrated in FIG. 8. (The first number in the desi~n~tion of the contact is the same as the first number of the relay to which it corresponds.) FIG. 7 also illustrates the c~ ic~tion path fromthe remote terminal to the distant terminal. A backplane access circuit 307 decodes and tr~n~l~tes digital signals from the central office. This bit stream, which includes 10 a colll"l~l-(l (test code) from the central office to test a channel unit, is put onto the bus 311 and sent through a programmable array logic chip 305 onto bus 312 to themultiplexer/demultiplexer circuit 309. Part of this circuit includes a scrambling circuit 313. The scrambled signal is coupled to the O/E interf~ce 24 and sent to the distant t~rmin~l Referring back to the backplane circuit 307, the test code is also 15 picked off of the incoming data and sent to a bank controller unit (BCU) 308. The BCU decides if the test should take place. If the test is to proceed, a col-r;. .l~to~
signal (OTR) is sent by the BCU through the backplane circuit onto lead 310 to the PAL where the signal is combined with the rest of the incoming signal on bus 312for tr~n~mi~sion to the distant terminal.
The circuit of FIG. 8 is the remote terminal tip-to-ring resistance delta to the central of fice based on which contacts are opened or closed by the data from the drop test. Resistors Rloo and Rlos produce constant ring-to-ground and tip-to-ground resi~t~nce which, in this example is applo~ .lately 91K Q. Resistor R104,which in this example is ap~ ately 18K Q, provides a minimllm resi~t~nce 25 regardless of the test results. Resistors Rlol, Rl02 and Rl03, which in this example are 40K Q, 20K Q, and 10K Q, respectively, will be coupled between tip and ring or shorted out depending on the condition of switches KSC~ K7c and K6C~ respectively, which are normally closed to short out these resistors. The table below gives one example of how the 3-bit messages from the drop test module can indic~te various30 test conllition~ based on the coupling of the various resistors.
TABLE
Bit Message Coll~lition Switches Opened Resistors Coupled S 001 No Drop Test K6C Rl04 and Rl03 Module 010 Pass K7c Rl04 and Rl02 011 NoRinger K6C andK7c Rlo4~Rl03.
and Rl02 100 FEMF/I e~k~ge KSC Rl04 andRloi 101 ROH K6C and KSC R104~ R101 and Rl03 The first condition in the table inflic~tes no drop test module is available. In the event that the optical link between the distant and remote terrnin~l~
25 is not working properly, an open circuit will be presented to the central office by opening switches KSB. K6B. and K7B
It will be appreciated that various values of the circuit components given herein are illustrative and can be varied according to particular needs. Various other lition~ and mr~ific~tion~ will also become a~pal~l t to those skilled in the art. All 30 such vari~tion~ which rely on the teachings through which the invention has advanced the art are pr~e.ly considered within the scope of the invention.
Back~round of the Il~vw~lion The invention relates to digital loop tr~n~mi~ion ~y~Lellls employing optical fibers, and in particular to a means for testing wire pairs which extend beyond 5 the last fiber link into subscriber premises.
Optical fiber has become the m~-lium of choice for sending digital signals belwæn dhe central office and remote termin~l~. Recendy the telephone service providers have extended the use of fiber optics beyond the remote terminal by setting up distant terminals on or near the subscriber premises and conn.o,cting 10 dhese distant terminals to the remote terminal by a fiber optic link. The distant tPrmin~l coll~,wl~ the digital signals from the fiber into normal analog signals.
Beyond dhe distant terminals, wire pairs, or "drop" wires extend into dhe customer premises to provide service. While a fiber optic link between remote and distanttçrmin~l~ will greatly increase the information capacity to the subscriber, it also 15 creates a problem in that it elimin;~tes electrical access to the customer's wire pair for determination of fault conditions.
The present method for electrical testing of the subscriber's line utilizes a wire pair e~ctçn-ling between the central office and remote terminal which can by-pass the digital link when testing is required (see, for example, U.S. Pat. No.
20 4,270,030). This technique is acceptable where thousands of cuslo.mel~ are being serviced, as is usually the case between the central office and remote tçrmin~
However, it becomes prohibitively expensive to provide wire pairs along with each fiber out to the distant terminals.
It is, thelefole, an object of the invention to provide a means for testing 25 the wire pair to customer premises in systems employing optical fiber up to the distant t~rmin~l S -mmqry of the Invention This and other objects are achieved in accordance with the invention which, in one aspect, is a digital loop tr~nsmi~sion system comprising a central30 office tçrmin~l, a remote termin~l optically and electrically coupled to the central office termin~l~ and a distant terminal which is optically coupled to the remoteterminal. The system further inciudes means in the distant termin~l for testing electrical wires extçn-ling beyond the distant termin~l and for optically tr~n~mitting the results of said test to the remote terminal. The remote termin~l further comprises means for CO~ ing said results into characteristic resi~t~nces which can be electrically aecesse~l by said central office terminal.
In accordance with a further aspect, the invention is a circuit for electrically testing a pair of wires. Circuit means are provided for ge~ratin~ a5 con~t~nt current having at least two values. Also provided is a bridge circuit having two legs and including means for comparing voltages at the two legs of the circuit.
The circuit further includes means for coupling at least one of the wires to a leg of the bridge circuit.
Brief Description of the Drawin~
These and other features of the invention are deline~ted in detail in the following description. In the drawing:
FM. 1 is a schem~tic block diagram illustrating a digital loop tr~n~mi~ion system in accordance with an embodiment of the invention;
FIG. 2 is a flow diagram illustrating a testing sequence in accordance 15 with an embodiment of the invention;
FIGS. 3-5 are schem~tic diagrams of a circuit for testing drop wires in accordance with an embodiment of the invention;
FM. 6 is a schematic block diagram of a circuit for tr~n~mitting test signals in accordance with an embodiment of the invention;
- 20 FM. 7 is a schematic block diagram of a circuit for receiving test result signals and tr~n~mitting test control information in accordance with the same embo lim~-nt; and FIG. 8 is a schematic diagram of a circuit for exhibiting resist~n-~es in accol~lce with the same embodiment.
25 Detailed Description FM. 1 illustrates in block diagram form a basic digital loop tr~n~mi~sion system in accordance with an aspect of the invention. A central office includes a central office switch 10 and a terminal 11 which is optically and electrically coupled to a remote terminal 12 for providing bidirectional digital30 tr~n~mi~sion. The digital signals are usually carried by optical fibers, but a wire pair 13 is also included between the terminals providing an electrical by-pass for the purpose of testing. This wire pair is coupled to a pair gain test controller 14 which is controlled by a mPch~ni7~d loop tester (MLT) 15. (For more details concerning the pair gain test control arr~ngement, see U.S. Pat. No. 4,270,030.) An optical link 17 20325~9 comlec~ the remote terminal to a distant terminal 16 which is coupled to a plurality of subscribers by wire pairs, only one of which is illustrated as 18.
In accordance with a main feature of the invention, a drop test module 20 is included as a plug-in circuit card at the distant termin~l~ This circuit, as S described in more detail below, is designed to test the wire pairs, e.g. 18, to the various subscribers, and transmit the results in the form of optical data bits through the distant terminal by means of a data link 21 and an opticaVelectronic intPrf~ce 22 back to the remote terrnin~l The remote termin~l in~ludes an O/E interf~ce 24 and data link 23 for receiving the signals and a plurality of resistors which can be10 coupled to the tip and ring conductors of the wire pair 13 by means of relays which are responsive to the data bits from the distant terminal. The MLT lS thereby has electrical access to the results of the drop wire testing in the form of these resistors.
FIG. 2 illustrates a typical testing sequence p~,lro~ ed by the drop test module 20. The first test (designated FEMF) dele~ les the extent of any voltage on lS the line when the distant terrninal is ~i~connçcted (also known as "foreign voltage").
If there is a voltage, typically, of at least 10 volts, the wires fail and no more testing is conducted. If the wires pass that test, they are then tested for any leakage in the wires resulting from faults. This is accomplished in the next step of the diagram by coupling the tip and ring conductors of the wire pair together and dete~ inillg if the 20 colllbined resi~t~nce from the tip and ring conductors to ground is greater than SOK Q. If it is not, the wires fail this first leakage test and the testing is termin~teA
If the wires pass the test (RT R~RD > 50K Q), the wires are subjected to a second leakage test in step three of the diagram. Here, the tip conductor is coupled toground and the resi~t~n~e from ring-to-tip is measured. If this resi~t~n-~e is, again, 25 greater than SOK Q, the wires pass and the next test is pe~rwllled. This test, also known as a "continuity test" deterrnines if the ringer in the c~lstom~r~s telephone is c~ r,d by measuring the c~pacit~nce of the CU~ilQl~f ~ 'S ringer. If the ringer is connected, the wires pass all tests; if not, the wires fail and an in~ tiQn of "no ringer" is given. Going back to step 3, if the resistance is not greater than SOK Q, the 30 wires must be tested further to deterrnine if there is, in fact, a leak or if the cus~ el's receiver is off-hook. These tests are illustrated in the right-hand leg of the diagram. Thus, in the next test, with the tip conductor again grounded, resi~t~nce is measured with a lS milli~mp current applied. If the measured resistance is not less than 650 Q, the wires fail the leak test since the receiver could not exhibit this 35 resi~t~nce if the receiver were off-hook. If the resistance is less than 650 Q, the resistance of ring-to-tip is again measured, since there still might be an off-hook - 2032~4g con~lition, but this time with 1 milli~mr of current through the wires. If the resi~t~n-~e is not greater than 200 Q, the wires fail the leak test since, again, there cannot be an off-hook condition exhibiting this resi~t~nce If the resict~nce is greater than 200 Q, the wires are tested one more time to determine if the resi~t~nce at5 1 milli~mr is more than 60 Q grea-er than the resi~t~nce at 15 milli~mrs If it is, the ~ cei~t~r is off-hook. If it is not, th~ receiver cannot be off-hook and so there must be l.oslc~ge which would result in the wires failing the test. This concl~ldes the testing procedure.
One example of a circuit which is capable of p~_lrolmillg these tests is 10 shown in FIGS. 3-5. FIG. 3 essen~i:llly illustrates the driver section of the circuit.
CMOS switches 100 and 101 will alternatively be enabled to sink either a 1 milli~mp or 15 milli~mp current, respectively, from the tip and ring conductors. The outputs of the switches provide a 2.5 volt reference voltage (generated across diode Dl ) across resistors R2 and R3 to the inverting input of an operational amplifier 102. The 15 non-in~,~,.Ling input of the Op Amp is grounded. The feedb~c~ loop of the Op Amp includes resistors R7, R6 and R4 as well as a pair of Darlington-coupled bipolartransistors, Ql and Q2. In order to drive the voltage at the invelLillg input of the Op Amp to zero volts, a current is drawn through resistor R6 and the tr~nsi~tors Ql and Q2. This current is supplied through resistor R8 to point A of the circuit which has a 20 voltage of -30 volts applied thereto.
A reference current of 0.1 milli~mr or 1.5 milli~mrs is thereby created depending upon which of ~witches 100 or 101 is enabled. Applying this current toR8 activates a x10 current mirror formed by Op Amp 103, resistor Rg and Darlington-coupled bipolar transistors Q3 and Q4. This produces the desired 25 1 milli~mp or 15 milli~mrs current from the cond~lctor labeled Iso~rce through resistor Rlo to point B which is at -30 volts.
As shown in FIG. 4, the drawing of a constant current at the conductor Iso~rCe will establish a voltage Vs at one node of a bridge circuit where resistors Rls and Rl6 constitute one leg. The other leg is formed by either R24 or R2s, depen-ling 30 upon which of solid state relays 104 or 105 is enabled, and the load re~i~t~nce, RL~
formed by the c~lstomer equipment on the conductors labeled Tip and Ring. The tip com1~1ctor is coupled to the node connecting R24 and R2s (labeled Vl ) through a fuse Fl, a relay contact K1B~ a resistor R42 and another relay contact K2. The ring conductor is coupled to the node through fuse F2, relay contact KlC and resistor R43.
35 The voltage Vl at this node is compared with the voltage V2 at the node coupling Rls and Rl6 by means of a differential amplifier including Darlington-coupled ~0~2549 bipolar transistors Q7 and Q8 and resistor Rl8 in one leg, and Darlington-coupled bipolar tr~n~i~tors Qg and Qlo and resistor Rlg in another leg. The output of this dirr~ntial amplifier appears as a high or low voltage on the con(luctor labeled "COMP." A constant current is drawn through the amplifier by a co~ . t current 5 source including bipolar transistors Q5 and Q6 having their base regions coupled in co~ ,on to resistor R2l and their emitters coupled to voltages of -30 volts through resistors R22 (for Q5) and R23 (for Q6).
In order to conduct the foreign voltage test (FEMF < 10V), referring to FIG. 3, a 1 milli:3mr current is established at Iso~rCe by activating switch 100. Also, 10 relay 106 is enabled to connect a 20 volt zener diode, D2, to the same con~ tnr.
Returning to FIG. 4, this establishes a Vs on the cnnl1uctor Is~ rCe of -20 volts. With switches 104 and 105 both disabled, V2 will be equal to -10 volts since Rls and Rl6 are equal. The tip and ring conductors are tied together by closing relay cont~cK1B and KlC and opening relay contact K2. The voltage V1 on the tip and ring 15 conductors is CO~ ,d with the voltage V2 of -10 volts by the dirrelenlial amplifier inslu~ling transistors Q7-Qlo as previously described. If Vl < -10 volts, current in the dirr~ ial amplifier will flow through the Q7-Q8 leg and the output at the COMP conductor will be high, while if Vl 2 -10 volts, the current will flow through Qs-Qlo and the output will be low.
The next few leakage tests can also be pelrolllled by basically the same portion of the circuit described so far. Thus, in the first leakage test shown in FIG. 2 (RT,R~RD ~ SOK Q), tip and ring conductors are again tied together by closing relay contacts K1B and KlC and opening relay contact K2. Switch 100 (of FIG. 3) is enabled to genel~t~ a 1 milli~mr current, while switch 106 (of FIG. 3) is disabled and switch 104 is enabled in order to connect R24, which is a~l,lo~illlately 50K Q, to the tip and ring conductors. Therefore, the voltage Vl will be greater than or equal to V2 if the resistance of the subscriber's line, RL. is less than or equal to 50K Q, and, conversely, V1 will be less than V2 if the subscriber's line resi~t~n5e, RL. is greater than 50K Q. As before, if Vl < V2, current in the differential amplifier will 30 flow through Q7-Q8 and the output at COMP will be high, while if Vl 2 V2, thecurrent will flow through Qg-Qlo and the output will be low. For the second leakage test (RTR ~ 50K Q), the procedure is the same except that relay contact K2 is closed so that the tip con-luctor is grounded.
For the next leakage test (RTR < 650 Q), switch 101 of FIG. 3 is enabled 35 to produce a con~t~nt current of 15 milli~mps at Isource~ Switch 105 (FIG. 4) is also enabled and switch 104 disabled so that now resistor R2s is coupled to the ring -con-luctor (while tip remains grounded by relay contact K2). Since R2s is applu~ tely 650 Q, the output appearing at COMP, which colllp~,s the two voltages Vl and V2 as previously described, will in~ ate whether the resi~t~nce on the subscriber's line is greater than or less than 650 Q.
For purposes of later testing, the voltage Vl appearing when R2s is coupled to tip and ring is coupled to an input of Op Amp 107 by enabling switch 117. The output of Op Amp 107 is coupled to a sample and hold integrated circuit108 after being divided (by 15 in this case) by the resistors R32 and R33. The reslllting voltage is stored on capacitor Clo for later use.
For the next leakage test (RTR > 200 Q), the current at Iso~lrCe is returned to 1 milli~mr~ and R2s continues to be coupled to the tip and ring con~luctors. The resulting voltage Vl is still coupled by switch 117 to Op Amp 107, but the output of the Op Amp is also connected to the non-inverting input of colnp~lor 109. The compdlator co~ es this input with the ratio of resistors R30 to R3l, which in this example is approximately 8.7. With R30 and R3l coupled to a voltage of -5 volts,the co~ tol will produce a signal on the conductor labeled "short" if RL is lessthan or equal to 200 ohms, while no signal will be produced if RL is greater than 200 Q.
The last leakage test (Rl -Rls > 60 Q) is con-lucted by co...l~. ;ng this 20 output of Op Amp 107 with the voltage stored in C~p~Git( r Clo from the previous leakage test which was conducted at 15 millim~ps (RTR < 650 Q). A reference voltage of +2.5 volts applied to resistor R3s subtracts from the output of 107 the equivalent of 60 Q of resistance. The resulting signal is then applied to the inverting input of colllpalator 110, while the voltage stored in c~p~citor C10 is applied to the 25 non-in~,~Ling input through the sample and hold circuit 108. If the signal at the hl~e.ling (-) input is less than that at the non-inverting (+) input, a signal will appear at the conduct-~r labeled ROH to infli~te the receiver is off-hook. If the signal at the in~,~ling input is greater than or equal to that at the non-inverting input, no signal will appear at ROH, thus in-lic~ting that the problem was a leak.
The test for the presence of a ringer on the cu~tomer~s line is made by m~ uring the capacitance between tip and ring. This test makes use of the high voltage which is derived by taking the ringing supply (an AC signal of a~plo~illl&l~ly 20 Hz which is continuously applied to the conductor "20 HZ~ of FIG. 3) and rectifying it by diode D3 to store a voltage of applo~ ly -120 volts35 on c~p~citor C3. This voltage is discharged onto Isource by enabling switch 112 while the energy delivered to the load is restricted by Rll to prevent the telephone from acci~lent~lly ringing. This voltage charges the c~p~it~nre~ CL, on the customer's line (FIG. 4) through resistor R2s by activating switch 105. Zener diodes D4 and Ds limit the voltage stored on the line to -75 volts. The large voltage used (-75V) allows sl~ffiçient charge to be stored on electronic ringers that have zener 5 diodes in series with the capacitor. At the same time, reference c~p~rit~rS C18 and C8 are also charged to the same voltage Vs by enabling switch 111. When ~wilches112, 105, and 111 are disabled, the c~p~itors are disconnected from the voltage Vs.
Enabling switch 1 17 causes the ringer capacitance, CL, to discharge through l~ OlS
R26 and R27 which have a combined resistance of approximately 50K Q. At the 10 same time, reference c~pacitors Cl8 and C8 will discharge through resistor Rl6 which is also equal to approximately 50K Q. After a specified interval, usually a~l.~ tely 10 milli~econds, the voltages Vl and V2 are co~ d by the compal~lor elem~ont as previously described. If Vl is greater than V2, there is a ringer on the line.
It is also desirable in a testing circuit of this type to insure that there are no excessive AC or positive voltages on the tip and ring conductors which could ~m~ge the components of the circuit. Thus, the circuit also provides a means forpre-s.;l~nillg the tip and ring conductors for high voltage prior to the series of tests previously described. This pre-screening is ~ccomplished by routing the tip and ring 20 conductors through relay contacts K1B and KlC of FM. 4 and resistors R46, R47, and R44, R4s to conductr r HV. Any positive voltage on HV will be inverted to a negative voltage by inverter 120 of FIG. 5. As also shown in FIG. 5, the peak value of any AC signal or the DC signal will appear as a negative voltage Vp applied to the hl~ hlg (-) input of coll~arator 114. This voltage, Vp, gets compared with the 25 voltage at the non-inverting (+) input produced by resistors R49 and Rso coupled to a source of -5 volts. Thus, if the absolute m~nitude of the voltage on tip and ring is greater than 10 volts, the output of comparator 114 produces a flag (PRESCREEN) at the pro~;l~lllllable array logic (PAL) chip 115 and the testing will be tern~in~te l As further shown in FIG. 5, the signal on the COMP conductor from the 30 previously-described tests utilizing the comparator including Q7-Qlo of FIG. 4 is coupled to colll~ tor 113 to provide gain and convert to a logic level signal oncon~luctor COMP IN which can be utilized by the PAL 115. That signal as well as the signals previously described which are produced on the ROH, PRESCREEN, and SHORT cond~lctors are all applied to the input portion of the PAL 115. The test 35 results appear as one bit on each of the output leads DTRl, DTR2, and DTR3. The conductor DT DONE in(~ tes when a test is completed. The rem~in-ler of the ` -output conductors are each coupled to one of the switches of the circuit as inrli~ated The conductors labeled Relay 1 and Relay 2 operate, respectively, the relays K1Aand K2A which are associated, respectively, with the relay contacts K1B, KlC, and K2 of FIG. 4. A monostable oscill~tor 116 is also coupled to the PAL to adjust the 5 normal clocking of the PAL during the ringer test to produce the 10 milli~ec period for sampling the discharging car~cit;~nce The outputs from the PAL 115 are then coupled to the data link, 21 of FIG. 1, at the distant termin~l This data link is illustrated in more detail in the block diagram of FIG. 6. As shown, the drop test module 20 is controlled by a 10 microprocessor 201 which initi~tes testing by providing a signal on the TEST lead through a latch 202 after receiving a command (test code) from the central of fice as part of the normal digital stream on data bus 208. This co,.",.~n(l, along with a con~lllalol~ signal (OTR) from the remote termin~l, is coupled to the micluplucessor 201 through latch 210 and specifies which of the channel units 203 15 are to be tested. The test module is coupled to the drop wires through the channel unit 203 serving the subscriber when a relay K10A is operated to close contact K10B-This relay is operated when microprocessor 201 sends a signal through latch 212 and relay driver 213 which is coupled to the relay. (It will be appreciated that only one relay driver and relay are shown, but there typically would be one of each for every 20 channel unit.) The test results from the module are tr~n~mittecl as sepd~aLe bits on leads DTRl, DTR2 and DTR3 to the microprocessor 201 through a latch 204. The test bits are then tr~n~mitted along with other data to separate latches 205, 206 and 207 onto the data bus 208. A multiplexer 209 frames the data bits and scrambles the signal according to well-known techniques. The signal is then coupled to a standard 25 opticaVelectronic interface 22, which comprises a laser and photodetector, for optical tr~nsmi~sion to the remote termin~l The optical data signal is Ll~lsre.~ed via optical link 17 of FIG. 1 from the distant terrnin~l to the O/E interf~ce 24 and data link 23 of FIG. 1 at the remote terminal.
As illustrated in more detail in the block diagram of FIG. 7, the remote 30 termin~l converts the optical signal to an electronic signal by means of a standard opticaVelectronic interf~ce circuit shown as 24. The signals are coupled to a standard protection circuit, illustrated by block 302, and fed to a skew cwllpensator 303 to set the incoming data to the clock (not shown) at the remote termin~l. The skew coll~ellsator can be the type including a programmable array logic chip which 35 is described in U.S. Pat. No. 4,839,907. The signals are then descrambled by standard means 304, such as a custom IC chip which is part of a multiplexer/demultiplexer 309, and coupled to the input of a pro~~ able array logic chip 305 which picks out the bits related to the drop testing and produces them on the lines labeled RLYl, RLY2 and RLY3. These bits are coupled to a standard relay driver 306 which operates relay contacts K4A-K7A. These relays operate the S COnt~Gt~ K4B. KSB. K6B. K7B. K4C. KSC. K6C~ and K7c illustrated in FIG. 8. (The first number in the desi~n~tion of the contact is the same as the first number of the relay to which it corresponds.) FIG. 7 also illustrates the c~ ic~tion path fromthe remote terminal to the distant terminal. A backplane access circuit 307 decodes and tr~n~l~tes digital signals from the central office. This bit stream, which includes 10 a colll"l~l-(l (test code) from the central office to test a channel unit, is put onto the bus 311 and sent through a programmable array logic chip 305 onto bus 312 to themultiplexer/demultiplexer circuit 309. Part of this circuit includes a scrambling circuit 313. The scrambled signal is coupled to the O/E interf~ce 24 and sent to the distant t~rmin~l Referring back to the backplane circuit 307, the test code is also 15 picked off of the incoming data and sent to a bank controller unit (BCU) 308. The BCU decides if the test should take place. If the test is to proceed, a col-r;. .l~to~
signal (OTR) is sent by the BCU through the backplane circuit onto lead 310 to the PAL where the signal is combined with the rest of the incoming signal on bus 312for tr~n~mi~sion to the distant terminal.
The circuit of FIG. 8 is the remote terminal tip-to-ring resistance delta to the central of fice based on which contacts are opened or closed by the data from the drop test. Resistors Rloo and Rlos produce constant ring-to-ground and tip-to-ground resi~t~nce which, in this example is applo~ .lately 91K Q. Resistor R104,which in this example is ap~ ately 18K Q, provides a minimllm resi~t~nce 25 regardless of the test results. Resistors Rlol, Rl02 and Rl03, which in this example are 40K Q, 20K Q, and 10K Q, respectively, will be coupled between tip and ring or shorted out depending on the condition of switches KSC~ K7c and K6C~ respectively, which are normally closed to short out these resistors. The table below gives one example of how the 3-bit messages from the drop test module can indic~te various30 test conllition~ based on the coupling of the various resistors.
TABLE
Bit Message Coll~lition Switches Opened Resistors Coupled S 001 No Drop Test K6C Rl04 and Rl03 Module 010 Pass K7c Rl04 and Rl02 011 NoRinger K6C andK7c Rlo4~Rl03.
and Rl02 100 FEMF/I e~k~ge KSC Rl04 andRloi 101 ROH K6C and KSC R104~ R101 and Rl03 The first condition in the table inflic~tes no drop test module is available. In the event that the optical link between the distant and remote terrnin~l~
25 is not working properly, an open circuit will be presented to the central office by opening switches KSB. K6B. and K7B
It will be appreciated that various values of the circuit components given herein are illustrative and can be varied according to particular needs. Various other lition~ and mr~ific~tion~ will also become a~pal~l t to those skilled in the art. All 30 such vari~tion~ which rely on the teachings through which the invention has advanced the art are pr~e.ly considered within the scope of the invention.
Claims (20)
1. A digital loop transmission system comprising:
a central office terminal;
a remote terminal optically and electrically coupled to the central office terminal;
a distant terminal optically coupled to the remote terminal; and means in the distant terminal for testing electrical wires extending beyond the distant terminal and for optically transmitting the results of said test to the remote terminal.
a central office terminal;
a remote terminal optically and electrically coupled to the central office terminal;
a distant terminal optically coupled to the remote terminal; and means in the distant terminal for testing electrical wires extending beyond the distant terminal and for optically transmitting the results of said test to the remote terminal.
2. The system according to claim 1 further comprising means in the remote terminal for converting said results into characteristic resistances which can be electrically accessed by a loop tester.
3. The system according to claim 1 wherein the testing means includes means for detecting leakage in the wires, the presence of a ringer circuit coupled to the wires and an off-hook condition of equipment coupled to the wires.
4. The system according to claim 3 wherein the testing means includes means for generating a constant current of two different values and for determining the resistance of the wires at these values.
5. The system according to claim 1 wherein the testing means includes a bridge circuit for comparing the resistance on the wires with a known resistance.
6. The system according to claim 1 further comprising means for producing a data signal comprising a predetermined bit length in response to said tests and for combining that signal with other data from the distant terminal for transmission to the remote terminal.
7. The system according to claim 1 wherein the characteristic resistances are generated by a resistor delta including fixed resistances between each wire and ground, and a variable resistance between the two wires.
8. The system according to claim 7 wherein the variable resistance is generated by a plurality of resistors coupled in series between the two wires and individual switches coupled in parallel to each of said resistors, said switches being responsive to the signal transmitted by the testing means to electrically couple one or more of said resistors between the two wires.
9. A circuit for electrically testing a pair of wires comprising:
circuit means for generating a constant current having at least two values;
a bridge circuit having two legs and including means for comparing voltages at the two legs of the circuit; and means for coupling at least one of said wires to a leg of the bridge circuit.
circuit means for generating a constant current having at least two values;
a bridge circuit having two legs and including means for comparing voltages at the two legs of the circuit; and means for coupling at least one of said wires to a leg of the bridge circuit.
10. The circuit according to claim 9 further comprising switching means for alternatively coupling two resistors to the leg of the bridge circuit coupled to at least one of said wires.
11. The circuit according to claim 9 further comprising means for comprising the voltage across the wires to a predetermined maximum value prior to coupling at least one of said wires to the bridge circuit.
12. The circuit according to claim 9 further comprising means for producing a digital output signal having a predetermined bit length, said signal based at least in part on the output of the comparing means.
13. The circuit according to claim 9 wherein the circuit means for generating a constant current comprises an operational amplifier with one input grounded and the other input coupled to a source of reference voltage, and a feedback loop to said other input comprising a pair of bipolar transistors and aresistor through which a constant current is drawn when said transistors are enabled.
14. The circuit according to claim 13 wherein the source of reference voltage is provided alternatively through a pair of switches having different resistors at the output of the switches.
15. The circuit according to claim 9 wherein the means for comparing voltages comprises a differential amplifier having two legs and including Darlington-coupled bipolar transistors and a resistor in different legs, each leg being coupled to a current source.
16. The circuit according to claim 9 further comprising means for coupling a zener diode of a particular breakdown voltage to a leg of the bridge circuit.
17. The circuit according to claim 10 further comprises means for storing the voltage generated at a leg of the bridge circuit when one of said two resistors is coupled thereto.
18. The circuit according to claim 17 further comprising an operational amplifier with one input coupled through a switch to a leg of the bridge circuit and the other input coupled to a pair of resistors so as to produce a signal if the resistance of the wires is greater than a predetermined value.
19. The circuit according to claim 18 further comprising a comparator element with one input coupled to the output of said operational amplifier and the other input coupled to said voltage storing means.
20. The circuit according to claim 9 further comprising reference capacitors coupled through a switch to a node of said bridge circuit, means for charging said capacitors and any capacitors on the wires to the same voltage, and means for discharging said capacitors and said capacitors on the line so that the amount of charge stored is compared by the comparing means of the bridge circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US516,624 | 1990-04-30 | ||
| US07/516,624 US5054050A (en) | 1990-04-30 | 1990-04-30 | Drop testing in fiber to the home systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2032549C true CA2032549C (en) | 1995-01-03 |
Family
ID=24056410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002032549A Expired - Fee Related CA2032549C (en) | 1990-04-30 | 1990-12-18 | Drop testing in fiber to the home systems |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5054050A (en) |
| EP (2) | EP0721292B1 (en) |
| JP (1) | JP2596649B2 (en) |
| KR (1) | KR100242615B1 (en) |
| CA (1) | CA2032549C (en) |
| DE (2) | DE69033792T2 (en) |
| TW (1) | TW219979B (en) |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5073919A (en) * | 1990-10-10 | 1991-12-17 | Teradyne, Inc. | Automatically testing telephone lines |
| GB9104133D0 (en) * | 1991-02-27 | 1991-04-17 | Plessey Telecomm | Remote line test facility |
| AU654570B2 (en) * | 1991-07-30 | 1994-11-10 | Alcatel N.V. | Subscriber loop testing in a fibre-to-the-curb telecommunications network |
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-
1990
- 1990-04-30 US US07/516,624 patent/US5054050A/en not_active Expired - Lifetime
- 1990-12-17 DE DE69033792T patent/DE69033792T2/en not_active Expired - Fee Related
- 1990-12-17 EP EP96103149A patent/EP0721292B1/en not_active Expired - Lifetime
- 1990-12-17 EP EP90313760A patent/EP0454926B1/en not_active Expired - Lifetime
- 1990-12-17 DE DE69030081T patent/DE69030081T2/en not_active Expired - Fee Related
- 1990-12-18 CA CA002032549A patent/CA2032549C/en not_active Expired - Fee Related
-
1991
- 1991-04-15 JP JP10811191A patent/JP2596649B2/en not_active Expired - Fee Related
- 1991-04-23 KR KR1019910006478A patent/KR100242615B1/en not_active IP Right Cessation
- 1991-04-27 TW TW080103318A patent/TW219979B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| TW219979B (en) | 1994-02-01 |
| KR100242615B1 (en) | 2000-02-01 |
| KR910019364A (en) | 1991-11-30 |
| EP0454926A3 (en) | 1994-01-19 |
| EP0721292B1 (en) | 2001-09-05 |
| DE69030081D1 (en) | 1997-04-10 |
| JPH04229757A (en) | 1992-08-19 |
| DE69033792D1 (en) | 2001-10-11 |
| EP0454926A2 (en) | 1991-11-06 |
| DE69033792T2 (en) | 2002-05-23 |
| EP0721292A1 (en) | 1996-07-10 |
| JP2596649B2 (en) | 1997-04-02 |
| DE69030081T2 (en) | 1997-08-28 |
| US5054050A (en) | 1991-10-01 |
| EP0454926B1 (en) | 1997-03-05 |
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Legal Events
| Date | Code | Title | Description |
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| EEER | Examination request | ||
| MKLA | Lapsed |