CA2024850C - Amplifying with directly coupled, cascaded amplifiers - Google Patents
Amplifying with directly coupled, cascaded amplifiersInfo
- Publication number
- CA2024850C CA2024850C CA002024850A CA2024850A CA2024850C CA 2024850 C CA2024850 C CA 2024850C CA 002024850 A CA002024850 A CA 002024850A CA 2024850 A CA2024850 A CA 2024850A CA 2024850 C CA2024850 C CA 2024850C
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- Prior art keywords
- amplifier
- amplifiers
- signal
- port
- potential
- Prior art date
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0216—Continuous control
- H03F1/0233—Continuous control by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2178—Class D power amplifiers; Switching amplifiers using more than one switch or switching amplifier in parallel or in series
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/405—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising more than three power stages
Abstract
A signal is amplified with a plurality of amplifiers, each amplifier having a reference port, a reference node coupled to the reference port, and a signal port, and each amplifier being supplied by a power source with operating potential with respect to the reference node that is coupled to the reference port of that amplifier. The amplifiers are cascaded in a manner selected so that the output of a first amplifier (which receives the signal to be amplified at its input port) drives the reference node of a second amplifier, and the reference node of the first amplifier provides an input at the signal port of the second amplifier, whereby the first and second amplifiers are directly coupled together to amplify the applied signal.
Description
Amplifying with Directly Coupled, Cascaded Amplifiers Background of the Invention This invention relates to amplifying schemes which use a number of amplifiers to provide output voltage and power swings greater than those available from a single amplifier.
It is known to cascade amplifiers in series, parallel, or in series/parallel combinations, to increase the overall voltage swing and power output of the amplifier arrangement without increasing the magnitude of the power supply voltages) and also to facilitate impedance matching to loads.
In some arrangements, for example, those described in U.S. Patent 4,454,480, issued to Allfather et al., identical amplifiers are cascaded between a common (e. g., ground) terminal and an output terminal.
Each amplifier includes a dual polarity power supply, the common (i.e.) reference) node of which is driven by the output of the immediately preceding amplifier in the cascade arrangement. A signal to be amplified is 20~ applied in series to the inputs of the amplifiers.
Typically, the signal is applied between the common node of each amplifier's power supply and the input of the amplifier using an isolation amplifier or an isolation transformer. Because each signal is referenced at the same potential as the power supply of the amplifier to which the signal is applied, the source of the signal to be amplified must be capable of producing voltage swings that are greater than the voltage swings generated by a single amplifier.
It is known to cascade amplifiers in series, parallel, or in series/parallel combinations, to increase the overall voltage swing and power output of the amplifier arrangement without increasing the magnitude of the power supply voltages) and also to facilitate impedance matching to loads.
In some arrangements, for example, those described in U.S. Patent 4,454,480, issued to Allfather et al., identical amplifiers are cascaded between a common (e. g., ground) terminal and an output terminal.
Each amplifier includes a dual polarity power supply, the common (i.e.) reference) node of which is driven by the output of the immediately preceding amplifier in the cascade arrangement. A signal to be amplified is 20~ applied in series to the inputs of the amplifiers.
Typically, the signal is applied between the common node of each amplifier's power supply and the input of the amplifier using an isolation amplifier or an isolation transformer. Because each signal is referenced at the same potential as the power supply of the amplifier to which the signal is applied, the source of the signal to be amplified must be capable of producing voltage swings that are greater than the voltage swings generated by a single amplifier.
Summary of the Invention The invention features, in general, amplifying a signal with a plurality of amplifiers, each amplifier having a reference port and a signal port and each amplifier being supplied by a power source with operating potential with respect to a reference node that is coupled to the reference port of that amplifier; the amplifiers are cascaded in a manner selected so that the output of a first amplifier (which receives the signal to be amplified at its input port) drives the reference node of a second amplifier, and the reference node of the first amplifier provides an input at the signal port of the second amplifier, whereby the first and second amplifiers are directly coupled together to amplify the applied signal.
Because the amplifiers (e. g., Class B amplifiers) are directly cascaded, the need for signal isolation amplifiers, signal isolation transformers, or other devices between the amplifiers is eliminated. As a result, the source of the input signal need not provide a voltage swing greater than that which can be produced by a single amplifier. Because each amplifier reproduces the voltage between the reference node of its power source (i.e., the output of the previous stage) and the voltage at the reference node of the previous stage, input signal voltage and power are both cascaded and amplified.
In general, the performance parameters of the amplifiers are additive in this arrangement. For example, if there are N amplifiers which have identical unity inverting voltage gains (A~) and identical current gains (AI), the total voltage gain is N~A~ and the overall power gain is N multiplied by the power gain of a single amplifier. For example, if A~ _ -1, the total voltage gain is -N. Also, the total slew rate equals N
multiplied by the slew rate of one amplifier. On the other hand, the overall current pain of the arrangement equals the current gain of a single stage, and the total gain-bandwidth is that of a single stage. Moreover, if the N power supplies for the N amplifiers each supply an operating potential V, the cascaded amplifiers can produce an output signal having a maximum (i.e., nonclipped) voltage of N~V volts.
Preferred embodiments include the following features.
The amplifiers are cascaded by electrically coupling the output of the first amplifier to the reference port of the second amplifier, and connecting the reference port of the first amplifier to the signal port of the second amplifier.
Alternatively, the amplifiers can be arranged to amplify the input signal in parallel. This is done by decoupling the .reference port of the second amplifier from the output of the first amplifier and decoupling the signal port of the second amplifier from the reference port of the first amplifier. Instead, the signal ports of the first and second amplifiers are coupled together and the outputs of the first and second amplifiers are also coupled together. In this case, the reference ports of the first.and second amplifiers are coupled to a reference (e.g., ground) potential, and resistances are coupled in series with the amplifier outputs to compensate for small differences in amplifier parameters (e. g., gain and offset).
The power sources each convert an applied A.C.
potential to D.C. potentials having opposite polarities and couple the D.C. potentials to the associated amplifier. This is preferably done with a power transformer that has a primary winding coupled to a source of A.C. potential and a secondary winding for developing the D.C. potentials; the secondary winding includes a center tap that forms the common node of the power source.
Other features and advantages of the invention will be apparent from the following detailed description, and from the claims, with reference to the accompanying drawings in which:
Brief Description of the Drawings Fig. 1 is a block diagram of the amplifying system of the invention;
Figs. 2A-2E are waveforms useful in understanding the operation of Fig. 1;
Fig. 3 is a schematic diagram of the amplifying system of Fig. 1;
Fig. 4 is an alternative arrangement of the amplifying system of Fig. 3; and Fig. S is a diagram of one embodiment of the power supplies used in Figs. 1, 3, and 4.
Detailed Description Referring to Fig. 1, the amplifying system 10 of the invention includes a plurality of (such as four) amplifiers 12, 14, 16, 18 that are preferably identical Class B devices. Each amplifier (e.g., amplifier 12) includes a signal-input port (sig) 20 and a reference port (ref) 22. The output 24 of each amplifier (e. g., amplifier 12) is connected to the next succeeding amplifier (e. g., amplifier 14) and as a result amplifiers 12-18 are serially cascaded between input terminal 26 and output terminal 28.
Amplifiers 12, 14, 16, 18 operate using dedicated dual-polarity D.C. power supplies 30, 32, 34, 36, respectively, which are each represented in Fig. 1 -202485p by a pair of batteries Vss. Each power supply is arranged to couple potentials of +Vss and -Vss with respect to its own common node C to the associated amplifier. The common node C of power supply 30 is connected to ground potential, while the common nodes of power supplies 32, 34, 36 "float" above ground.
Amplifiers 12-18 are directly cascaded according to the invention so that the signal needed to drive each amplifier is supplied directly by the preceding amplifier, without the use of any isolation amplifiers, isolation transformers, or instrumentation amplifiers between amplifiers 12-18. The output 24 of each stage drives the floating common node C of the power supply of the next succeeding amplifier, and the reference port 22 of each stage is connected to the signal port 20 of the following stage. For example, output 24 of amplifier 12 drives common node C of power supply 32, which is in turn connected to reference port 22 of amplifier.l4. Signal port 20 of amplifier 14 gets its input directly from reference port 22 of amplifier 12.
This cascading scheme is followed for the remaining amplifiers in the arrangement. ,Thus, the output of amplifier 14 is applied to common node C of power supply 34 and the reference port of amplifier 16, the signal port 20 of which is connected to reference port 22 of amplifier 14. Common node C of power supply 36 (and hence reference port 22 of amplifier 18) is driven by the output of amplifier 16, the reference port 22 of which is tied to signal port 20 of amplifier 18.
The arrangement is completed by connecting input terminal 26 (which is referenced to ground) to signal port 20 of amplifier 12, and connecting output port 24 of amplifier 18 to output terminal 28. Output terminal 28 is also referenced to ground.
202485p Referring also to Figs. 2A-2E, in operation, let each amplifier have an inverting unity gain. With an input voltage VIN as shown in Fig. 2A, the output voltages of amplifiers 12 (V1), 14 (V2), 16 (V3), and 18 (Vout) are shown in Figs. 2B-2E, respectively.
Each amplifier/power supply stage amplifies the voltage between its power supply common node C (i.e., the output of the previous stage) and the common node C of the power supply of the immediately preceding stage. As a result, the total voltage gain of amplifying arrangement 10 is the sum of the voltage gains (A~) of individual amplifiers 12-18 (i.e., 4). That is Vout 'vl + -v2 + -w3 + --V4 VIN
Also, because amplifiers 12-18 are identical and connected in series, current gain (AI) of arrangement 10 equal those of a single amplifier. Accordingly, I1 _ I2 = I3 _ I4 It is thus seen that the power gain is also additive, the total power gain equalling the power gain of an individual amplifier multiplied by the number of cascaded amplifiers.
Note also from~Figs. 2B-2E that, although each amplifier 12-18 operates from a power supply of +Vss' all amplifiers except for initial amplifier 12 can produce outputs having greater voltage-swing than +Vss without clipping. This is because of the serial cascading of amplifiers 12-18. In general, (assuming equal Vss magnitudes for all power supplies) the maximum voltage swing of the arrangement is equal to the number of amplifiers multiplied by the maximum voltage swing (+Vss) of one amplifier. Thus, amplifier 14 can generate an output of +2Vss, an output of +3Vss can be produced by amplifier 16, and the total voltage swing of arrangement 10 (at output terminal 28) is +4Vss' 2o24s5Q
-,_ Other advantages follow from serially cascading amplifiers 12-18 as in Fig. 1. For example) the slew rate of arrangement l0 becomes the slew rate of a single amplifier multiplied by the number of amplifiers.
Referring to Fig. 3, a specific circuit 100 for implementing amplifying arrangement 10 (Fig. 1) is shown. Amplifying system 100 comprises a plurality of (such as four) identical amplifier circuit sections 102, 104, 106, 108. Sections 102-108 respectively include differential amplifiers 112-118 and power supplies 130-136. Each power supply 130-136 is represented by a pair of batteries connected to provide operating potentials of _+Vss (with respect to a common power supply node C) to the associated amplifiers 112-118.
Each amplifier section 102-108 also includes a set of switches 138, 140, 142 for cascading sections 102-108 between a source 126 of input voltage (VIN) and an output terminal 128.
One switched terminal of switches 138 in sections 108, 106, 104 is connected to input voltage source 126, and the other switched terminal of each such switch 138 is connected to the common node C of the power supply 134, 132, 130 of the immediately preceding amplifier section 106, 104, 102, respectively. Hoth switched terminals of switch 138 in amplifier section 102 are connected to source 126.. _ Amplifiers 112-118 are operational amplifiers having a gain of -1 as determined by resistors Ri and Rf. The inverting (-) input of each amplifier 112-118 (e. g., amplifier 114) is driven from the common terminal of switch 138 in its amplifier section (e. g., section 104) and the noninverting (+) input provides a reference and is connected to the common node C of the amplifier's power supply (e. g., power supply 132).
. 2024850 _$_ Amplifiers 112-116 drive either the next succeeding amplifier 114-118, respectively, or output terminal 128 via switches 140. More specifically, the outputs of amplifiers 112, 114, 116 are connected to the floating common nodes C of power supplies 132) 134, 136, respectively, when switches 140 are in the position shown in Fig. 3. When switches 140 are in the opposite position (as shown in Fig. 4, discussed below), amplifiers 112-118 drive output terminal 128 in parallel through resistors Re. The output of amplifier 118 always drives output terminal 122 through its switch 140.
Amplifying system 100 is referenced to the same potential (e.g., ground) as voltage source 126. To establish this reference potential, the common node C of power supply 130 (and hence the noninverting (i.e., reference) input of amplifier 112) is always connected to ground potential, either directly or through switch 142. Switches 142 operate in tandem with switches 140 to alternatively. connect the common nodes C power supplies 132-136 to ground potential when amplifiers 112-118 are to operate in parallel (as explained below in connection with Fig. 4).
In operation, with switches 138, 140, 142 all in the positions shown in Fig. 3, amplifiers 112-118 are serially cascaded between voltage source 126 and output terminal 128 and operate in the same manner as described above for amplifying-system 10: Amplifying system 100 thus has a total voltage gain of -4 (i.e., the sum of the four inverting unity gains of amplifiers 112-118).
On the other hand, the output currents I1-I4 of amplifiers 112-118, respectively, are all equal. That is, the total current gain of system 100 equals the current gain of a single amplifier. The maximum voltage swing of the output signal produced at terminal 128 is +4Vss, as discussed above.
_ g _ Referring to Fig. 4, when switches 138, 140, 142 are all actuated to their opposite positions, amplifiers 112-118 are cascaded in parallel between voltage source 126 and output terminal 128 through switches 138, 140. Also, the common node C of each power supply 130-136 (and thus the noninverting input of each amplifier 112-118) is connected to ground potential through switches 142. As a result, the total voltage gain of system 100 becomes that of a single amplifier (i.e., -1). On the other hand, the output currents I1-I4 add, and hence the total current gain is four times the current gain of each amplifier 112-118.
Resistors Re are present to compensate for small differences in the parameters (such as gain and offset) of amplifiers 112-118. The closer that the amplifiers are matched, the smaller equalizing resistors Re may be. As the resistances of resistors Re decrease, so, too, are the errors and deficiencies that they cause reduced.
Other embodiments are within the following claims.
For example, although four amplifiers have been shown, more or fewer amplifiers can be cascaded in accordance with the invention.
Referring to Fig. 5, power supplies 30-36, - 130=136-can'each be implemented-by-fnll-wave rectifying an A.C. signal from source 150 using a transformer 152 having a center tapped secondary winding 154 and a diode bridge 156. The center tap becomes the common node C of the power supply and also serves as the reference for D.C. supply voltages +Vss and for ripple capacitors 158.
Because the amplifiers (e. g., Class B amplifiers) are directly cascaded, the need for signal isolation amplifiers, signal isolation transformers, or other devices between the amplifiers is eliminated. As a result, the source of the input signal need not provide a voltage swing greater than that which can be produced by a single amplifier. Because each amplifier reproduces the voltage between the reference node of its power source (i.e., the output of the previous stage) and the voltage at the reference node of the previous stage, input signal voltage and power are both cascaded and amplified.
In general, the performance parameters of the amplifiers are additive in this arrangement. For example, if there are N amplifiers which have identical unity inverting voltage gains (A~) and identical current gains (AI), the total voltage gain is N~A~ and the overall power gain is N multiplied by the power gain of a single amplifier. For example, if A~ _ -1, the total voltage gain is -N. Also, the total slew rate equals N
multiplied by the slew rate of one amplifier. On the other hand, the overall current pain of the arrangement equals the current gain of a single stage, and the total gain-bandwidth is that of a single stage. Moreover, if the N power supplies for the N amplifiers each supply an operating potential V, the cascaded amplifiers can produce an output signal having a maximum (i.e., nonclipped) voltage of N~V volts.
Preferred embodiments include the following features.
The amplifiers are cascaded by electrically coupling the output of the first amplifier to the reference port of the second amplifier, and connecting the reference port of the first amplifier to the signal port of the second amplifier.
Alternatively, the amplifiers can be arranged to amplify the input signal in parallel. This is done by decoupling the .reference port of the second amplifier from the output of the first amplifier and decoupling the signal port of the second amplifier from the reference port of the first amplifier. Instead, the signal ports of the first and second amplifiers are coupled together and the outputs of the first and second amplifiers are also coupled together. In this case, the reference ports of the first.and second amplifiers are coupled to a reference (e.g., ground) potential, and resistances are coupled in series with the amplifier outputs to compensate for small differences in amplifier parameters (e. g., gain and offset).
The power sources each convert an applied A.C.
potential to D.C. potentials having opposite polarities and couple the D.C. potentials to the associated amplifier. This is preferably done with a power transformer that has a primary winding coupled to a source of A.C. potential and a secondary winding for developing the D.C. potentials; the secondary winding includes a center tap that forms the common node of the power source.
Other features and advantages of the invention will be apparent from the following detailed description, and from the claims, with reference to the accompanying drawings in which:
Brief Description of the Drawings Fig. 1 is a block diagram of the amplifying system of the invention;
Figs. 2A-2E are waveforms useful in understanding the operation of Fig. 1;
Fig. 3 is a schematic diagram of the amplifying system of Fig. 1;
Fig. 4 is an alternative arrangement of the amplifying system of Fig. 3; and Fig. S is a diagram of one embodiment of the power supplies used in Figs. 1, 3, and 4.
Detailed Description Referring to Fig. 1, the amplifying system 10 of the invention includes a plurality of (such as four) amplifiers 12, 14, 16, 18 that are preferably identical Class B devices. Each amplifier (e.g., amplifier 12) includes a signal-input port (sig) 20 and a reference port (ref) 22. The output 24 of each amplifier (e. g., amplifier 12) is connected to the next succeeding amplifier (e. g., amplifier 14) and as a result amplifiers 12-18 are serially cascaded between input terminal 26 and output terminal 28.
Amplifiers 12, 14, 16, 18 operate using dedicated dual-polarity D.C. power supplies 30, 32, 34, 36, respectively, which are each represented in Fig. 1 -202485p by a pair of batteries Vss. Each power supply is arranged to couple potentials of +Vss and -Vss with respect to its own common node C to the associated amplifier. The common node C of power supply 30 is connected to ground potential, while the common nodes of power supplies 32, 34, 36 "float" above ground.
Amplifiers 12-18 are directly cascaded according to the invention so that the signal needed to drive each amplifier is supplied directly by the preceding amplifier, without the use of any isolation amplifiers, isolation transformers, or instrumentation amplifiers between amplifiers 12-18. The output 24 of each stage drives the floating common node C of the power supply of the next succeeding amplifier, and the reference port 22 of each stage is connected to the signal port 20 of the following stage. For example, output 24 of amplifier 12 drives common node C of power supply 32, which is in turn connected to reference port 22 of amplifier.l4. Signal port 20 of amplifier 14 gets its input directly from reference port 22 of amplifier 12.
This cascading scheme is followed for the remaining amplifiers in the arrangement. ,Thus, the output of amplifier 14 is applied to common node C of power supply 34 and the reference port of amplifier 16, the signal port 20 of which is connected to reference port 22 of amplifier 14. Common node C of power supply 36 (and hence reference port 22 of amplifier 18) is driven by the output of amplifier 16, the reference port 22 of which is tied to signal port 20 of amplifier 18.
The arrangement is completed by connecting input terminal 26 (which is referenced to ground) to signal port 20 of amplifier 12, and connecting output port 24 of amplifier 18 to output terminal 28. Output terminal 28 is also referenced to ground.
202485p Referring also to Figs. 2A-2E, in operation, let each amplifier have an inverting unity gain. With an input voltage VIN as shown in Fig. 2A, the output voltages of amplifiers 12 (V1), 14 (V2), 16 (V3), and 18 (Vout) are shown in Figs. 2B-2E, respectively.
Each amplifier/power supply stage amplifies the voltage between its power supply common node C (i.e., the output of the previous stage) and the common node C of the power supply of the immediately preceding stage. As a result, the total voltage gain of amplifying arrangement 10 is the sum of the voltage gains (A~) of individual amplifiers 12-18 (i.e., 4). That is Vout 'vl + -v2 + -w3 + --V4 VIN
Also, because amplifiers 12-18 are identical and connected in series, current gain (AI) of arrangement 10 equal those of a single amplifier. Accordingly, I1 _ I2 = I3 _ I4 It is thus seen that the power gain is also additive, the total power gain equalling the power gain of an individual amplifier multiplied by the number of cascaded amplifiers.
Note also from~Figs. 2B-2E that, although each amplifier 12-18 operates from a power supply of +Vss' all amplifiers except for initial amplifier 12 can produce outputs having greater voltage-swing than +Vss without clipping. This is because of the serial cascading of amplifiers 12-18. In general, (assuming equal Vss magnitudes for all power supplies) the maximum voltage swing of the arrangement is equal to the number of amplifiers multiplied by the maximum voltage swing (+Vss) of one amplifier. Thus, amplifier 14 can generate an output of +2Vss, an output of +3Vss can be produced by amplifier 16, and the total voltage swing of arrangement 10 (at output terminal 28) is +4Vss' 2o24s5Q
-,_ Other advantages follow from serially cascading amplifiers 12-18 as in Fig. 1. For example) the slew rate of arrangement l0 becomes the slew rate of a single amplifier multiplied by the number of amplifiers.
Referring to Fig. 3, a specific circuit 100 for implementing amplifying arrangement 10 (Fig. 1) is shown. Amplifying system 100 comprises a plurality of (such as four) identical amplifier circuit sections 102, 104, 106, 108. Sections 102-108 respectively include differential amplifiers 112-118 and power supplies 130-136. Each power supply 130-136 is represented by a pair of batteries connected to provide operating potentials of _+Vss (with respect to a common power supply node C) to the associated amplifiers 112-118.
Each amplifier section 102-108 also includes a set of switches 138, 140, 142 for cascading sections 102-108 between a source 126 of input voltage (VIN) and an output terminal 128.
One switched terminal of switches 138 in sections 108, 106, 104 is connected to input voltage source 126, and the other switched terminal of each such switch 138 is connected to the common node C of the power supply 134, 132, 130 of the immediately preceding amplifier section 106, 104, 102, respectively. Hoth switched terminals of switch 138 in amplifier section 102 are connected to source 126.. _ Amplifiers 112-118 are operational amplifiers having a gain of -1 as determined by resistors Ri and Rf. The inverting (-) input of each amplifier 112-118 (e. g., amplifier 114) is driven from the common terminal of switch 138 in its amplifier section (e. g., section 104) and the noninverting (+) input provides a reference and is connected to the common node C of the amplifier's power supply (e. g., power supply 132).
. 2024850 _$_ Amplifiers 112-116 drive either the next succeeding amplifier 114-118, respectively, or output terminal 128 via switches 140. More specifically, the outputs of amplifiers 112, 114, 116 are connected to the floating common nodes C of power supplies 132) 134, 136, respectively, when switches 140 are in the position shown in Fig. 3. When switches 140 are in the opposite position (as shown in Fig. 4, discussed below), amplifiers 112-118 drive output terminal 128 in parallel through resistors Re. The output of amplifier 118 always drives output terminal 122 through its switch 140.
Amplifying system 100 is referenced to the same potential (e.g., ground) as voltage source 126. To establish this reference potential, the common node C of power supply 130 (and hence the noninverting (i.e., reference) input of amplifier 112) is always connected to ground potential, either directly or through switch 142. Switches 142 operate in tandem with switches 140 to alternatively. connect the common nodes C power supplies 132-136 to ground potential when amplifiers 112-118 are to operate in parallel (as explained below in connection with Fig. 4).
In operation, with switches 138, 140, 142 all in the positions shown in Fig. 3, amplifiers 112-118 are serially cascaded between voltage source 126 and output terminal 128 and operate in the same manner as described above for amplifying-system 10: Amplifying system 100 thus has a total voltage gain of -4 (i.e., the sum of the four inverting unity gains of amplifiers 112-118).
On the other hand, the output currents I1-I4 of amplifiers 112-118, respectively, are all equal. That is, the total current gain of system 100 equals the current gain of a single amplifier. The maximum voltage swing of the output signal produced at terminal 128 is +4Vss, as discussed above.
_ g _ Referring to Fig. 4, when switches 138, 140, 142 are all actuated to their opposite positions, amplifiers 112-118 are cascaded in parallel between voltage source 126 and output terminal 128 through switches 138, 140. Also, the common node C of each power supply 130-136 (and thus the noninverting input of each amplifier 112-118) is connected to ground potential through switches 142. As a result, the total voltage gain of system 100 becomes that of a single amplifier (i.e., -1). On the other hand, the output currents I1-I4 add, and hence the total current gain is four times the current gain of each amplifier 112-118.
Resistors Re are present to compensate for small differences in the parameters (such as gain and offset) of amplifiers 112-118. The closer that the amplifiers are matched, the smaller equalizing resistors Re may be. As the resistances of resistors Re decrease, so, too, are the errors and deficiencies that they cause reduced.
Other embodiments are within the following claims.
For example, although four amplifiers have been shown, more or fewer amplifiers can be cascaded in accordance with the invention.
Referring to Fig. 5, power supplies 30-36, - 130=136-can'each be implemented-by-fnll-wave rectifying an A.C. signal from source 150 using a transformer 152 having a center tapped secondary winding 154 and a diode bridge 156. The center tap becomes the common node C of the power supply and also serves as the reference for D.C. supply voltages +Vss and for ripple capacitors 158.
Claims (13)
1. Apparatus for amplifying a signal, comprising a plurality of amplifiers, each amplifier having a reference port, a reference node coupled to said reference port, and a signal port, said signal being applied to the signal port of a first one of said amplifiers, a plurality of power sources, each power source supplying operating potential to one. of said amplifiers with respect to the reference node that is coupled to said reference port of said amplifier, and circuitry for cascading said amplifiers in a manner selected so that an output of said first amplifier drives the reference node of a second one of said amplifiers, and the reference node of said first amplifier provides an input at the signal port of said second amplifier, whereby said first and second amplifiers are directly coupled together to amplify said signal.
2. The apparatus of claim 1 wherein said cascading circuitry electrically couples the output of said first amplifier to the reference port of said second amplifier, and connects the reference port of said first amplifier to the signal port of said second amplifier.
3. The apparatus of claim 2 wherein the reference port of said first amplifier is coupled to a reference potential equal to a reference potential for said input signal.
4. The apparatus of claim 1 wherein said plurality of power sources each comprises circuitry for converting an A.C. potential applied to said power source to a pair of D.C. potentials having opposite polarities and equal magnitudes with respect to a potential at said reference node, and applying said D.C.
potentials to said amplifier.
potentials to said amplifier.
5. The apparatus of claim 4 wherein said converting circuitry comprises a transformer having a primary winding coupled to a source of A.C. potential and a secondary winding for developing said D.C.
potentials, said secondary winding having a center tap that comprises the reference node.
potentials, said secondary winding having a center tap that comprises the reference node.
6. The apparatus of claim 2 wherein said cascading circuitry further comprises switching circuitry for selectively (a) decoupling the reference port of said second amplifier from the output of said first amplifier, and decoupling the signal port of said second amplifier from the reference port of said first amplifier, and (b) coupling the signal ports of said first and second amplifiers together and coupling the outputs of said first and second amplifiers together, whereby said first and second amplifiers amplify said signal in parallel.
7. The apparatus of claim 6 wherein said cascading circuitry further comprises switching circuitry for selectively coupling the reference ports of said first and second amplifiers to a common reference potential when said amplifiers are amplifying in parallel.
8. The apparatus of claim 6 further comprising circuitry for coupling resistances in series with the outputs of said first and .second amplifiers when said outputs are coupled together.
9. The apparatus of claim 1 wherein there are N amplifiers having substantially identical gains, whereby the total voltage gain of the apparatus equals N
multiplied by the voltage gain of a single amplifier and the total current gain of the apparatus equals the current gain of one amplifier.
multiplied by the voltage gain of a single amplifier and the total current gain of the apparatus equals the current gain of one amplifier.
10. The apparatus of claim 9 wherein said substantially identical gains equal -1.
11. The apparatus of claim 1 wherein there are N power sources supplying operating potentials of substantially the same magnitude, V, whereby the apparatus can produce an output signal having a maximum potential of N multiplied by V.
12. The apparatus of claim 1 wherein said plurality of amplifiers are like power amplifiers.
13. The apparatus of claim 12 wherein said plurality of amplifiers are class B amplifiers.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/328,051 US4973919A (en) | 1989-03-23 | 1989-03-23 | Amplifying with directly coupled, cascaded amplifiers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2024850A1 CA2024850A1 (en) | 1992-03-08 |
| CA2024850C true CA2024850C (en) | 1999-11-09 |
Family
ID=23279299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002024850A Expired - Fee Related CA2024850C (en) | 1989-03-23 | 1990-09-07 | Amplifying with directly coupled, cascaded amplifiers |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4973919A (en) |
| EP (1) | EP0474930B1 (en) |
| AT (1) | ATE134088T1 (en) |
| AU (1) | AU629685B2 (en) |
| CA (1) | CA2024850C (en) |
| DE (1) | DE69025324T2 (en) |
| DK (1) | DK0474930T3 (en) |
| ES (1) | ES2085896T3 (en) |
| GR (1) | GR3019358T3 (en) |
Families Citing this family (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4973919A (en) * | 1989-03-23 | 1990-11-27 | Doble Engineering Company | Amplifying with directly coupled, cascaded amplifiers |
| DE4139762C2 (en) * | 1991-12-03 | 1996-09-12 | Daimler Benz Aerospace Ag | Circuit arrangement for switching high capacitive loads at a certain voltage level |
| US5317277A (en) * | 1992-12-08 | 1994-05-31 | Doble Engineering Company | Power amplifying apparatus for supplying A.C. signals having a maximum loop gain at a desired frequency |
| US8362838B2 (en) * | 2007-01-19 | 2013-01-29 | Cirrus Logic, Inc. | Multi-stage amplifier with multiple sets of fixed and variable voltage rails |
| US7667408B2 (en) * | 2007-03-12 | 2010-02-23 | Cirrus Logic, Inc. | Lighting system with lighting dimmer output mapping |
| US8018171B1 (en) | 2007-03-12 | 2011-09-13 | Cirrus Logic, Inc. | Multi-function duty cycle modifier |
| US8076920B1 (en) | 2007-03-12 | 2011-12-13 | Cirrus Logic, Inc. | Switching power converter and control system |
| US7852017B1 (en) | 2007-03-12 | 2010-12-14 | Cirrus Logic, Inc. | Ballast for light emitting diode light sources |
| US20080224631A1 (en) * | 2007-03-12 | 2008-09-18 | Melanson John L | Color variations in a dimmable lighting device with stable color temperature light sources |
| US7696913B2 (en) | 2007-05-02 | 2010-04-13 | Cirrus Logic, Inc. | Signal processing system using delta-sigma modulation having an internal stabilizer path with direct output-to-integrator connection |
| US7554473B2 (en) | 2007-05-02 | 2009-06-30 | Cirrus Logic, Inc. | Control system using a nonlinear delta-sigma modulator with nonlinear process modeling |
| US8102127B2 (en) * | 2007-06-24 | 2012-01-24 | Cirrus Logic, Inc. | Hybrid gas discharge lamp-LED lighting system |
| US7804697B2 (en) | 2007-12-11 | 2010-09-28 | Cirrus Logic, Inc. | History-independent noise-immune modulated transformer-coupled gate control signaling method and apparatus |
| US8008898B2 (en) | 2008-01-30 | 2011-08-30 | Cirrus Logic, Inc. | Switching regulator with boosted auxiliary winding supply |
| US8576589B2 (en) | 2008-01-30 | 2013-11-05 | Cirrus Logic, Inc. | Switch state controller with a sense current generated operating voltage |
| US8022683B2 (en) | 2008-01-30 | 2011-09-20 | Cirrus Logic, Inc. | Powering a power supply integrated circuit with sense current |
| US7755525B2 (en) * | 2008-01-30 | 2010-07-13 | Cirrus Logic, Inc. | Delta sigma modulator with unavailable output values |
| US7759881B1 (en) | 2008-03-31 | 2010-07-20 | Cirrus Logic, Inc. | LED lighting system with a multiple mode current control dimming strategy |
| US8008902B2 (en) | 2008-06-25 | 2011-08-30 | Cirrus Logic, Inc. | Hysteretic buck converter having dynamic thresholds |
| US8212491B2 (en) | 2008-07-25 | 2012-07-03 | Cirrus Logic, Inc. | Switching power converter control with triac-based leading edge dimmer compatibility |
| US8014176B2 (en) | 2008-07-25 | 2011-09-06 | Cirrus Logic, Inc. | Resonant switching power converter with burst mode transition shaping |
| US8344707B2 (en) | 2008-07-25 | 2013-01-01 | Cirrus Logic, Inc. | Current sensing in a switching power converter |
| US8487546B2 (en) * | 2008-08-29 | 2013-07-16 | Cirrus Logic, Inc. | LED lighting system with accurate current control |
| US8222872B1 (en) | 2008-09-30 | 2012-07-17 | Cirrus Logic, Inc. | Switching power converter with selectable mode auxiliary power supply |
| RU2402862C2 (en) | 2008-09-30 | 2010-10-27 | Игорь Владиславович Захаров | Variable signal converter |
| US8179110B2 (en) | 2008-09-30 | 2012-05-15 | Cirrus Logic Inc. | Adjustable constant current source with continuous conduction mode (“CCM”) and discontinuous conduction mode (“DCM”) operation |
| US8288954B2 (en) * | 2008-12-07 | 2012-10-16 | Cirrus Logic, Inc. | Primary-side based control of secondary-side current for a transformer |
| US8362707B2 (en) * | 2008-12-12 | 2013-01-29 | Cirrus Logic, Inc. | Light emitting diode based lighting system with time division ambient light feedback response |
| US8299722B2 (en) | 2008-12-12 | 2012-10-30 | Cirrus Logic, Inc. | Time division light output sensing and brightness adjustment for different spectra of light emitting diodes |
| US7994863B2 (en) * | 2008-12-31 | 2011-08-09 | Cirrus Logic, Inc. | Electronic system having common mode voltage range enhancement |
| US7859333B2 (en) * | 2009-02-03 | 2010-12-28 | Triquint Semiconductor, Inc. | Power amplifier with reconfigurable direct current coupling |
| US8482223B2 (en) * | 2009-04-30 | 2013-07-09 | Cirrus Logic, Inc. | Calibration of lamps |
| US8198874B2 (en) | 2009-06-30 | 2012-06-12 | Cirrus Logic, Inc. | Switching power converter with current sensing transformer auxiliary power supply |
| US8248145B2 (en) | 2009-06-30 | 2012-08-21 | Cirrus Logic, Inc. | Cascode configured switching using at least one low breakdown voltage internal, integrated circuit switch to control at least one high breakdown voltage external switch |
| US8963535B1 (en) | 2009-06-30 | 2015-02-24 | Cirrus Logic, Inc. | Switch controlled current sensing using a hall effect sensor |
| US8212493B2 (en) | 2009-06-30 | 2012-07-03 | Cirrus Logic, Inc. | Low energy transfer mode for auxiliary power supply operation in a cascaded switching power converter |
| US9155174B2 (en) * | 2009-09-30 | 2015-10-06 | Cirrus Logic, Inc. | Phase control dimming compatible lighting systems |
| US8654483B2 (en) | 2009-11-09 | 2014-02-18 | Cirrus Logic, Inc. | Power system having voltage-based monitoring for over current protection |
| US8183921B1 (en) | 2010-11-24 | 2012-05-22 | Altera Corporation | Offset cancellation for continuous-time circuits |
| US8957801B2 (en) * | 2012-06-11 | 2015-02-17 | Dan Raphaeli | Method and system for flash type analog to digital converter |
| US9401687B2 (en) | 2013-04-09 | 2016-07-26 | Honeywell International Inc. | Voice alarm amplifier |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3423689A (en) * | 1965-08-19 | 1969-01-21 | Hewlett Packard Co | Direct current amplifier |
| JPS5325481Y2 (en) * | 1972-09-21 | 1978-06-29 | ||
| US4454480A (en) * | 1981-07-15 | 1984-06-12 | Allfather Lars P | Amplifying with cascaded class B amplifiers |
| FR2555839B1 (en) * | 1983-11-25 | 1986-01-24 | Thomson Csf | BROADBAND AMPLIFIER-LIMITER DEVICE |
| US4559502A (en) * | 1984-04-19 | 1985-12-17 | Signetics Corporation | Multi-stage amplifier with capacitive nesting for frequency compensation |
| US4717889A (en) * | 1986-09-02 | 1988-01-05 | Electro-Voice, Incorporated | Power control system for periodically and selectively energizing or shorting primary windings of transformers for controlling the output voltage across a common secondary winding |
| US4973919A (en) * | 1989-03-23 | 1990-11-27 | Doble Engineering Company | Amplifying with directly coupled, cascaded amplifiers |
-
1989
- 1989-03-23 US US07/328,051 patent/US4973919A/en not_active Expired - Lifetime
-
1990
- 1990-09-07 CA CA002024850A patent/CA2024850C/en not_active Expired - Fee Related
- 1990-09-10 AU AU62326/90A patent/AU629685B2/en not_active Ceased
- 1990-09-11 EP EP90309945A patent/EP0474930B1/en not_active Expired - Lifetime
- 1990-09-11 DE DE69025324T patent/DE69025324T2/en not_active Expired - Fee Related
- 1990-09-11 ES ES90309945T patent/ES2085896T3/en not_active Expired - Lifetime
- 1990-09-11 AT AT90309945T patent/ATE134088T1/en active
- 1990-09-11 DK DK90309945.5T patent/DK0474930T3/en active
-
1996
- 1996-03-19 GR GR960400757T patent/GR3019358T3/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| DE69025324D1 (en) | 1996-03-21 |
| ATE134088T1 (en) | 1996-02-15 |
| AU629685B2 (en) | 1992-10-08 |
| DE69025324T2 (en) | 1996-06-20 |
| DK0474930T3 (en) | 1996-06-17 |
| EP0474930B1 (en) | 1996-02-07 |
| CA2024850A1 (en) | 1992-03-08 |
| AU6232690A (en) | 1992-06-04 |
| EP0474930A1 (en) | 1992-03-18 |
| ES2085896T3 (en) | 1996-06-16 |
| GR3019358T3 (en) | 1996-06-30 |
| US4973919A (en) | 1990-11-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |