CA2006732A1 - Control system for fetching an instruction - Google Patents

Control system for fetching an instruction

Info

Publication number
CA2006732A1
CA2006732A1 CA2006732A CA2006732A CA2006732A1 CA 2006732 A1 CA2006732 A1 CA 2006732A1 CA 2006732 A CA2006732 A CA 2006732A CA 2006732 A CA2006732 A CA 2006732A CA 2006732 A1 CA2006732 A1 CA 2006732A1
Authority
CA
Canada
Prior art keywords
branch
instruction
judgement
control system
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2006732A
Other languages
French (fr)
Other versions
CA2006732C (en
Inventor
Tsuyoshi Mori
Seishi Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Tsuyoshi Mori
Seishi Okada
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsuyoshi Mori, Seishi Okada, Fujitsu Limited filed Critical Tsuyoshi Mori
Publication of CA2006732A1 publication Critical patent/CA2006732A1/en
Application granted granted Critical
Publication of CA2006732C publication Critical patent/CA2006732C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables

Abstract

Abstract for the Disclosure An instruction fetch control system prefetches a branch instruction in a pipeline system and fetches a branch target instruction of the branch instruction.
The control system comprises a first branch judgement circuit for conducting a branch condition judgement in a stage prior to the branch judgement stage in which a second and original branch judgement of the branch instruction is conducted, and a circuit for starting a prefetch of instructions following said branch target instruction without waiting for the branch judgement stage where the first branch judgement circuit judges that the branch is successful.
CA002006732A 1988-12-27 1989-12-27 Control system for fetching an instruction Expired - Fee Related CA2006732C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP32776588 1988-12-27
JP63-327765 1988-12-27

Publications (2)

Publication Number Publication Date
CA2006732A1 true CA2006732A1 (en) 1990-06-27
CA2006732C CA2006732C (en) 1994-05-03

Family

ID=18202737

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002006732A Expired - Fee Related CA2006732C (en) 1988-12-27 1989-12-27 Control system for fetching an instruction

Country Status (6)

Country Link
US (1) US6631464B1 (en)
EP (1) EP0376258B1 (en)
KR (1) KR920006770B1 (en)
AU (1) AU620962B2 (en)
CA (1) CA2006732C (en)
DE (1) DE68928937T2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6119221A (en) * 1996-11-01 2000-09-12 Matsushita Electric Industrial Co., Ltd. Instruction prefetching apparatus and instruction prefetching method for processing in a processor
US6415356B1 (en) * 2000-01-14 2002-07-02 Sun Microsystems, Inc. Method and apparatus for using an assist processor to pre-fetch data values for a primary processor
US6681318B2 (en) * 2000-09-08 2004-01-20 Sun Microsystems, Inc. Method and apparatus for using an assist processor to prefetch instructions for a primary processor
TW586666U (en) * 2001-04-03 2004-05-01 Univ Nat Chiao Tung Microprocessor command reading structure
JP7131236B2 (en) 2018-09-20 2022-09-06 富士通株式会社 Arithmetic processing device and method of controlling arithmetic processing device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120640A (en) * 1976-04-02 1977-10-11 Toshiba Corp Micro program control system
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4373180A (en) * 1980-07-09 1983-02-08 Sperry Corporation Microprogrammed control system capable of pipelining even when executing a conditional branch instruction
JPS57150040A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Pipeline computer
US4435756A (en) * 1981-12-03 1984-03-06 Burroughs Corporation Branch predicting computer
JPS5958700A (en) * 1982-09-29 1984-04-04 Fujitsu Ltd Memory protection judge method
JPS60105050A (en) 1983-11-11 1985-06-10 Fujitsu Ltd Pipeline control system
JPS60107141A (en) * 1983-11-16 1985-06-12 Fujitsu Ltd Branch control system
CA1250667A (en) * 1985-04-15 1989-02-28 Larry D. Larsen Branch control in a three phase pipelined signal processor
JPH0789319B2 (en) * 1985-04-22 1995-09-27 株式会社日立製作所 Prior control device in data processing device
US4847755A (en) * 1985-10-31 1989-07-11 Mcc Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
US4853840A (en) * 1986-01-07 1989-08-01 Nec Corporation Instruction prefetching device including a circuit for checking prediction of a branch instruction before the instruction is executed
JP2723238B2 (en) * 1988-01-18 1998-03-09 株式会社東芝 Information processing device
JPH01271838A (en) * 1988-04-22 1989-10-30 Fujitsu Ltd Microprogram branching method
US4974155A (en) * 1988-08-15 1990-11-27 Evans & Sutherland Computer Corp. Variable delay branch system

Also Published As

Publication number Publication date
DE68928937D1 (en) 1999-04-08
EP0376258B1 (en) 1999-03-03
EP0376258A3 (en) 1992-07-15
KR920006770B1 (en) 1992-08-17
KR900010552A (en) 1990-07-07
AU4728489A (en) 1990-07-05
EP0376258A2 (en) 1990-07-04
CA2006732C (en) 1994-05-03
DE68928937T2 (en) 1999-07-01
AU620962B2 (en) 1992-02-27
US6631464B1 (en) 2003-10-07

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed