CA1331228C - Synchronous protocol data formatter - Google Patents
Synchronous protocol data formatterInfo
- Publication number
- CA1331228C CA1331228C CA000593851A CA593851A CA1331228C CA 1331228 C CA1331228 C CA 1331228C CA 000593851 A CA000593851 A CA 000593851A CA 593851 A CA593851 A CA 593851A CA 1331228 C CA1331228 C CA 1331228C
- Authority
- CA
- Canada
- Prior art keywords
- formatter
- time slots
- host computer
- synchronous
- messages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0435—Details
- H04Q11/0464—Primary rate access circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1623—Plesiochronous digital hierarchy [PDH]
- H04J3/1647—Subrate or multislot multiplexing
Abstract
Abstract A synchronous protocol data formatter handles all 24-32 channels of a so-called primary rate version of a digital multiplexed interface or ISDN Primary Rate Interface for a communication system. The formatter relieves the host computer of the local area network of some highly specialized tasks, and, at thesame time, provides the following augmented capabilities, which exceed those required by the C.C.I.T.T. standard, I431:
1. dynamic channel bandwidth alloction can assign arbitrary (even non-adjacent) time slots to create a super channel;
2. a circular interrupt-queue in a shared memory enables the formatter and the host computer of the local area network to interact efficiently in updating and responding to changing conditions; and 3. cyclical redundancy codes can be used on a more flexible basis than heretofore, e.g., can be generated upon only address and control fields fordigitized voice signals, or, in a relay mode, can substitute an existing cyclical redundancy code to guard against memory errors.
1. dynamic channel bandwidth alloction can assign arbitrary (even non-adjacent) time slots to create a super channel;
2. a circular interrupt-queue in a shared memory enables the formatter and the host computer of the local area network to interact efficiently in updating and responding to changing conditions; and 3. cyclical redundancy codes can be used on a more flexible basis than heretofore, e.g., can be generated upon only address and control fields fordigitized voice signals, or, in a relay mode, can substitute an existing cyclical redundancy code to guard against memory errors.
Description
r.~
SYNCEIRONOUS PROTOCOL DATA FORMATI~R
eld of the Invention This inven~ion relates to synchronous protocol data formatter used in digital multiplexed interfaces, particularly the relatively high-frequency type called a primary rate interface, for an integrated services digital network (ISDN).
S Back~round of the Invention In the recent rapid development of digital communication services, the general concept of an integrated services digital network has steadily gained ground. In other words, all contemplated services would be provided through the same digital network.
International Standards Organizations have moved quickly to foster this development. They have adapted standards for a line rate of 1.544 Mbits/s (primarily in North America and Japan) and 2.048 Mbits/s (most of the world) fora primary rate digital multiplexed interface.
While some commercial products exist for these purposes, each of 15 them has drawbacks.
For example, some of them serve such a small number of channels `
the equipment costs and coordination problems quickly escalate. Others are insufficiently flexible to assure the customer of a communication link of the desired capacity whenever possible.
It is an object of this invention to solve the foregoing problems. -Summanr of the Invention In accordance with one aspect of the invention there is provided a synchronous formatter for a data net vork interface of the type having means forallocating communication channel bandwidth to one or more applied messages 25 through the allocation of time slots and means for performing protocol functions for the Integrated Service Digital Network (ISDN) Primary Rate Standard, characterized in that the means for allocating channel bandwidth includes means for allocating a plurality of time slots to each of said one or more messages without regard to adjacency of said plurality of time slots for use repetitively to 3~ CGmmuniCate a message.
, ;
- . ... ~
~3~ 2~
-la-In accordance with another aspect of the invention there is provided in combination, a host computer, a memory and a synchronous formatter for a data network interface of the type having means for allocating communication bandwidth through the allocation of time slots and means for performing protocolS functions, characterized in that the means for performing protocol functions includes means for sharing said memory without conflict with said host computer,means for establishing a circular queue of items for the attention of the host computer, and means for issuing an attention signal to the host computer after each access of the shared memory by the formatter, when the attention of the host computer is likely to be required.
In accordance with yet another aspect of the invention there is provided a method of controlling a synchronous formatter for a data network interface, said synchronous formatter being adapted to allocate communication channe1 bandwidth for one or more applied messages through allocation of time ' slots, comprising the steps of: for each applied message, determining a number of time slots needed in accordance with the bandwidth required for said applied message, identifying available time slots, and allocating said number of available time slots for repetitive use to communicate said applied message without regard to adjacency of said time slots.
According to our invention, the synchronous protocol data formatter is adapted so that it can handle all the channels of a primary rate digital multiplexed interface, or can dynamically allocate adjacent or non-adjacent 64 kbits rhannelS to create one or more "super channels".
According to another feature of our invention, the formatter includes a circular queue and "interrupt-queue" StNCture that facilitates the shared ; usage of a main memory by the formatter and by a host computer, or microprocessor, associated with the interface.
The interrupt-queue structure allows immediate access to the memory by the formatter, together with a notice pulse to the host computer, which still allows the host computer to continue some urgent priorities before accessing the memory itself.
.
~.:
~ ,, .:,: -.:.. . .. . .
"~
J _~ _,, r. .-- ~3 According to another feature of our invention, the error-checking cyclic redundancy code (CRC) is calculated only upon the address and control fields when it is known that voice signals are being transmitted.
According to sdll another feature of our invention, the fonnatter 5 prevents calculadon of additional CRC when it is in the relay mode (e.g., transrnission th~augh a repeater) and, instead, passes through the prior CRC forthe frame, to tend to guard against memory errors.
Brief Description of the Drawin~
Further features and advantages of the invention vill become apparent 10 from the following detailed descripdon, taken together with the drawings, in which:
FIG. 1 is a block diagrammatdc showing of the digital multiplexed interface applicadon environment, in which a synchronous protocol data formatter- according to our invention can be used;
E;IGs. 2 and 3 together are a block diagrammadc showing of a preferred embodiment of our invention;
FIC;s. ~6 illustrate the flexibility of the dynamic channel allocadon according to our invendon;
FIG~ 7 shows-the associadon of ~IGs. 2 and 3 20 Detailed Descrip~ioD
Ln FIG~ 1, a fo~matting digital multiplexed interface, which can be implemented according to our invendon, includes the transmit unit 11, the receive unit 12, and VO ~nterface 13. Transmit unit 11 and receive uni~ 12 are generically termed a ~ransceiver, providing necessary protocol, formatdng and related general - 25 functions in coupling the local input/output interface 13, which serves, for example, a local host computer 14, to the transmission line interface 15 to the public, s~ntched telephone network, or other information transport facility.
Befo~e tun~ing to the internal details of urlit 11, let us consider the ove~all funcdons, as they have developed in the prior arL In the ardcle "An Eight 30 Channel Synchr~nous Data Controller for a Primary Rate Interface to ISDN", byHa~Ty T. French, Conf. Proceedings ICCD, Rye, New York, Oct. 5, 1987, pp. 100 106, there is described an integrated circuit which is the irnmediate antecedent of the present invention.
With regard to the synchronous formatter there described, it is stated:
It relieves the hos~ processor from low level formatting functions and provides the fi~nctions needed, such as CRC generation and shecking, to provide link layer flow con~ol and error recovery . .
, , ,. , ..... . - : . .
.;;. - - -, , ~ ~ ~ - . . - - .
,, -. .. . . . .
,~: . , . :.
SYNCEIRONOUS PROTOCOL DATA FORMATI~R
eld of the Invention This inven~ion relates to synchronous protocol data formatter used in digital multiplexed interfaces, particularly the relatively high-frequency type called a primary rate interface, for an integrated services digital network (ISDN).
S Back~round of the Invention In the recent rapid development of digital communication services, the general concept of an integrated services digital network has steadily gained ground. In other words, all contemplated services would be provided through the same digital network.
International Standards Organizations have moved quickly to foster this development. They have adapted standards for a line rate of 1.544 Mbits/s (primarily in North America and Japan) and 2.048 Mbits/s (most of the world) fora primary rate digital multiplexed interface.
While some commercial products exist for these purposes, each of 15 them has drawbacks.
For example, some of them serve such a small number of channels `
the equipment costs and coordination problems quickly escalate. Others are insufficiently flexible to assure the customer of a communication link of the desired capacity whenever possible.
It is an object of this invention to solve the foregoing problems. -Summanr of the Invention In accordance with one aspect of the invention there is provided a synchronous formatter for a data net vork interface of the type having means forallocating communication channel bandwidth to one or more applied messages 25 through the allocation of time slots and means for performing protocol functions for the Integrated Service Digital Network (ISDN) Primary Rate Standard, characterized in that the means for allocating channel bandwidth includes means for allocating a plurality of time slots to each of said one or more messages without regard to adjacency of said plurality of time slots for use repetitively to 3~ CGmmuniCate a message.
, ;
- . ... ~
~3~ 2~
-la-In accordance with another aspect of the invention there is provided in combination, a host computer, a memory and a synchronous formatter for a data network interface of the type having means for allocating communication bandwidth through the allocation of time slots and means for performing protocolS functions, characterized in that the means for performing protocol functions includes means for sharing said memory without conflict with said host computer,means for establishing a circular queue of items for the attention of the host computer, and means for issuing an attention signal to the host computer after each access of the shared memory by the formatter, when the attention of the host computer is likely to be required.
In accordance with yet another aspect of the invention there is provided a method of controlling a synchronous formatter for a data network interface, said synchronous formatter being adapted to allocate communication channe1 bandwidth for one or more applied messages through allocation of time ' slots, comprising the steps of: for each applied message, determining a number of time slots needed in accordance with the bandwidth required for said applied message, identifying available time slots, and allocating said number of available time slots for repetitive use to communicate said applied message without regard to adjacency of said time slots.
According to our invention, the synchronous protocol data formatter is adapted so that it can handle all the channels of a primary rate digital multiplexed interface, or can dynamically allocate adjacent or non-adjacent 64 kbits rhannelS to create one or more "super channels".
According to another feature of our invention, the formatter includes a circular queue and "interrupt-queue" StNCture that facilitates the shared ; usage of a main memory by the formatter and by a host computer, or microprocessor, associated with the interface.
The interrupt-queue structure allows immediate access to the memory by the formatter, together with a notice pulse to the host computer, which still allows the host computer to continue some urgent priorities before accessing the memory itself.
.
~.:
~ ,, .:,: -.:.. . .. . .
"~
J _~ _,, r. .-- ~3 According to another feature of our invention, the error-checking cyclic redundancy code (CRC) is calculated only upon the address and control fields when it is known that voice signals are being transmitted.
According to sdll another feature of our invention, the fonnatter 5 prevents calculadon of additional CRC when it is in the relay mode (e.g., transrnission th~augh a repeater) and, instead, passes through the prior CRC forthe frame, to tend to guard against memory errors.
Brief Description of the Drawin~
Further features and advantages of the invention vill become apparent 10 from the following detailed descripdon, taken together with the drawings, in which:
FIG. 1 is a block diagrammatdc showing of the digital multiplexed interface applicadon environment, in which a synchronous protocol data formatter- according to our invention can be used;
E;IGs. 2 and 3 together are a block diagrammadc showing of a preferred embodiment of our invention;
FIC;s. ~6 illustrate the flexibility of the dynamic channel allocadon according to our invendon;
FIG~ 7 shows-the associadon of ~IGs. 2 and 3 20 Detailed Descrip~ioD
Ln FIG~ 1, a fo~matting digital multiplexed interface, which can be implemented according to our invendon, includes the transmit unit 11, the receive unit 12, and VO ~nterface 13. Transmit unit 11 and receive uni~ 12 are generically termed a ~ransceiver, providing necessary protocol, formatdng and related general - 25 functions in coupling the local input/output interface 13, which serves, for example, a local host computer 14, to the transmission line interface 15 to the public, s~ntched telephone network, or other information transport facility.
Befo~e tun~ing to the internal details of urlit 11, let us consider the ove~all funcdons, as they have developed in the prior arL In the ardcle "An Eight 30 Channel Synchr~nous Data Controller for a Primary Rate Interface to ISDN", byHa~Ty T. French, Conf. Proceedings ICCD, Rye, New York, Oct. 5, 1987, pp. 100 106, there is described an integrated circuit which is the irnmediate antecedent of the present invention.
With regard to the synchronous formatter there described, it is stated:
It relieves the hos~ processor from low level formatting functions and provides the fi~nctions needed, such as CRC generation and shecking, to provide link layer flow con~ol and error recovery . .
, , ,. , ..... . - : . .
.;;. - - -, , ~ ~ ~ - . . - - .
,, -. .. . . . .
,~: . , . :.
3?
[It3 would see applicadons in front end processors, host computers, cluster controllers and high-end worlcstadons.
Nevertheless, it has become desirable to reduce ~he required duplication of such eight (8)-channel circuits for 24-channel Notth American 5 standard applications or 32-channel European (C.E.P.T.) standard applications as sdopted by (C~C.I.T.T.3.
Viewed as a front end processor for the host computer, the invention provides a single integtated circuit which gleatly reduces the software needs and computing butden for the host computer.
Returning to ~;IG. 1, we see Ihat transmit uni~ 11 includes the transmit setial inputloutput unit 16, the high-level data-link control (HDLC) unit 17, and a random access memory 18, which enables one synchronous formattet to keep trac~c of all 32 independent channels.
In the prefetred embodirnent of FIGs. 2 and 3, which fit toge~her as 15 shown in E;IG. 7, there are shown in block diagr~Datic form the elements thatenable the dynarnic channel allocadon and the interrupt-queue structure, and other features, of the present invention.
- Clock signals are generated in clock generator 21, ~esponsive both to an external clock (CLK) and the various signals coming from the interface 15; and 20 everything in units 11, 12 and 13 runs synchronously with the signal from the- clock generator 21.
Data flows between interfaces 13 and 11 on the 40 bit data bus 22, but the vasious intemal control signals flow within unit 11 on the control bus 23.
When host computer 14 places a command in shared memory 20, then - 25 sends a pulse on the SA lead to IIO interface 13, together indicating that a super channel of g~eater capacity than the 64k bit/s of a B (Bearer-general voice or data) or D (Data or Signaling channel) is needed, the synclhonous forrnatter responds to the SA signal by reading the new info~nation in the shar~d memory 20, which desig~ates a sufficien~ number of channels, and then proceeds to put together a 30 channel of sufficient overall bandwidth.
Logical channel number circuit 28 plays an essendal role in this process by mapping the locations of the timeslo~s into channe1s and super channels.
The intelsupt-queue s~ructure of the present invention is implemented 3S as follows:
. ~,;. ~. .
. .. , ",. . ~ . .
., . . , ~ . - . - . .. ..
, .,,. ,., ,.., ,.,, ~ :, :
.~. :; . - . - . . -$
[It3 would see applicadons in front end processors, host computers, cluster controllers and high-end worlcstadons.
Nevertheless, it has become desirable to reduce ~he required duplication of such eight (8)-channel circuits for 24-channel Notth American 5 standard applications or 32-channel European (C.E.P.T.) standard applications as sdopted by (C~C.I.T.T.3.
Viewed as a front end processor for the host computer, the invention provides a single integtated circuit which gleatly reduces the software needs and computing butden for the host computer.
Returning to ~;IG. 1, we see Ihat transmit uni~ 11 includes the transmit setial inputloutput unit 16, the high-level data-link control (HDLC) unit 17, and a random access memory 18, which enables one synchronous formattet to keep trac~c of all 32 independent channels.
In the prefetred embodirnent of FIGs. 2 and 3, which fit toge~her as 15 shown in E;IG. 7, there are shown in block diagr~Datic form the elements thatenable the dynarnic channel allocadon and the interrupt-queue structure, and other features, of the present invention.
- Clock signals are generated in clock generator 21, ~esponsive both to an external clock (CLK) and the various signals coming from the interface 15; and 20 everything in units 11, 12 and 13 runs synchronously with the signal from the- clock generator 21.
Data flows between interfaces 13 and 11 on the 40 bit data bus 22, but the vasious intemal control signals flow within unit 11 on the control bus 23.
When host computer 14 places a command in shared memory 20, then - 25 sends a pulse on the SA lead to IIO interface 13, together indicating that a super channel of g~eater capacity than the 64k bit/s of a B (Bearer-general voice or data) or D (Data or Signaling channel) is needed, the synclhonous forrnatter responds to the SA signal by reading the new info~nation in the shar~d memory 20, which desig~ates a sufficien~ number of channels, and then proceeds to put together a 30 channel of sufficient overall bandwidth.
Logical channel number circuit 28 plays an essendal role in this process by mapping the locations of the timeslo~s into channe1s and super channels.
The intelsupt-queue s~ructure of the present invention is implemented 3S as follows:
. ~,;. ~. .
. .. , ",. . ~ . .
., . . , ~ . - . - . .. ..
, .,,. ,., ,.., ,.,, ~ :, :
.~. :; . - . - . . -$
Ihe circular interrupt queue of up to 4096 words of 16 bits is set up in the shared memory 20. The queue is circular in that the last sequential position in the circular interrupt queue is sequentially linked to the first position, so shat interrupt-queue pointer 32 in control 13 moves smoothly from the last position to 5 the first.
The purpose of the interrupt queue is to store condidons (needing attendon) found in the data handled in the synchronous formatter in the unit 11 or 12, respecdvely. To this end, the forrnatter has irnmediase access to the sharedmemory. Simultaneously, it advances the queue pointer 3~ and sends an alert 10 signal to the host computer 14 (shown in FIG. 1) on the INT lead.
If the host computer has more urgent processing priorities, it will temporarily ignore the interrupts, but the formatter has set a bit in the interrupt queue which will later lead the host computer to find the corresponding address in - the intenupt queue, and proceed to do the appropriate processing, rec~rd u~
lS dating; etc. The entries in the int~rrupt queue are dealt with strictly sequendally.
The interloclc mechanism we currently use is via the set~ng and clearing of a flag bit within each word in the circular interrupt queue. The formatter sets this bit when an interrupt condition is generated and advances the interrupt Q pointer held in the interface unit 13. The host after reading the circular interrupt queue clears 20 this flag bit and advances its own interrupt Q pointer. In this way the host is always chasing the formatter around the circular queue. No problem can develop as long as the formatter pointer doesn't lap the host pointer.
The cyclical redundancy code (CRC) control 34 differ3 fiom the prior - art in the flexibility with which the code can be calculated on the complete 25 transmiued frame, or only upon the address and control Selds in the case tha voice signal data is c~eDdy being transmitted, or not at all in the relay mode.
If the device is programmed for voice signal p~cessing then, in the receiver 12, the CRC register contents is fi~zen after some numbe~ of header bytes are received. As additional data is received a comparison is done between 30 the frozen CRC and the newly receiYed data When a closing flag delimiter (0 1I 1 1 1 1 O) is received the frozen CRC register contents will be equal to the previous two bytes (befo~e flag) if there are no errors in tlle frame. The received CRC is always w~itten to the shared memory 20 by the interface unit 13.
In the transmitter 11 the CRC register contents is frozen after some 35 number of header bytes are transmit~ed. The frozen CRC is held until Ihe end of the f~ame when it is transmitted prior to the closing flag delimiter.
.
, , In the event that unit 11 is in a frame relay application, memory access e~?rors may be a principal source of error in the data. In that event, no new CR.C is generated; and the prior value is passed directly from the shared memory20 to the transmit unit 11 via the interface unit 13. The transmit CRC SR (part of 5 34~ register is not used in this mode.
For the purpose of diagnostic tesdng, a corrupted CRC' may be passed from the shared memory 20 to the transmit unit 11 via the interface unit 13. In other words, the system forces a CRC error in the test mode. This simulates a line e~ror and can be used to check the recei~ing end circuitry.
From Fl&. 4, the Ielationship of our new dynanuc channel allocation to the recently established International standards may be understood. The firstline illustrates all 24 channels of the North American standard, of which the last (here, designated "23") must be the particular sort of data which comprlses - channel signaling data The second line illustrates the four standard 384 kbps super channels.
In fact, lines 2 and 3 in PIG. 4 illustrate super channel assignments which are described in detail in the new standard CC.I.T.T. - recommendadons of the Series I, I. 431, Geneva, 1985, but which are as equally well implemented bythe circuitry of our invention to achieve the "mix and match" moae of the last 20 line.
On the last line of F~C;. 4 is illus~ated the mLxed regular channel-super channel allocations, according to our invention.
As a result o~ our invention, we sce that portions of channel #l may be separated in time by portions of channel #2 and vice-versa.
Two poi~ts should be observed. First, the host computer maps the timo slots (and the fQnnatter copies those choices into its MAP registcr 36) so that busy channels or dmo slots are not interferred with. Second, thc mapping never allocates channel 23, or any other time slot or channel reserved ~or special funcdons, such as signalling, into a dynamic channd allocation according to our 30 invendon.
A~ the end of each 64kbitls time slot, the formatter does a context switch, stonng partial informadon for that timeslot's channel in the internal RAM
-~ ~ 18, and rstrieves partial informadon for the next timeslot's channeL This ar~hitechlre allows this ve~y flexible channd allocation feature.
~r,.i" ~
The purpose of the interrupt queue is to store condidons (needing attendon) found in the data handled in the synchronous formatter in the unit 11 or 12, respecdvely. To this end, the forrnatter has irnmediase access to the sharedmemory. Simultaneously, it advances the queue pointer 3~ and sends an alert 10 signal to the host computer 14 (shown in FIG. 1) on the INT lead.
If the host computer has more urgent processing priorities, it will temporarily ignore the interrupts, but the formatter has set a bit in the interrupt queue which will later lead the host computer to find the corresponding address in - the intenupt queue, and proceed to do the appropriate processing, rec~rd u~
lS dating; etc. The entries in the int~rrupt queue are dealt with strictly sequendally.
The interloclc mechanism we currently use is via the set~ng and clearing of a flag bit within each word in the circular interrupt queue. The formatter sets this bit when an interrupt condition is generated and advances the interrupt Q pointer held in the interface unit 13. The host after reading the circular interrupt queue clears 20 this flag bit and advances its own interrupt Q pointer. In this way the host is always chasing the formatter around the circular queue. No problem can develop as long as the formatter pointer doesn't lap the host pointer.
The cyclical redundancy code (CRC) control 34 differ3 fiom the prior - art in the flexibility with which the code can be calculated on the complete 25 transmiued frame, or only upon the address and control Selds in the case tha voice signal data is c~eDdy being transmitted, or not at all in the relay mode.
If the device is programmed for voice signal p~cessing then, in the receiver 12, the CRC register contents is fi~zen after some numbe~ of header bytes are received. As additional data is received a comparison is done between 30 the frozen CRC and the newly receiYed data When a closing flag delimiter (0 1I 1 1 1 1 O) is received the frozen CRC register contents will be equal to the previous two bytes (befo~e flag) if there are no errors in tlle frame. The received CRC is always w~itten to the shared memory 20 by the interface unit 13.
In the transmitter 11 the CRC register contents is frozen after some 35 number of header bytes are transmit~ed. The frozen CRC is held until Ihe end of the f~ame when it is transmitted prior to the closing flag delimiter.
.
, , In the event that unit 11 is in a frame relay application, memory access e~?rors may be a principal source of error in the data. In that event, no new CR.C is generated; and the prior value is passed directly from the shared memory20 to the transmit unit 11 via the interface unit 13. The transmit CRC SR (part of 5 34~ register is not used in this mode.
For the purpose of diagnostic tesdng, a corrupted CRC' may be passed from the shared memory 20 to the transmit unit 11 via the interface unit 13. In other words, the system forces a CRC error in the test mode. This simulates a line e~ror and can be used to check the recei~ing end circuitry.
From Fl&. 4, the Ielationship of our new dynanuc channel allocation to the recently established International standards may be understood. The firstline illustrates all 24 channels of the North American standard, of which the last (here, designated "23") must be the particular sort of data which comprlses - channel signaling data The second line illustrates the four standard 384 kbps super channels.
In fact, lines 2 and 3 in PIG. 4 illustrate super channel assignments which are described in detail in the new standard CC.I.T.T. - recommendadons of the Series I, I. 431, Geneva, 1985, but which are as equally well implemented bythe circuitry of our invention to achieve the "mix and match" moae of the last 20 line.
On the last line of F~C;. 4 is illus~ated the mLxed regular channel-super channel allocations, according to our invention.
As a result o~ our invention, we sce that portions of channel #l may be separated in time by portions of channel #2 and vice-versa.
Two poi~ts should be observed. First, the host computer maps the timo slots (and the fQnnatter copies those choices into its MAP registcr 36) so that busy channels or dmo slots are not interferred with. Second, thc mapping never allocates channel 23, or any other time slot or channel reserved ~or special funcdons, such as signalling, into a dynamic channd allocation according to our 30 invendon.
A~ the end of each 64kbitls time slot, the formatter does a context switch, stonng partial informadon for that timeslot's channel in the internal RAM
-~ ~ 18, and rstrieves partial informadon for the next timeslot's channeL This ar~hitechlre allows this ve~y flexible channd allocation feature.
~r,.i" ~
- 6 - L ~
In other respects, the preferred embodiment operates in ways ~enerally known and understood by workers of ordinary skill in the art.
For example, see the above-cited ar~cle by French et al.
Other possible standard super channel assignments are set out in the table of ~IG. S and are believed to be self-explanatory.
FIG. 6 shows a flow diagram, which states in words and in somewhat greater detail, the procedure followed (primarily by the host computeT 14) in the dynarnic channel allocation.
The "load cross-reference" step therein means that uhe host idendfies 10 which dmeslots should be assigned to which channels and builds a cross-reference table containing the new assignments in the shared memory.
The "attendon map" referred to is cs)pied by the formatter from shared memory into the register 36 and idendfies to the formatter which of the cross reference assignments of unit 28 in FIG. 2 have changed.
The "formatter attendon register" idendfies what type of reconfiguradon the formatter is to undergo (i.e., reallocation, commands, new inte~upt queue). The host computer writes all of the informadon described in thesecond through four the blocks of ~IG. 6 into the shaIed memory 20. The host dten pulses the SA pin (refer to FIG. 1) to accomplish the step of the fifth block 20 in PIG. 6. Subsequently, the formatter reads the shared memory, updating the SA
register 29 in the formatter and stardng the reconfiguration process.
The foregoing descripdon will suggest to the reader many possible vanatdons within the scopc of the invendon. -' i: ;
' ~ , ; ~ .
,: ' , ~.-. ; .,
In other respects, the preferred embodiment operates in ways ~enerally known and understood by workers of ordinary skill in the art.
For example, see the above-cited ar~cle by French et al.
Other possible standard super channel assignments are set out in the table of ~IG. S and are believed to be self-explanatory.
FIG. 6 shows a flow diagram, which states in words and in somewhat greater detail, the procedure followed (primarily by the host computeT 14) in the dynarnic channel allocation.
The "load cross-reference" step therein means that uhe host idendfies 10 which dmeslots should be assigned to which channels and builds a cross-reference table containing the new assignments in the shared memory.
The "attendon map" referred to is cs)pied by the formatter from shared memory into the register 36 and idendfies to the formatter which of the cross reference assignments of unit 28 in FIG. 2 have changed.
The "formatter attendon register" idendfies what type of reconfiguradon the formatter is to undergo (i.e., reallocation, commands, new inte~upt queue). The host computer writes all of the informadon described in thesecond through four the blocks of ~IG. 6 into the shaIed memory 20. The host dten pulses the SA pin (refer to FIG. 1) to accomplish the step of the fifth block 20 in PIG. 6. Subsequently, the formatter reads the shared memory, updating the SA
register 29 in the formatter and stardng the reconfiguration process.
The foregoing descripdon will suggest to the reader many possible vanatdons within the scopc of the invendon. -' i: ;
' ~ , ; ~ .
,: ' , ~.-. ; .,
Claims (5)
1. A synchronous formatter for a data network interface of the type having means for allocating communication channel bandwidth to one or more applied messages through the allocation of time slots and means for performing protocol functions for the Integrated Service Digital Network (ISDN) Primary Rate Standard, characterized in that the means for allocating channel bandwidth includes means for allocating a plurality of time slots to each of said one or more messages without regard to adjacency of said plurality of time slots for use repetitively to communicate a message.
2. A synchronous formatter for a data network interface of the type having means for allocating communication bandwidth to one or more applied messages through the allocation of time slots and means for performing protocol functions, characterized in that the means for performing protocol functions includes means for calculating cyclical redundancy codes based on the content of said messages, said means for calculating comprising means for calculating said codes based on less than the entire content of said messages.
3. A synchronous formatter of the type claimed in claim 2, further characterized in that the means for calculating includes means for excluding any voice signal content of said messages in calculating said cyclical redundancy codes.
4. A synchronous formatter for a data network interface of the type having means for allocating communication bandwidth through the allocation of time slots and means for performing cyclical redundancy code checking on received data, further characterized by means for suppressing cyclical redundancy code checking and for transmitting the received cyclical redundancy code as received.
5. In combination, a host computer, a memory and a synchronous formatter for a data network interface of the type having means for allocating communication bandwidth through the allocation of time slots and means for performing protocol functions, characterized in that the means for performing protocol functions includes means for sharing said memory without conflict with said host computer, means for establishing a circular queue of items for the attention of the host computer, and means for issuing an attention signal to the host computer after each access of the shared memory by the formatter, when the attention of the host computer is likely to be required. 6. A synchronous formatter of the type claimed in claim 5, further characterized by means in said formatter including means for directing said host computer to an item requiring attention when said host computer failed to respond to a prior attention signal temporarily; and means for constraining the host computer to access items in the queue in the order in which they were entered there.
7. A method of controlling a synchronous formatter for a data network interface, said synchronous formatter being adapted to allocate communication channel bandwidth for one or more applied messages through allocation of time slots, comprising the steps of:
for each applied message, determining a number of time slots needed in accordance with the bandwidth required for said applied message, identifying available time slots, and allocating said number of available time slots for repetitive use to communicate said applied message without regard to adjacency of said time slots.8. The method of claim 7 adapted for a frame relay application in which the data in at least one of said applied messages is transmitted as a sequence of frames and wherein said determining step further comprises:
determining the number of time slots needed for said message in accordance with the length of said frames.
7. A method of controlling a synchronous formatter for a data network interface, said synchronous formatter being adapted to allocate communication channel bandwidth for one or more applied messages through allocation of time slots, comprising the steps of:
for each applied message, determining a number of time slots needed in accordance with the bandwidth required for said applied message, identifying available time slots, and allocating said number of available time slots for repetitive use to communicate said applied message without regard to adjacency of said time slots.8. The method of claim 7 adapted for a frame relay application in which the data in at least one of said applied messages is transmitted as a sequence of frames and wherein said determining step further comprises:
determining the number of time slots needed for said message in accordance with the length of said frames.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US169,687 | 1980-07-17 | ||
| US07/169,687 US5029163A (en) | 1988-03-18 | 1988-03-18 | Synchronous protocol data formatter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1331228C true CA1331228C (en) | 1994-08-02 |
Family
ID=22616756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000593851A Expired - Fee Related CA1331228C (en) | 1988-03-18 | 1989-03-15 | Synchronous protocol data formatter |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5029163A (en) |
| JP (2) | JPH01241935A (en) |
| CA (1) | CA1331228C (en) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5218680A (en) * | 1990-03-15 | 1993-06-08 | International Business Machines Corporation | Data link controller with autonomous in tandem pipeline circuit elements relative to network channels for transferring multitasking data in cyclically recurrent time slots |
| FR2669488B1 (en) * | 1990-11-15 | 1993-01-08 | Cit Alcatel | METHOD FOR TRANSMITTING CONTROL INFORMATION FOR ASYNCHRONOUS TIME MULTIPLEXED CELL TRANSMISSION LINK. |
| JPH06502973A (en) * | 1990-11-26 | 1994-03-31 | モトローラ・インコーポレイテッド | Paging method and device in communication system |
| US6847611B1 (en) | 1990-12-10 | 2005-01-25 | At&T Corp. | Traffic management for frame relay switched data service |
| JP2968593B2 (en) * | 1991-01-08 | 1999-10-25 | 株式会社東芝 | Header conversion table and preprocessor |
| US5390353A (en) * | 1991-05-23 | 1995-02-14 | Eastman Kodak Company | Hardware implemental field oriented bit stream formatter for generating user programmed data formats |
| US5421030A (en) * | 1991-09-17 | 1995-05-30 | Com21, Inc. | Communications system and method for bi-directional communications between an upstream control facility and downstream user terminals |
| WO1994009595A1 (en) * | 1991-09-20 | 1994-04-28 | Shaw Venson M | Method and apparatus including system architecture for multimedia communications |
| JPH0591081A (en) * | 1991-09-27 | 1993-04-09 | Fujitsu Ltd | Method and device for transfer control in exchange |
| US5566301A (en) * | 1992-02-11 | 1996-10-15 | Futuretel, Inc. | ISDN audiovisual teleservices interface subsystem |
| AU682815B2 (en) * | 1992-02-11 | 1997-10-23 | Mark C. Koz | An ISDN audiovisual teleservices interface subsystem |
| US5579379A (en) * | 1992-03-05 | 1996-11-26 | Bell Atlantic Network Services, Inc. | Personal communications service having a calling party pays capability |
| US5353331A (en) * | 1992-03-05 | 1994-10-04 | Bell Atlantic Network Services, Inc. | Personal communications service using wireline/wireless integration |
| AU4245493A (en) * | 1992-05-15 | 1993-12-13 | Connective Strategies, Inc. | Isdn-based high speed communication system |
| US5341415A (en) * | 1992-09-22 | 1994-08-23 | Paul Baran | Method and apparatus for sharing of common in-house wiring to permit multiple telephone carriers to serve the same customer |
| WO1994008414A1 (en) * | 1992-09-29 | 1994-04-14 | Com 21, Inc. | Cell based wide area network alternative access telephone and data system |
| GB2286314B (en) * | 1992-10-16 | 1996-09-18 | Venson M Shaw | Method and apparatus including system architecture for multimedia communications |
| US5425027A (en) * | 1993-01-04 | 1995-06-13 | Com21, Inc. | Wide area fiber and TV cable fast packet cell network |
| US5325419A (en) * | 1993-01-04 | 1994-06-28 | Ameritech Corporation | Wireless digital personal communications system having voice/data/image two-way calling and intercell hand-off |
| DE69326935T2 (en) * | 1993-03-02 | 2000-05-18 | Ibm | Method and device for the transmission of a data stream with high bit repetition frequency via independent digital communication channels |
| JPH06274463A (en) * | 1993-03-19 | 1994-09-30 | Hitachi Ltd | Data communication system |
| US6771617B1 (en) | 1993-06-17 | 2004-08-03 | Gilat Satellite Networks, Ltd. | Frame relay protocol-based multiplex switching scheme for satellite mesh network |
| US5434850A (en) | 1993-06-17 | 1995-07-18 | Skydata Corporation | Frame relay protocol-based multiplex switching scheme for satellite |
| FI108100B (en) * | 1993-06-23 | 2001-11-15 | Nokia Networks Oy | Communication method and communication system in a cellular radio network |
| EP0696395B1 (en) * | 1994-02-25 | 2002-09-11 | Telefonaktiebolaget Lm Ericsson | Decentralized base station for reducing bandwidth requirements for communications to and from radio transmitter-receivers in a telecommunications network |
| US5659684A (en) * | 1995-02-03 | 1997-08-19 | Isdn Systems Corporation | Methods and apparatus for interconnecting personal computers (PCs) and local area networks (LANs) using packet protocols transmitted over a digital data service (DDS) |
| US6122297A (en) * | 1995-03-13 | 2000-09-19 | Telefonaktiebolaget Lm Ericsson | Arrangement and method relating to digital communication systems |
| SE504161C2 (en) * | 1995-03-13 | 1996-11-25 | Ericsson Telefon Ab L M | Device and method for digital communication systems |
| US5621787A (en) * | 1995-09-13 | 1997-04-15 | Bell Atlantic Network Services, Inc. | Prepaid cash card |
| US5668807A (en) * | 1995-11-30 | 1997-09-16 | Motorola, Inc. | Synchronization of transparent TDM superchannels |
| US6111870A (en) * | 1996-11-07 | 2000-08-29 | Interdigital Technology Corporation | Method and apparatus for compressing and transmitting high speed data |
| US6081524A (en) | 1997-07-03 | 2000-06-27 | At&T Corp. | Frame relay switched data service |
| US6167466A (en) * | 1997-07-09 | 2000-12-26 | Texas Instruments Incorporated | Multi-channel serial port with programmable features |
| JP2002522949A (en) * | 1998-07-31 | 2002-07-23 | シーメンス アクチエンゲゼルシヤフト | Circuit device and method for receiving and transmitting data |
| US6219656B1 (en) * | 1998-11-25 | 2001-04-17 | Schlumberger Resource Management Services, Inc. | Memory integrity for meters |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3001417C2 (en) * | 1980-01-16 | 1982-01-28 | Siemens AG, 1000 Berlin und 8000 München | Method for occupying time slots in a time division multiplex system with dynamic multiplexers |
| US4630261A (en) * | 1984-07-30 | 1986-12-16 | International Business Machines Corp. | Integrated buffer management and signaling technique |
| US4736371A (en) * | 1985-12-30 | 1988-04-05 | Nec Corporation | Satellite communications system with random multiple access and time slot reservation |
| JPS62281626A (en) * | 1986-05-30 | 1987-12-07 | Nippon Telegr & Teleph Corp <Ntt> | Digital data transmission system |
| US4641304A (en) * | 1986-06-06 | 1987-02-03 | Rca Corporation | Announced retransmission random access system |
-
1988
- 1988-03-18 US US07/169,687 patent/US5029163A/en not_active Expired - Lifetime
- 1988-05-09 JP JP63110628A patent/JPH01241935A/en active Pending
-
1989
- 1989-03-15 CA CA000593851A patent/CA1331228C/en not_active Expired - Fee Related
- 1989-03-17 JP JP1063973A patent/JPH0210931A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01241935A (en) | 1989-09-26 |
| JPH0210931A (en) | 1990-01-16 |
| US5029163A (en) | 1991-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1331228C (en) | Synchronous protocol data formatter | |
| US4408323A (en) | Processor facilities for integrated packet and voice switching | |
| US4539676A (en) | Bulk/interactive data switching system | |
| US4377859A (en) | Time slot interchanger and control processor apparatus for use in a telephone switching network | |
| US5546392A (en) | Communications bus and controller | |
| GB1288195A (en) | ||
| EP0430955B1 (en) | Communication system | |
| US6526068B2 (en) | Interface control of communication between a control processor and a digital signal processor | |
| US5027349A (en) | Embedded control technique for distributed control systems | |
| EP0158673B1 (en) | Plural communication channel protocol support systems | |
| US4811339A (en) | Non-coded information and companion data switching mechanism | |
| JPH0591081A (en) | Method and device for transfer control in exchange | |
| JPS5810021B2 (en) | Time division multiplex network system | |
| US4930103A (en) | Data transmission method in a digital transmission network and apparatus for implimenting same | |
| US4695997A (en) | Device for performing wrap tests on a multiplex link in a data communication system | |
| EP0183530A2 (en) | Subscriber line interface modem | |
| EP0325327B1 (en) | Method of asynchronous duplex data communication between two stations relating to specific services to be performed through a common communication channel, and stations for carrying out the method | |
| US5689535A (en) | Method and apparatus for processing multiple facility datalinks | |
| JPS592455A (en) | Time division multiplex transmitting system | |
| KR820002240B1 (en) | Multiport digital switching element | |
| SU1100613A1 (en) | Interface | |
| KR950035219A (en) | Gateway Implementation Method and System for Network Matching between Integrated Information Network and Local Area Network | |
| JPH01209841A (en) | Configuration method for communication control processor | |
| JPS61161050A (en) | Channel access method in line exchange type network | |
| JPS62171298A (en) | Layer 2 control system in isdn network |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |