CA1241767A - Arrangement for apportioning priority among co- operating computers - Google Patents
Arrangement for apportioning priority among co- operating computersInfo
- Publication number
- CA1241767A CA1241767A CA000497302A CA497302A CA1241767A CA 1241767 A CA1241767 A CA 1241767A CA 000497302 A CA000497302 A CA 000497302A CA 497302 A CA497302 A CA 497302A CA 1241767 A CA1241767 A CA 1241767A
- Authority
- CA
- Canada
- Prior art keywords
- priority
- bus
- logic circuit
- input
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/46—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using electromechanical counter-type accumulators
Abstract
ABSTRACT OF THE DISCLOSURE
A priority apportioning arrangement for computers that contain processors of two types connected to a common bus, namely a high-priority type which can determine its priority itself in relation to processors of a second low-priority type. The arrangement contains a first logic circuit which has its first input activated on a request for access from one of the low-priority units, its second input activated on a request for access from the high-priority unit, and its third activated during the whole time the bus is used, and has two outputs for assigning the bus a low-priority unit or the high-priority unit. A second logic circuit has two inputs, of which one senses that the high-priority unit desires access and the other senses that this access can take place with delay and two outputs, of which indicates to the first logic circuit that the access request from the high-priority unit is present, and the other indicates that the bus is occupied. When the input signal to the second logic circuit indicates that the assignment of the bus to the high-priority unit can take place with delay, the arrangement has time to assign the bus to a low-priority unit but the high-priority unit still has immediate access to the bus after termination of the task of the low-priority unit.
A priority apportioning arrangement for computers that contain processors of two types connected to a common bus, namely a high-priority type which can determine its priority itself in relation to processors of a second low-priority type. The arrangement contains a first logic circuit which has its first input activated on a request for access from one of the low-priority units, its second input activated on a request for access from the high-priority unit, and its third activated during the whole time the bus is used, and has two outputs for assigning the bus a low-priority unit or the high-priority unit. A second logic circuit has two inputs, of which one senses that the high-priority unit desires access and the other senses that this access can take place with delay and two outputs, of which indicates to the first logic circuit that the access request from the high-priority unit is present, and the other indicates that the bus is occupied. When the input signal to the second logic circuit indicates that the assignment of the bus to the high-priority unit can take place with delay, the arrangement has time to assign the bus to a low-priority unit but the high-priority unit still has immediate access to the bus after termination of the task of the low-priority unit.
Description
~2~7~
The invention relates to a priority apportioning arran(~e,llen-t for computers con-taining processors of two types, a high-priority type and a low-priori-ty type. The high-p~^iority processor can itself de-termine its priority in relation to processors of the low-priority type when a comlllon bus is used 7 SO as to allow -the use of the bus by the low-priority processors if -the high-priority processor does not have important tasks to carry out.
In a system having several processors using -the same bus, where none of the processors has priori-ty, dis-tribution on ihe bus can take place with 'che aid oF a logic circuit that obtains a signal from each oF tne prospective users and assigns the bus to them in a given order, with the lastest user coming last. None of the processors can be kept out longer than for a number o-F
accesses corresponding -to the number or processors minus one .
Apportioning becomes more complica-ted when a number of processors with low priori-cy and a processor with high priority work on the same bus. In known arrangements, such as -that described in Electronic Design, May 24th, 1978 extra time is necessary for assigning -the bus when -the high-priority processor needs it.
An object of the inven-tion is to shorten the waiting time and to give the high-priority processor -Full priority when it needs the bus, but to give access to the low-priority processors when the bus is not needed by -the high-priority processor. This is achieved in accordance wi-th the invention by blocking access to the bus For the low-priority units when the high-priority processor needs the bus, whereas when the high-priority unit does not need the bus imlnediately, the low-priority units are given access for a time in given proportion to the opera-ting -time ~LZ~6~
oF the high-priority uni-t.
Accordingly therefore the present invention pro-vides an arrangement for apportioning priority for computers containing processors of two types connected to a comrnon bus, namely a high-priority type which can deternline i-ts priority in relation to processors of a second low-priority type, comprising a first logic circuit having three inpu-ts, the -First input receiving a low-priority input signal signi-Fying a request for access from one of the low-priority pro-cessors, the second input receiving a high-priori-ty input sigtlal signifying a request for access from the high-priority processor, and the chird input receiving an occupied signal signifying that the bus is in use, said -first logic circuit having two outputs on which a low-priority output signal appears on the first output for assigning the bus to a low-priority unit if only -the First input has been activated, and on which on the second outpu-t there appears a signal for assigning to the bus the high-priority processor while the signal on the first output is inhibited, the second logic circuit having two outputs and two inputs, the first output feeding the high-priority input signal to the second input of the first logic circuit, and the second output feeding the occupied signal to the -third i 25 input o-F the first logic circuit, the first input o-F the second logic circuit on activation resulting in the appearance unconditionally o-f the high-priority input signal on the second input of the First logic circuit, the presence of said high-priority input signal on the second input of the firs-t logic circuit denoting that the high-priority processor desires access so that the assigning signal occurs on the second output o-f the first logic circuit, and the second input of the second logic circuit on activation resulting in the occurrence of the high-priority input signal with delay on the Firs-t output of -the second logic circuit so that a signal for assigning the bus to a ~2~7~7 low-priority processor has time to appear but the high-priority un-it stil-l has immediate access to the bus after termination of the work of the low-priority processor.
The invention will now be described in more detail, by way of example only, with reference to the accom-paying drawings, in which:-Figure 1 is a block diagram of a processor system with processors working over a common bus;
Figure 2 is a block diagram of a priority distri-bution arrangement in accordance with the invention; and Figure 3 is a time chart illustrating how the bus is assigned when the high-priority processor does not need the bus immediately.
In Figure 1 a processor 1 with high priority is connected via a bus 2 to a plurality, in all eight, of low-priority processors 3a-3h. A memory 4 is connected to the bus, and the processors have access to the memory via the bus. The problem occuring in this co-operation is that access for the high-priority processor must always be ensured, while the low-priority processors share the remain-ing access time. In accordance with the invention this is solved by the priority apportioning arrangement denoted by 5. The arrangerment is indicated as a separate uni-t, but may be divided such that certain parts are in the processors.
The signals with which these units comrnunicate with each other will be explained in de-tail in connection with Figure
The invention relates to a priority apportioning arran(~e,llen-t for computers con-taining processors of two types, a high-priority type and a low-priori-ty type. The high-p~^iority processor can itself de-termine its priority in relation to processors of the low-priority type when a comlllon bus is used 7 SO as to allow -the use of the bus by the low-priority processors if -the high-priority processor does not have important tasks to carry out.
In a system having several processors using -the same bus, where none of the processors has priori-ty, dis-tribution on ihe bus can take place with 'che aid oF a logic circuit that obtains a signal from each oF tne prospective users and assigns the bus to them in a given order, with the lastest user coming last. None of the processors can be kept out longer than for a number o-F
accesses corresponding -to the number or processors minus one .
Apportioning becomes more complica-ted when a number of processors with low priori-cy and a processor with high priority work on the same bus. In known arrangements, such as -that described in Electronic Design, May 24th, 1978 extra time is necessary for assigning -the bus when -the high-priority processor needs it.
An object of the inven-tion is to shorten the waiting time and to give the high-priority processor -Full priority when it needs the bus, but to give access to the low-priority processors when the bus is not needed by -the high-priority processor. This is achieved in accordance wi-th the invention by blocking access to the bus For the low-priority units when the high-priority processor needs the bus, whereas when the high-priority unit does not need the bus imlnediately, the low-priority units are given access for a time in given proportion to the opera-ting -time ~LZ~6~
oF the high-priority uni-t.
Accordingly therefore the present invention pro-vides an arrangement for apportioning priority for computers containing processors of two types connected to a comrnon bus, namely a high-priority type which can deternline i-ts priority in relation to processors of a second low-priority type, comprising a first logic circuit having three inpu-ts, the -First input receiving a low-priority input signal signi-Fying a request for access from one of the low-priority pro-cessors, the second input receiving a high-priori-ty input sigtlal signifying a request for access from the high-priority processor, and the chird input receiving an occupied signal signifying that the bus is in use, said -first logic circuit having two outputs on which a low-priority output signal appears on the first output for assigning the bus to a low-priority unit if only -the First input has been activated, and on which on the second outpu-t there appears a signal for assigning to the bus the high-priority processor while the signal on the first output is inhibited, the second logic circuit having two outputs and two inputs, the first output feeding the high-priority input signal to the second input of the first logic circuit, and the second output feeding the occupied signal to the -third i 25 input o-F the first logic circuit, the first input o-F the second logic circuit on activation resulting in the appearance unconditionally o-f the high-priority input signal on the second input of the First logic circuit, the presence of said high-priority input signal on the second input of the firs-t logic circuit denoting that the high-priority processor desires access so that the assigning signal occurs on the second output o-f the first logic circuit, and the second input of the second logic circuit on activation resulting in the occurrence of the high-priority input signal with delay on the Firs-t output of -the second logic circuit so that a signal for assigning the bus to a ~2~7~7 low-priority processor has time to appear but the high-priority un-it stil-l has immediate access to the bus after termination of the work of the low-priority processor.
The invention will now be described in more detail, by way of example only, with reference to the accom-paying drawings, in which:-Figure 1 is a block diagram of a processor system with processors working over a common bus;
Figure 2 is a block diagram of a priority distri-bution arrangement in accordance with the invention; and Figure 3 is a time chart illustrating how the bus is assigned when the high-priority processor does not need the bus immediately.
In Figure 1 a processor 1 with high priority is connected via a bus 2 to a plurality, in all eight, of low-priority processors 3a-3h. A memory 4 is connected to the bus, and the processors have access to the memory via the bus. The problem occuring in this co-operation is that access for the high-priority processor must always be ensured, while the low-priority processors share the remain-ing access time. In accordance with the invention this is solved by the priority apportioning arrangement denoted by 5. The arrangerment is indicated as a separate uni-t, but may be divided such that certain parts are in the processors.
The signals with which these units comrnunicate with each other will be explained in de-tail in connection with Figure
2. Tile-ir designatiorls are as follows:
BMA = bus master address. Selects one of the 8 low-priority processors.
- 2a -!L7~7 ,i EBG = external bus gran-t. Grants access to one Or the low- priority uni-ts.
MGB = intensive processor bus grant. Grants access -to the high-priority processor.
RQB = request bus. Request for bus access from the low-; priority units.
REB = reserve bus. Request for access to the bus from the high-priority processor.
BOC = bus occupied. The bus is engaged, work is in pro-gress.
i /
i ,, , 30 1, 35 i - 2b -~Z4~7Ç~7 Figure 2 illustrates the priority apportioning arrangement in the form o~ a block cliagram. The mutual apportioning of the blls between the low-priority pro-cessors takes place with the aid of a 1ogic circuit consisting of a PR0M m~ry 10 and a register 11. Each 1cw priori-ty processor 3a-3h, in all eight according to the5 exemplified embodiment, sends asigna1 R(~Bwitharequestforaccesstothe PROM memory l0, which contains a table. In the table there is given the address to that oF the low-priority processors which shall be activated next. The address is pointed out by a signal BMA which anables addressing eight different units via a 3-wire line. The fed-out address is registered in the register ll and 10 points out in the memory a new address which is to be used when the next low-priority processor sends an RQB signal. Of the low-priority units only the unit ~h is indieated in detail. A wait flip-flop denoted by 6 has its output activated when bus access is desired according to the programme, and an access flip-flop is denoted by 7, this flip-flop being activated when the processor has obtained 15 access, and is kept activated as long as this processor uses the bus. During this time the flip-flop sends the signal BOC denoting that the bus is engaged by the processor. The -flip-flop 7 is activated by a comparator 8 determining that the address BMA sent from the register ll agrees with the address o~ the processor itself and activates an input on an AND circuit 9, which obtains an EBG signal 20 on another input, denoting that the bus is available for the low-priority processors. Such an arrangement is already known.
If it is now desired to subdivide the access between the low-priority processorsand the high-priority processor such that the former will have access to the buscluring a time which is in a given proportion to the time during which the high-25 priority processor uses the bus, although permitting the high-priority processor to have immediate access to the bus at any time, an arrangement in accordance with the invention is then necessary. The arrangement includes a first logic circuit 20 controlling the assignment of the bus alternatively to the high-priority unlt or to a low-priority unit, and a second logic circuit 40, the output 30 signal of whieh indicates that the high-priority unit is in immediate need of the bus or that it can temporarily release the bus to a low-priority unit. Accordingto the exemplified embodiement, the first logie eircuit 20 is arranged outside the processors while the second logic eireuit 40 is in the high-priority proeessor.
However, where the logie circuits are situated has no importance from the 35 inventive aspect.
~2~
The First logic circuit 20 has three inputs, a first where a signal RQB occurs wherl one oF the low-priority units needs the bus, a second where a signal REB
occurs when the high-priority unit needs the bus and a third where a signal BOC
occurs denoting that the bus is engaged by one of the units. The siynals on the 5 first and the second inputs are taken to an AND circuit 21 wl)ich sends an output signal only iF the high-priority unit does not request access, and is blocked for the opposite case. This signal is fed to an input on an AND circuit 22 the negation input of which obtains the signal BOC. When the signal BOC
thus ceases in connection with the bus being disengaged and the signal REB does 10 not occur since the high-priority uni~ is not in immediate need oF the bus, an EBG signal is sent to enable access for one of the low-priority units. A furtherAND circuit 23 is arranged, which obtains the AND circuit 21 output signal on one side and the BOC signal on the other side. If both these signals cease, the signal MBG is generated, which assigns the bus to the high-priority unit and this 15 signal is fed to the second logic circuit 40.
A progr~rn selector denoted by 30 provides one of two alternative signals in response to the progr~mmne under execwtion. -r h e ~ i r s t t y p e o f s i 9 n a 1 f r o m t h e programme selector signifies that immediate bus access is desired by the high-priority unit, and the other signal signifies that immediate access is desired, but 20 low-priority units are also permitted to use the bus. A wait flip-flop denoted by 41 has its output activated immediately when the first type of signal is fed to its activating input S. The output signal blocks the circuit 21 so that access to the bus from the low-priority units is prevented, and when tlle (bus occupied) signal BOC ceases, the bus is once again assigned to the high-prlority unit by 25 the signal MGB. This is fed to one input of an AND circuit 39, the other input oF
which obtains the programme selector signal via an OR circuit 3~. lhe output signal of the AND circuit 39 activates an access flip-flop 42, which feeds a BOC signal via its output to the logic circuit 20 to ind;cate that the bus is occupied. IF the first type of signal remains from the programrne selector, the 30 output of the wait -Flip-Flop 41 is immediately activated so that the circuit 21 is kept blocked and no EBG signal is sent For giving access to the low-priority units. The other type of signal from the programme selector 30 signi-Fies that the high-priority unit can allow access for a low-priority unit. A flip--flop 43, which is activated by this signal, feeds a signal to the input of and AND circuit 35 46 in which a negation input is connected to the output oF the Flip-flop 42 so ~2~ 7`
that it is blocked the whole time the high-priority processor uses the bus. The output oF the AND circuit 46 is connected to an input oF the OR circuit ~7 which will send tlle output signal of the circuit ~6 to the AND s:ircuit 21. By activating the output signal of the circuit 46, and the generation of the REB
5 signal taking place with a given delay after the BOC signal has ceased, due tothe delay circuit 48, the REB signal does not occur until after the EBG signal has occurrecl at the output oF the circuit 22, so that one of the low-priority units will be given access. The REB signal occurs, immediately afterwards which ensures that the high-priority unit is given direct access when the "bus 10 occupied" signal BOC has ceased.
This is -further explained in the time chart according to Figure 3. When the high-priority unit is working and there is no immediate need to use the bus again, there is no standing REB signal from the flip-flop 41. When the "bus occupied" signal BOC ceases, the output of the circuit 46 is activated with a 15 time lag such that the REB signal does not occur until the EBG signal has hadtime to be sent to the low-priority processors. Immediately afterwards the circuit 21 is once again blocked by the REB signal, so that when the low-priority unit has completed its task and the BOC signal has ceased, the high-priority unit can take over the bus without delay4 By the E~OC signal ceasing, 20 the register 11 is activated and the identity of the low-priority unit can be sent out. With the aid of the described arrangement it will be possible to assign thebus to the low-priority units cluring such periods where the program does not make necessary immediate acces for the high-priority unit, aithough it is ~sured that the high-priority unit always has immediate access to the bus when 25 so required.
BMA = bus master address. Selects one of the 8 low-priority processors.
- 2a -!L7~7 ,i EBG = external bus gran-t. Grants access to one Or the low- priority uni-ts.
MGB = intensive processor bus grant. Grants access -to the high-priority processor.
RQB = request bus. Request for bus access from the low-; priority units.
REB = reserve bus. Request for access to the bus from the high-priority processor.
BOC = bus occupied. The bus is engaged, work is in pro-gress.
i /
i ,, , 30 1, 35 i - 2b -~Z4~7Ç~7 Figure 2 illustrates the priority apportioning arrangement in the form o~ a block cliagram. The mutual apportioning of the blls between the low-priority pro-cessors takes place with the aid of a 1ogic circuit consisting of a PR0M m~ry 10 and a register 11. Each 1cw priori-ty processor 3a-3h, in all eight according to the5 exemplified embodiment, sends asigna1 R(~Bwitharequestforaccesstothe PROM memory l0, which contains a table. In the table there is given the address to that oF the low-priority processors which shall be activated next. The address is pointed out by a signal BMA which anables addressing eight different units via a 3-wire line. The fed-out address is registered in the register ll and 10 points out in the memory a new address which is to be used when the next low-priority processor sends an RQB signal. Of the low-priority units only the unit ~h is indieated in detail. A wait flip-flop denoted by 6 has its output activated when bus access is desired according to the programme, and an access flip-flop is denoted by 7, this flip-flop being activated when the processor has obtained 15 access, and is kept activated as long as this processor uses the bus. During this time the flip-flop sends the signal BOC denoting that the bus is engaged by the processor. The -flip-flop 7 is activated by a comparator 8 determining that the address BMA sent from the register ll agrees with the address o~ the processor itself and activates an input on an AND circuit 9, which obtains an EBG signal 20 on another input, denoting that the bus is available for the low-priority processors. Such an arrangement is already known.
If it is now desired to subdivide the access between the low-priority processorsand the high-priority processor such that the former will have access to the buscluring a time which is in a given proportion to the time during which the high-25 priority processor uses the bus, although permitting the high-priority processor to have immediate access to the bus at any time, an arrangement in accordance with the invention is then necessary. The arrangement includes a first logic circuit 20 controlling the assignment of the bus alternatively to the high-priority unlt or to a low-priority unit, and a second logic circuit 40, the output 30 signal of whieh indicates that the high-priority unit is in immediate need of the bus or that it can temporarily release the bus to a low-priority unit. Accordingto the exemplified embodiement, the first logie eircuit 20 is arranged outside the processors while the second logic eireuit 40 is in the high-priority proeessor.
However, where the logie circuits are situated has no importance from the 35 inventive aspect.
~2~
The First logic circuit 20 has three inputs, a first where a signal RQB occurs wherl one oF the low-priority units needs the bus, a second where a signal REB
occurs when the high-priority unit needs the bus and a third where a signal BOC
occurs denoting that the bus is engaged by one of the units. The siynals on the 5 first and the second inputs are taken to an AND circuit 21 wl)ich sends an output signal only iF the high-priority unit does not request access, and is blocked for the opposite case. This signal is fed to an input on an AND circuit 22 the negation input of which obtains the signal BOC. When the signal BOC
thus ceases in connection with the bus being disengaged and the signal REB does 10 not occur since the high-priority uni~ is not in immediate need oF the bus, an EBG signal is sent to enable access for one of the low-priority units. A furtherAND circuit 23 is arranged, which obtains the AND circuit 21 output signal on one side and the BOC signal on the other side. If both these signals cease, the signal MBG is generated, which assigns the bus to the high-priority unit and this 15 signal is fed to the second logic circuit 40.
A progr~rn selector denoted by 30 provides one of two alternative signals in response to the progr~mmne under execwtion. -r h e ~ i r s t t y p e o f s i 9 n a 1 f r o m t h e programme selector signifies that immediate bus access is desired by the high-priority unit, and the other signal signifies that immediate access is desired, but 20 low-priority units are also permitted to use the bus. A wait flip-flop denoted by 41 has its output activated immediately when the first type of signal is fed to its activating input S. The output signal blocks the circuit 21 so that access to the bus from the low-priority units is prevented, and when tlle (bus occupied) signal BOC ceases, the bus is once again assigned to the high-prlority unit by 25 the signal MGB. This is fed to one input of an AND circuit 39, the other input oF
which obtains the programme selector signal via an OR circuit 3~. lhe output signal of the AND circuit 39 activates an access flip-flop 42, which feeds a BOC signal via its output to the logic circuit 20 to ind;cate that the bus is occupied. IF the first type of signal remains from the programrne selector, the 30 output of the wait -Flip-Flop 41 is immediately activated so that the circuit 21 is kept blocked and no EBG signal is sent For giving access to the low-priority units. The other type of signal from the programme selector 30 signi-Fies that the high-priority unit can allow access for a low-priority unit. A flip--flop 43, which is activated by this signal, feeds a signal to the input of and AND circuit 35 46 in which a negation input is connected to the output oF the Flip-flop 42 so ~2~ 7`
that it is blocked the whole time the high-priority processor uses the bus. The output oF the AND circuit 46 is connected to an input oF the OR circuit ~7 which will send tlle output signal of the circuit ~6 to the AND s:ircuit 21. By activating the output signal of the circuit 46, and the generation of the REB
5 signal taking place with a given delay after the BOC signal has ceased, due tothe delay circuit 48, the REB signal does not occur until after the EBG signal has occurrecl at the output oF the circuit 22, so that one of the low-priority units will be given access. The REB signal occurs, immediately afterwards which ensures that the high-priority unit is given direct access when the "bus 10 occupied" signal BOC has ceased.
This is -further explained in the time chart according to Figure 3. When the high-priority unit is working and there is no immediate need to use the bus again, there is no standing REB signal from the flip-flop 41. When the "bus occupied" signal BOC ceases, the output of the circuit 46 is activated with a 15 time lag such that the REB signal does not occur until the EBG signal has hadtime to be sent to the low-priority processors. Immediately afterwards the circuit 21 is once again blocked by the REB signal, so that when the low-priority unit has completed its task and the BOC signal has ceased, the high-priority unit can take over the bus without delay4 By the E~OC signal ceasing, 20 the register 11 is activated and the identity of the low-priority unit can be sent out. With the aid of the described arrangement it will be possible to assign thebus to the low-priority units cluring such periods where the program does not make necessary immediate acces for the high-priority unit, aithough it is ~sured that the high-priority unit always has immediate access to the bus when 25 so required.
Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An arrangement for apportioning priority for computers containing processors of two types connected to a common bus, namely a high-priority type which can determine its priority in relation to processors of a second low-priority type, comprising a first logic circuit having three inputs, the first input receiving a low-priority input signal signifying a request for access from one of the low-priority processors, the second input receiving a high-priority input signal signifying a request for access from the high-priority processor, and the third input receiving an occupied signal signifying that the bus is in use, said first logic circuit having two outputs on which a low-priority output signal appears on the first output for assigning the bus to a low-priority unit if only the first input has been activated, and on which on the second ouput there appears a signal for assigning to the bus the high-priority processor while the signal on the first output is inhibited, the second logic circuit having two outputs and two inputs, the first output feeding the high-priority input signal to the second input of the first logic circuit, and the second output feeding the occupied signal to the third input of the first logic circuit, the first input of the second logic circuit on activation resulting in the appearance unconditionally of the high-priority input signal on the second input of the first logic circuit, the presence of said high-priority input signal on the second input of the first logic circuit denoting that the high-priority processor desires access so that the assigning signal occurs on the second output of the first logic circuit, and the second input of the second logic circuit on activation resulting in the occurrence of the high-priority input sig-nal with delay on the first output of the second logic cir-cuit so that a signal for assigning the bus to a low-priority processor has time to appear but the high-priority unit still has immediate access to the bus after termination of the work of the low-priority processor.
2. An arrangement as claimed in claim 1, wherein the first logic circuit comprises a plurality of AND gates separate from the processor.
3. An arrangement as claimed in claim 2, wherein the second logic circuit is located in the high-priority processor.
4. An arrangement as claimed in claim 3 , wherein the first and second inputs of the second logic circuit are connected to the outputs of a program selector.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE8406312A SE445861B (en) | 1984-12-12 | 1984-12-12 | PRIORITY DISTRIBUTION DEVICE FOR COMPUTERS |
| SE8406312-2 | 1984-12-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1241767A true CA1241767A (en) | 1988-09-06 |
Family
ID=20358135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000497302A Expired CA1241767A (en) | 1984-12-12 | 1985-12-10 | Arrangement for apportioning priority among co- operating computers |
Country Status (23)
| Country | Link |
|---|---|
| US (1) | US4791563A (en) |
| EP (1) | EP0205472B1 (en) |
| JP (1) | JPH0630086B2 (en) |
| KR (1) | KR910003015B1 (en) |
| AT (1) | ATE45825T1 (en) |
| BR (1) | BR8507112A (en) |
| CA (1) | CA1241767A (en) |
| DE (1) | DE3572552D1 (en) |
| DK (1) | DK165077C (en) |
| EG (1) | EG17290A (en) |
| ES (1) | ES8702677A1 (en) |
| FI (1) | FI88549C (en) |
| GR (1) | GR852847B (en) |
| IE (1) | IE57050B1 (en) |
| IT (1) | IT1186409B (en) |
| MA (1) | MA20594A1 (en) |
| MX (1) | MX158467A (en) |
| NO (1) | NO170999C (en) |
| NZ (1) | NZ214010A (en) |
| PT (1) | PT81612B (en) |
| SE (1) | SE445861B (en) |
| TR (1) | TR22658A (en) |
| WO (1) | WO1986003606A1 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU595691B2 (en) * | 1987-03-26 | 1990-04-05 | Honeywell Bull Inc. | Tandem priority resolver |
| JP2635639B2 (en) * | 1987-12-28 | 1997-07-30 | 株式会社東芝 | Data processing device |
| JP2635995B2 (en) * | 1988-05-18 | 1997-07-30 | 株式会社日立製作所 | System with processor |
| JPH0289149A (en) * | 1988-09-26 | 1990-03-29 | Matsushita Electric Ind Co Ltd | Bus priority device |
| US5081578A (en) * | 1989-11-03 | 1992-01-14 | Ncr Corporation | Arbitration apparatus for a parallel bus |
| EP0426413B1 (en) * | 1989-11-03 | 1997-05-07 | Compaq Computer Corporation | Multiprocessor arbitration in single processor arbitration schemes |
| EP0444711A3 (en) * | 1990-03-02 | 1994-07-20 | Fujitsu Ltd | Bus control system in a multi-processor system |
| US5414818A (en) * | 1990-04-06 | 1995-05-09 | Mti Technology Corporation | Method and apparatus for controlling reselection of a bus by overriding a prioritization protocol |
| US5297277A (en) * | 1990-08-31 | 1994-03-22 | International Business Machines Corporation | Apparatus for monitoring data transfers of an oemi channel interface |
| JPH06110825A (en) * | 1992-09-30 | 1994-04-22 | Nec Corp | Common bus control system |
| US5519838A (en) * | 1994-02-24 | 1996-05-21 | Hewlett-Packard Company | Fast pipelined distributed arbitration scheme |
| US5740383A (en) * | 1995-12-22 | 1998-04-14 | Cirrus Logic, Inc. | Dynamic arbitration priority |
| US6374319B1 (en) | 1999-06-22 | 2002-04-16 | Philips Electronics North America Corporation | Flag-controlled arbitration of requesting agents |
| FR2894696A1 (en) * | 2005-12-14 | 2007-06-15 | Thomson Licensing Sas | METHOD FOR ACCESSING A DATA TRANSMISSION BUS, DEVICE AND CORRESPONDING SYSTEM |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5812611B2 (en) * | 1975-10-15 | 1983-03-09 | 株式会社東芝 | Data Tensou Seigiyohoushiki |
| US4059851A (en) * | 1976-07-12 | 1977-11-22 | Ncr Corporation | Priority network for devices coupled by a common bus |
| US4096571A (en) * | 1976-09-08 | 1978-06-20 | Codex Corporation | System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking |
| US4096569A (en) * | 1976-12-27 | 1978-06-20 | Honeywell Information Systems Inc. | Data processing system having distributed priority network with logic for deactivating information transfer requests |
| SE414087B (en) * | 1977-02-28 | 1980-07-07 | Ellemtel Utvecklings Ab | DEVICE IN A COMPUTER SYSTEM FOR SENDING SIGNALS FROM A PROCESSOR TO ONE OR MANY OTHER PROCESSORS WHERE PRIORITY SIGNALS ARE SENT DIRECTLY WITHOUT TIME DELAY AND OPRIORATED SIGNALS ORDER ... |
| US4121285A (en) * | 1977-04-01 | 1978-10-17 | Ultronic Systems Corporation | Automatic alternator for priority circuit |
| US4257095A (en) * | 1978-06-30 | 1981-03-17 | Intel Corporation | System bus arbitration, circuitry and methodology |
| IT1100916B (en) * | 1978-11-06 | 1985-09-28 | Honeywell Inf Systems | APPARATUS FOR MANAGEMENT OF DATA TRANSFER REQUESTS IN DATA PROCESSING SYSTEMS |
| US4271467A (en) * | 1979-01-02 | 1981-06-02 | Honeywell Information Systems Inc. | I/O Priority resolver |
-
1984
- 1984-12-12 SE SE8406312A patent/SE445861B/en not_active IP Right Cessation
-
1985
- 1985-10-30 NZ NZ214010A patent/NZ214010A/en unknown
- 1985-11-01 KR KR1019860700547A patent/KR910003015B1/en not_active IP Right Cessation
- 1985-11-01 JP JP60505172A patent/JPH0630086B2/en not_active Expired - Lifetime
- 1985-11-01 EP EP85905902A patent/EP0205472B1/en not_active Expired
- 1985-11-01 US US06/882,933 patent/US4791563A/en not_active Expired - Lifetime
- 1985-11-01 DE DE8585905902T patent/DE3572552D1/en not_active Expired
- 1985-11-01 WO PCT/SE1985/000429 patent/WO1986003606A1/en active IP Right Grant
- 1985-11-01 AT AT85905902T patent/ATE45825T1/en not_active IP Right Cessation
- 1985-11-01 BR BR8507112A patent/BR8507112A/en not_active IP Right Cessation
- 1985-11-15 MX MX629A patent/MX158467A/en unknown
- 1985-11-20 TR TR47073/85A patent/TR22658A/en unknown
- 1985-11-25 GR GR852847A patent/GR852847B/el unknown
- 1985-12-04 PT PT81612A patent/PT81612B/en not_active IP Right Cessation
- 1985-12-04 IE IE3053/85A patent/IE57050B1/en not_active IP Right Cessation
- 1985-12-05 EG EG777/85A patent/EG17290A/en active
- 1985-12-06 IT IT23124/85A patent/IT1186409B/en active
- 1985-12-10 CA CA000497302A patent/CA1241767A/en not_active Expired
- 1985-12-11 ES ES549805A patent/ES8702677A1/en not_active Expired
- 1985-12-12 MA MA20820A patent/MA20594A1/en unknown
-
1986
- 1986-06-24 FI FI862682A patent/FI88549C/en not_active IP Right Cessation
- 1986-07-08 NO NO86862764A patent/NO170999C/en unknown
- 1986-08-11 DK DK381686A patent/DK165077C/en active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |