CA1232034A

CA1232034A - Programmed logic array

Info

Publication number: CA1232034A
Application number: CA000442792A
Authority: CA
Inventors: Mark E. Thierbach
Original assignee: Western Electric Co Inc
Current assignee: AT&T Corp
Priority date: 1982-12-08
Filing date: 1983-12-07
Publication date: 1988-01-26
Also published as: US4661922A; JPS60500038A; WO1984002433A1; GB8332605D0; EP0128195A1; GB2131993A; GB2131993B; EP0128195A4

Abstract

PROGRAMMED LOGIC ARRAY

Abstract A programmed logic array is equipped with a first master-slave shift register on the intermediate wordlines between AND and OR planes of the PLA and a second master-slave shift register on the output lines from the OR plane.
In this way, since the propagation delays of both AND and OR planes are much larger than those of the registers, the speed of operation of the PLA is limited to the greater of the propagation delays of the AND and OR plane instead of the sum of these delays as in prior art.

Description

Lowe PROGRAMMED LOGIC ARRAY

Field of the Invention This invention relates to programmed logic arrays (Plus).
Background of the Invention Programmed logic arrays (Plus) are used in digital data processing systems to perform logic calculations or transformations in accordance with prescribed logic transformation rules. A conventional PLY
comprises two logic array portions known as the AND plane and the OR plane. The AND and OR planes are electrically connected together by paths or lines known as interconnecting word lines, say n in number. During operation, a sequence of binary input data signal combinations is entered into the AND plane on a plurality of input lines, say N in number, in order to furnish a sequence of binary input combinations or input words, and a sequence of binary output data signals or output words emanates in response thereto from the OR plane on a plurality of output lines, say P in number. When the PLY
is adapted for use as a finite state machine, one or more of the binary output signals from the OR plane can be fed back as input bits to the AND plane. Both AND and OR
planes, in certain specific embodiments, comprise orthogonal row and column lines mutually intersecting at cross points; and at each of the cross points is situated or is not situated a cross point connecting link such as a transistor, depending upon the desired logic transformation function of the PLAY
In ordinary operation with a PLAY it is desired that the PLY should handle many input words in sequence, one input word after another, and should deliver its corresponding output words in sequence, one output word after another. Accordingly, the PLY is supplied with data shifting means for repetitively temporarily storing and ~32~3!3~

shifting data into, through, and out of, the PLA--all in accordance with a suitable time sequence, so as to avoid confusion of one word or set of data (say, old data) with another (say, new data) in the PLAY Moreover, the PLY must be able to receive each new input word and to deliver each new output word at appropriate respective moments of time or during appropriate time intervals, according to the system requirements of the rest of the data processing system in which the PLY operates. Such system requirements typically are "synchronous": that is, the PLY receives data from and delivers data to the rest of the system in response to clock control tiring, typically in the form of a sequence of clock pulses. In such a case, the PLY can receive input data only during a first predetermined portion or phase of each cycle of the clock control, and the PLY can deliver output data only during a second predetermined (in general, different) portion or phase of each such cycle of the clock. Accordingly, the rate at which the PLY processes (receives and delivers) data is inversely proportional to the period T of the control clock and is directly proportional to the clock frequency flyweight.
The data shifting means required in a PLY
ordinarily takes the form of a pair of clocked parallel shift registers for temporarily storing periodically shifting data. The pair of registers is ordinarily connected and supplied with control timing so as to operate in a "master-slave" relationship, that is, one of the registers serving as the "master" register and the other as its "slave." By definition, the master receives data from an external source (such as another register) and its slave receives data from its master, all in response to control timing arranged so that when one of the registers (master or slave) can receive new data, the other cannot.
In prior art, a single pair of registers is used in master-slave relationship to control the flow of data through a PLAY and thus the PLY operates with single-level control timing whereby data is transferred through and is :~232~3~

processed by the PLY within a single clock cycle. Thus, in prior art, input data enters into, is transformed by, and emanates from the PLY as (logically transformed) output data all during a single cycle (or "clock period") of the control timing of the registers.
Single-level control timing is exemplified in toe prior art by placing a master register in the word lines, between the AND and OR planes of a PLAY and a slave register in the output lines of the OR plane of the PLY as described in a paper by E. Hebenstreit et at entitled "High-Speed Programmable Logic Arrays in ESFI SOS
Technology," published in IEEE Journal of Solid State Circuits, Vol. Scull, pp. 370-374 (1976). Alternatively, a master register can be placed on the input lines of the AND
plane and a slave register on the output lines of the OR
plane.
There is an upper limit on the clock frequency flyweight usable by the PLAY and hence upon the rate at which the PLY can process data. This upper limit stems from the inherent propagation delay times of the circuit components of the PLY (AND plane, OR plane, and registers), that is, the minimum time required for data to be transferred from one (input) end of a component to the other (output) end thereof regardless of how fast the clock frequency may be. For proper operation, therefore, to avoid undesirable confusion of old and new data, the clock cycle time or period used in single-level PLY control timing should be greater than the sum of the propagation delays of the AND and OR planes plus the sum of the propagation delays of the register, and the minimum time interval between successive words that can be processed and delivered by the PLY is limited to approximately this sum of propagation delays. Moreover, the maximum speed at which the PLY can operate is often the limiting factor on the overall speed of operation of the entire data processing system in which the PLY operates. It would therefore be desirable to slave a means for increasing the 4 ~23~

maximum possible speed at which a given PLY can operate.
Summary of the Invention In accordance with one aspect of the invention there is provided a programmed logic array comprising (a) an AND plate; by an OR plane; I intermediate word lines connecting the OR plane to the AND plane; (d) a first master register connected in the intermediate word line, for receiving intermediate data from the AND plane in response to a first control timing sequence; (e) a first slave register connected for receiving the intermediate data from the first master register and for delivering the intermediate data to the OR plane in response to a second control timing sequence; and (f) a second master register connected for receiving output data from the OR plane in response to a third control timing sequence, the propagation delays of the OR plane and of the AND plane being much larger than those of any of the registers.
A PLY in accordance with the invention, comprises an AND plane, an OR plane, and a plurality of intermediate word lines connected there between, with a first master and a first slave parallel register both connected on the intermediate word lines in master-slave relationship for receiving intermediate data from the AND plane and delivering the intermediate data to the OR plane, a second master parallel register (e.g., 16) connected to receive output data from the OR plane, and a second slave parallel register connected to receive output data from the second master register.

- pa - lZ3~034 Brief Description of the Drawing FIG. 1 is a block diagram of a PLY equipped with shift registers in accordance with this invention;
FIG. 2 is a diagram of control timing sequences useful in the embodiment shown in FIG. l;
FIG. 3 is a schematic circuit diagram of a pair of registers, in master-slave relationship, useful in the embodiment shown in FIG. l; and FIG. 4 is a block diagram of a PLY equipped with shift registers in accordance with another embodiment of the invention.
Detailed Description As shown in FIG. 1, a PLY 100 includes input lines If, INN, an AND plane 11, intermediate word lines We, Winnie, a first master parallel register 12, a first slave parallel register 13, an OR plane 14, OR
plane output lines Al 2 up' an inventor array 15, a second master parallel register 16, a second slave parallel register 17, and PLY output lines Al' Z2 zip The signal output on line Zip, for example, is fed back on a feedback line 25 to become a signal input on line IN, in order, as is known, to implement a finite state machine.

Jo I

The first master register 12 includes a linear array of master stages, each stage typically a clocked flip-flop device, each labeled M, and the first slave register 13 also includes a linear array of slave stages, each stage typically also a clocked flip-flop device, each labeled S. A specific example of a clocked master stage and a clocked slave stage is shown in FIG. 3 and is described hereinafter. Similarly each of the second master and slave registers 16 and 17 (with master stages M and slave stages S), is typically in the form of a linear array of clocked flip-flops. Each master register can receive data when and only when a fist control timing sequence I
is HIGH; each slave, when a second control timing sequence I is HIGH. The inventor array 15 serves to invert (from ONE to ZERO, from ZERO to ONE) the signals on the OR plane output lines 1~ 02...0P emanating from the OR plane 14, to form PLY output signals on PLY output lines Al' Z2 zip The inventor array 15 is optional and can be omitted in case inversion of signal on the output lines is not desired.
The phases of the control timing I and I for the registers 12, 13, 15, and 16 are arranged in general so that when data can enter into a master register none can enter into its slave, and when data can enter into a slave register (from its master) none can enter into its master.
Accordingly, waveforms of the control timing sequences for the master and slave registers, respectively, can be selected as represented in FIG. 2, that is, first and second clock pulse sequences I and I respectively, of mutually non overlapping HIGH phases. These sequences are thus arranged as desired: whenever I is HIGH and the master registers can receive data, then I is LOW and hence none of the slave registers can receive any data, and whenever I is HIGH and hence the slave registers can receive data, then I is LO and hence none of the master registers can receive any data.

- 6 - ~Z3~34 During operation, an input data word enters the AND plane 11 of the PLY 100 on input lines If, INN
either from an external source (not shown) or as feedback (in the case of IN, for example), and the input data are transformed by the AND plane into intermediate data which are received by the first master register 12 on word lines We, Winnie emanating from the AND plane during a HIGH phase (e.g., loll) of the first sequence I Next, during the succeeding HIGH phase (t2t3) of the second sequence I these intermediate data are received by the first slave register 13. Then, during the succeeding HIGH
phase (t4t5) of the first sequence I the intermediate data from the slave register 13 are transformed by the OR
plane 14 and the inventor array 15 and are received as output data by the second master register 16. Next, during the succeeding HIGH phase (t6t7) of the second sequence I
the output data are received by the second slave register 17 from the second master register 16. The data, as thus processed by the PLY into output data, are then available for transfer into other registers located in other portions of the data processing system (not shown) in which the PLY 100 operates.
An advantage of the inventive Plus is now described.
Data being processed by a PLAY according to this invention, take two cycles of the clock to be transferred through the PLAY as opposed to one cycle in prior art; and while one set of data is being transferred through (and logically transformed by) the AND plane, another set of data is transferred (by the registers) through the OR
plane. In this way, the speed of operation as determined by the speed of the control timing (clock cycle period) can be approximately equal to the larger of the propagation delay times of the AND and OR planes rather than to the sum of these two delay times as in prior art. Accordingly, for example, in case the propagation delays of AND and OR
planes are approximately equal, the PLY can operate at Lowe approximately twice the clock rate that is possible in prior art, and thus the PLY can then process data likewise at approximately twice the data processing rate possible in prior art. The PLY thus still yields a (full) new output word during every new clock cycle, even though the PLY now requires two clock cycles to process each word. Thus, by using the higher clock frequency made possible by this invention, the PLY supplies output words at a correspondingly higher rate, even though it now takes two clock cycles for the PLY to process each word.
FIG. 3 shows an example (from prior art) of a pair of register stages (master stage M, and slave stage S) in master-slave relationship, useful for the registers in the PLY 100. A transistor 31, controlled by the first sequence I serves as an input gate for the master M; and a transistor 35, controlled by the second sequence I
serves as an input (or coupling) gate for the slave S. A
pair of inventors 32 and 33, together with a transistor 34 in a feedback loop and controlled by the second sequence I serves as a regenerative temporary storage means (latch) for the master M; and a pair of inventors 36 and 37, together with a transistor 38 located in a feedback loop and controlled by the first sequence I serves as a regenerative temporary storage means (latch) for the slave S. During HIGH phases of the first sequence I the transistors 31 and 38 controlled by this first sequence are ON, and are OFF otherwise. During HIGH phases of the second sequence I the transistors 34 and 35 controlled thereby are ON, and are OFF otherwise.
During operation, for example starting at time interval loll when the first sequence I is HIGH
(transistors 31 and 38 ON, transistors 34 and 35 OFF), data is received by the master M and is amplified by inventors 32 and 33 and reaches a feedback node FM located between inventor 33 and transistor 34. because input transistor 35 in the slave S is OFF during loll, no data - can then be received by the slave S. Next, during t2t3 ~L23~(~34 when the second sequence I is HIGH and hence transistors 34 and 35 controlled thereby are ON
(transistors 31 and 38 are OFF), the data then enters into the slave S and is amplified by inventors 36 and 37 and reaches a feedback node US located between inventor 37 and transistor 38. At the same time (during t2t3), since transistor 34 in the feedback loop of the master M is ON, the inventors 32 and 33 are cross-coupled (latched) together, thereby furnishing a temporary regenerative static latch. Next, during t4t5 when the first sequence is again HIGH, input transistor 31 enables entry of new data into the master M, while thin cross-coupled inventors 36 and 37 latch the old data in the slave S now that its feedback loop transistor 38 is ON, but the slave S cannot now (yet) receive the new data because its input (coupling) transistor 35 is OFF. Thereafter, during t6t7, I is HIGH, the slave S receives the new data from its master M which then is latching the new data. In this way, data is repetitively shifted into and through the master and slave registers, new data replacing old data.
The feedback loops formed by inventors 33 and 37, together with the transistors 34 and 38, respectively, serve as (regenerative) static latches for the master and slave, respectively. Static latches have the advantage of being able to store data in case the control timing terminates, i.e., the clock stops, so long as DO power continues to be supplied to the inventor. In cases where a static latch function is not required in either master or slave (or both), either (or both) of these feedback loops can be omitted; that is, instead of static register stages M or S (or both), dynamic register stages can be used, as known in the art. Moreover, the inventor array 15 can be omitted by placing one of the inventors in the feedback loops of master or slave register 16 or 17 into the direct data path, that is, for example, by placing the inventor 33 between the transistor 31 an the inventor 32, as suggested in the aforementioned paper by 32~;~4 g E. Hebenstreit et at.
FIG. 4 shows a PLY 400 equipped with two-level -control timing in accordance with another specific embodiment of the invention. The PLY 400 is similarly constructed as the PLY 100 except for the placing of the second slave register 18 on the input lines If, INN
rather than on the output lines. The second slave register thus serves as an input register 18 for the AND plane 11.
The same reference indicators are used in FIG. 4 as in FIG. 1 to denote similar elements. It should be understood that this input register 18 typically is formed by a parallel register having N parallel stages An advantage of the arrangement shown in FIG. 4 is that the control timing of the input register 18 can easily be grated with combinatorial logic; that is, instead of using the second clock pulse sequence I as the control timing for the input register 18, this sequence I is AND-grated by an auxiliary or WAIT signal, and the resulting grated (interrupted) I sequence is used as the control timing for the input register 18. Briefly, the control timing sequence I for the input register 18 is stopped (interrupted) when the WAIT signal is LOW ("unready") and thus the finite state machine is frozen with the same data on all feedback lines until the WAIT signal goes EYE
("ready") and thus the machine resumes normal operation with the periodic (not-stopped) control timing sequences I
and I The use of a WRIT signal, and the advantages of such use, are described in co-pending application entitled, programmed Logic Array, filed on the same day as this application.
In another variation, instead of the first and second non overlapping clock pulse sequences I and I a clock pulse sequence of HIGH and LOW phases of equal durations together with its complement I, respectively, can be used as control timing for the registers in those cases where the safety margin against undesirable "race-through"
(premature shifting) afforded by the time intervals tlt2 ~32034 t3t4, t5t6, t7t8 (when both sequences are LOW) is not required, as known in the art. Also especially in FIG. 4, the master registers equivalently can be denoted as slave registers while the slave resisters are denoted as master registers.

Claims

Claims:

1. A programmed logic array comprising:
(a) an AND plane;
(b) an OR plane;
(c) intermediate word lines connecting the OR
plane to the AND plane;
(d) a first master register connected in the intermediate word line, for receiving intermediate data from the AND plane in response to a first control timing sequence;
(e) a first slave register connected for receiving the intermediate data from the first master register and for delivering the intermediate data to the OR plane in response to a second control timing sequence, and (f) a second master register connected for receiving output data from the OR plane in response to a third control timing sequence, the propagation delays of the OR plane and of the AND plane being much larger than those of any of the registers.

2. The programmed logic array of claim 1 further comprising a second slave register connected for receiving the output data from the second master register in response to a fourth control timing sequence.

3. The programmed logic array of claim 2 in which the third and fourth control timing sequences are substantially the same, respectively, as the first and second control timing sequences, whereby the PLA operates with two-level control timing.

4. The programmed logic array of claim 1 further comprising a second slave register connected for receiving input data and for delivering the input data to the AND plane in response to a fourth control timing sequence.

5. The programmed logic array of claim 4 in which the third control timing sequence is substantially the same as the first.

6. The programmed logic array of claim 5 in which the second master register has at least one output line which is connected as an input line to the second slave register, whereby the programmed logic array implements a finite state machine.