CA1231790A - High speed image generation of complex solid objects using octree encoding - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE An image generator for generating two-dimensional images of three-dimensional solid objects at a high speed defines a scene to be displayed within a cuboid three-dimensional universe which has been hierarchically subdivided into a plurality of discrete volumes of uniform size and similar orientation. The three-dimensional universe is represented by a tree structure having a plurality of nodes, one for every volume in the three-dimensional universe which is at least partially occupied by objects in the scene. A user selects a point of view for viewing the object. Nodes in the tree structure representing the three-dimensional universe are visited in a sequence determined by the point of view selected by the user so that nodes corresponding to volumes which are unobstructed by other volumes are visited first. Each visited node enclosed by the object is projected onto a subdivided view plane organized into a hierarchy of a plurality of discrete areas. Areas of the view plane which are completely enclosed by the projection are painted onto a display screen. Areas which intersect but are not enclosed by the projection are further subdivided to locate those areas which are enclosed. A representation of the hierarchically-subdivided view plane arranged in a tree structure is stored. Each time an area of the view plane is painted, an entry in the representation of the view plane corresponding to that area is marked. The corresponding entry in the representation of the view plane is checked before an area is painted, to ensure that no area is painted more than once so that hidden surfaces are not displayed. To create sectional views, a user may define a region of the three-dimensional universe, and volumes outside of that region are not projected. Real time image generation wherein calculations necessary to create the image are performed by hard-wired digital logic elements to increase speed performance is possible.

Description

=~L~
~0I.~D OBJEC$S U8IN~: ~TREE_ ENCODI~G;

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The invention generally relate ~o sc:lid ~od~ling o~ three-dim~nsional ~olid objec~s ~nd more par~icularly ~o ~ me~hod and ~pparatus ~or ~he high-speed ~eneration oÇ a two-dimensional image o~ a three-di~ensional solid object wherein surfaees hidden from the viewer from a selected point of view are elimina'ced from the image. The ir.vention is appli~able wherever the qener~tion of twoo dimensional images of solid objects of arbitrary complexity must be perform~d in real time, and is especially suited for interac~ive image gen2ra~ion systems, ~.~CK~XOUND OF T~E INVENTION

Countle~s applicatio~ presently ~xist for ~uto~ated solid ~odeling, the automated r~pre~enta~lo~, ~anipulation, ~n~lysis and display of 301~d ob~ect ~ Perhaps the primary appli~ation for solid ~odeling systems at present are in C~D/C~M
~Computer-~id~d Design and Computer-Aided 1~317~

Manuf~c'cur~1 systela~. Such ~y~em~; per~it the ~f~ ci~tl'c design and analy~is ~ n~ec:h;~ni~al part~, the ~n~ysi~ o space u~ilization process@q lor instanco packaging, ~roces~ planning, roboticst parts ~se~bly, etc. ), moleeul~r ~odeling, and literally countles~ of other u5es-Solid ~o~eling sys~ems have al50 beenapplied ~o medical imaging, where an image o~ a por~ion of ~ human body is generated f rom da~a acquired by a CT ~Co~puter Tomography), ~MR or Ultrasourld 5canne~ to per~it a physician ~o study, analyze and manipulate the image. Using such syst~ms, phy~icians are able to selectively view p~rtisns of the anatomy under study f~om v~rious viewing angles and ~t different magnifica~ions, employ an "electronic scapel~ to cut out parts of the anato~ny, ~nalyze volume~ ~nd displacements to determine the size and location of ana~omical tructure~, etc.
Another u5eful ~pplication o~ olid modeling ~y~"ems i~ in flight ~i~ulator~, which permi~ a pilot to tr~in under a variety of flight conditiorls without. the associ~ted danger and ~o~t of u3ing an actual aircraft. Another applic~tion i~ in seismology, wherein a geologist may study and analyze images created ~ro~ acoustical or

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~l~ctro~gneti~ d~ta ind;c~tiv~ o~ ~inera~
c~ur~ o~ ~he ~rthS~s 3u~fac~ in order o pr~dic~ th~ location o~ valuable ~in~ral depo~it~, the o~currence of ~ei~mological ~isturbanc~s, ~tc.
Y~ another application i~ in the ~ield o~
~rtificial vision wherein template~ of three-dimensio~al obje~ts viewed from various angles and perspe~tives must bc co~pared with observed data to permit the reoo~nition of objec~s. ~urther applica~ion~ of solid ~odeling system~ include the generation of realistic im~ges of physi~al objects sr analytically-defined objects and permitting the i~teractive manipulation o~ these im~yes for use in ~ine~ato~raphy and video ~rcade game~. ~s solid modelin~ ~ystems be~ome more effieient and les5 costly, numer~us other applications for them w 11 no doubt be ~ound.
There are sev~ral differ~nt solid modeling sys~em~ presently commercially available~ but all of the~ ar~ li~ited by re~trictions on the way in w~ich the object t~ b~ i~aged i~ r~present~d or the .~peed a~t which the i~age i~ genera~ed. M~ny available ~y~t~ do not per~i~ an object o~ arbi~rary co~plexity to be represented. Others can o~rate on object~ of essentially arbitrary complexity ~nd configur~tions~ but require a sub~tantial amount o -^-` 123179~

real ti~e to generat~ single i~ages ~of~on th~ ei~e to genera~e ~ne i~age ~ay be ~easur~d in ~inute~ or hour~) becau~ Qf the ex~re~ely lar~e nu~b~r Of sal~ulation re~uired to p~rform interference detec~ion, hidden-~urface re~ov~l and obje~t ~nipulation on ~uch arbitrarily complex obje~ts.
Of cour~e~ ~he ti~e it takes So gen~ra~e an image i~ not critical in many applica~ions.
~owever~ if a human b~ing mu~t interact with ~he image generation process lfor instance, to define points o ~iew, ccaling facto~s, se~tional views, e~c.~ D it may be desirable to gener~te ima~es in r~al ~im~. For instance, video arcade games and flight ~imulator~ r~quir~ a real time response in g~nerate~ images when a user D~era~e various intera~tive input devices. Likewi~e, the creative thought processes of a physician w~uld be severely inhibit~d if he or ~h~ h~d to wait minutes or hours after specifying a view of a portion of a patient's ana~omy b~fore actually seeing the r~sulting image. Productivity ~f a CAD/CAM sys~em decreases dra~at;cally as the i~e required to g~nerate each im~ge ~n~r~2ses.
50~e commercially available graphic~
system~ reduce the ~ime required ~o genera~e images by no~ tru~y modelin~ the three-dimensional object to b~ ~ged, but rather projesting only the ~dg~s lraith~r than th~ aurface~) o~ th~ obje~t onto display ~creen. The det2rmin~tion o$ wha~ i~
actually ~olid i~ left to human interpretatiorl in such imagin~ ~yst~ns. Whil~ quit~ ~uitable for many applications, such system (which in reality can only be used as sophisticated autos~ated draf ting sys~e~s) do not produce realistic images of solids.
Variou~ s~he~es for repre~enting solid ob jec~c5 to be imag~d ~re employed by exis~ing true solid modeling systems . ~ome ~systems def ine the object to be imaged ~hrough pr:lmitive instancing, wherein families of objects ar~ defined in terms of a primieive ~hape type ~or example, a certain kind o~ polyhedron) and a limited s~t o~ parameters furth~r specifying the shape. Spatial enumeration, .whereln an ob~eGt is represented by the cuboid spatial thre~odimensional cells whi~h it occupies, i~ anoth~r method conventionaliy used to def ine a three-di~ensional obje~. R generalized form of spatial enumer~tion i~ sell decomposition, in which the spatial cells are not n~cessarily cuboid or even identical. Another method ronventionally us~d i~
constructive solid geometry ~CSG), wherein objeces are represented as collections of primitive ~olids such as cuboids, cylinders, etc. Tree struceures - ~ ~

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~e typi~al~y usea ~o org~nize th~ primitive ~olids, wh~r~ln leaf nod~ of the tree ~epre~ent the pri~itives and branch node~ ~pecify ~t op~r~tion~
performed on the primi~ive~. Yet another method of repre~enting ~ ~olid i5 by defining it as the volume swept ~y ~ two-dim~nsional o~ three-dimensional hape as it i5 translated along a curve. Finally, boundary re~resentation is conventionally used to repre~ent ob3e~ts by ~h~ra~erizing them according to the~r enclosing ~urfaces (i~o planes, quadrate ~urface~, patches, etc.).
Speciic advantages and disadvan~ages of ~he various ~ethods of object represen~ation conve~tionally employed togeth@r with a classifica-tion of some existing solid mo~eling systems may be found in Requicha, A.~ and Voelcker, ~., "Solid Modeling: Cu~rent Btatus and ~e~earch Direc~ions,"
IEEE Com uter Graphic~ and Applic~ions, Vsl. 3, ~o.
7, Oot. 1983, pp. 25037, and Xequlcha, ~4 t and Voelcker, BD ~ ~SO1id ~odelings A ~i~tori~al Summary and Contemporary Asse~sment~
and ~E~lications, Vol. 2, No. 2, March 1982, pp. 9-240 ~e~ al~o ~er, A., E~stman, C., and ~enrion, M., ~Geom~tric Modeling: ~ Survey Desi~n, Vol. ll, No. 5, Sept. l9~9.

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~ o~t c~mmer~ally ava~lab~ solid ~od~linq sy~e~ u~e eith~r con3tructive ~olid geome~ry or bound~ry repre~nt~ion (or a combinati~n o~ t~
t~oj ~. th~ pri~ary schem~ to represent ~he object. For e~a~ple, ~ TIP5, the PA~L, and ~he 5ynthaYisi~n systems use a ~onstru~tive olid geo~e~ry repres~nta~ion scheme; the ~uild~ CADD, Design, Solidesign and Romulus ~yst2ms employ ~he boundary r~pr~sentation scheme: the EUKLID and GMSolid ~ystems u~e ~ combination of these Swo sche~es. 50me sy~tems per~i~ alternate representations, such as al~ernate data input schemes wherein an ob~ect may be defined by the swept volume representation. The TIPS sys~m c~
~o~t the primi~ive~ into a spatial enumeration arr~y to facilitate interference analysis.
New ~e~hods are needed to solve or a~ least reduc~ ~ number of proble~ which have plagued solid modeling ~yste~ç developed in the past. Many existing ~y~tems seriously re~trict the objects whieh can be imaged because of the constraints impos~d ~y the repres~n~ation che~e used~ Serious li~itati4ns ~re i~posed when the obje~t mu~t be defined by a li~ited number of mathematically well-defined surf~ce or solid primitives. Many .~hemes ~au~e extraneous ~ur~a~es not corresponding to true ~?317~

~urfac~ in ~h2 th~ di~ensiona~ ~b~ect ~o be includ~ the g~nerat~d i~ag~ due to i~pr~ci ion in t~e obje~t represen~atlon.
~ n i~portant drawback of pr~sent ~olid modeling ~ystems wh~re real ~ime image qeneration is des;red i~ the often huge amount of d~ta required to repre~ent an objeet of a~bitrary comple~ity, and the efficieney o~ the operation~ which must be performed on ~his data to generate an image. The computa tional eomple~ity and memo~y ~e~uirements o~
~lgorithms used to generate the image should not g ow at a rate faster than linear ~ith the number and oomplexity of object~ to be imagedO ~ost present systems whi~h ean represen~ ob~ec~s of arbitrary complexi~y do not ~atisfy the~e requirements.
~ inally, ~ost ~xisting solid modeling system~ were designed usin~ limited hardware and storage reçource desiqn constraints~ Because the amount of hardware i5 oft~n traded of with the speed peror~anc~ o~ ~he ~yste~, exi~ting solid ~odeling $yste~s generally hav~ poor speed per~or~anee a~ ~ re~ult. ~ith the ~dvent o~
inexpen~ive ~olid st~te ~emory and hardware tbrough~
about by the advent of VLSI technoloqy~, larger amount~ o hardw~re can now be used a~ relatively 1 7 9 1~

l~ttl~ eo~t ~o ~chie~e ~a~ter proces~ing ~ than eoùld ~ re~l;z~d previou~ly..
One o~ thc k~y~ ~co th~ e~icien~ ~er eration oi~ i~lla9@9 of !~ol.idB i~ to li~i~ a~gorithms to a linear grow~ch rate. One ~ethod which may be used to limi~ growth ra~e in i~age generation i~ the hi~rarchical subdivision of the di~play ~urface into pro~re~sively smaller area~. Such a scheme i~
.disclosed in Warnock ~J.S. P~en~ ~ao. 3,602,702, issued ~ugus'c 31s 1971~ wh~ch disclose~ a method and system for electrorlically gener~ting and displaying shaded two-dimensional perspe~tive images of three-disnensional objects. Warnock discloses the represen~cation of an object to be di~play~d by plar.ar polygonal surace primi~:ives resulting when th~ obje~t is projected onto a view plane. A square ~iew plane i~ ~ubdivided into ~ number of ubsqu~res, each of which may be further subdivided if necessary. ~h~ urace primitive i5 teste~ with resp~ct to tAe variou~ ubsquares of the view plane to det~r~nin2 wh~th~r the subsqu~re i5 enclos~d by the ~urface primitive, inter~ec'c~ but doe~ not enclo~ the ~urface primitive~ or i5 compl~t~ly di~oint with the surf~c~ pri~itive. These ee~ts are~performed ~y ~omparing the c~ordinate3 of each ~ t~e line seg~ents of the surface primitive with .

the coordinat~s of th~ sub~guare of the view plan~
un~ te~t.
A ~ubsquare wh~h i~ entir21y ~nclo~ by a surface primiti~e ~ay b~ ~had~d on æ display s~reen.
Subsquares which in~ersec~ but a~e not enclosed by the 3urPace primitive are further subdivided un~il a level of resolution along the edge of ~he surace primitive is reached~ Of course, during the subdivi~ion process, new subsquare~ which are found to be enclo~ed by the surfac~ primitive are appropriat~ly shaded.
The use of two-dimensional hierarchical tre~ structure~ ~alled "quadtre~s" in the field o image processing to repres~n~ a hierarchically subdivide~ displ~y surface wa~ proposed in ~unter, G. ~. and Steiglitz, K., "Opezations on Imag~s Using Quad Trees,~ ~
and M~chine Intelli~enc@, Vol. PA~ o. 2, April 1979. ~osen~el~, A., "Quadtre~s and Pyramids for Pattern Recognition and Image Processing,"
Rroceedings of the 5th ~ntern~tion~l Conference on Pattern Recognition, December 1980, discus~e~ the u~e o~ quadtrees in pattern reoognition ~nd im~ge proces~ing~ S~me~ nd ~osenPeld, A., ~Quadtree Representation of Binary Images,~ Proceedings of the 5th International Confesen~e on ~at~ern '7~

Recognition, D~cember 1980, presents an ov~view of qu~'dtrees, w~ile Sa~et, ~ eighbor Findin~
Techn~que~ for Image~ ~epresensed by Quadtree~,"
Computer Graphics and_Ima~e Processln~, Vol. 18, 1982, 37 57 di~cusses techniques for finding neighbor~ for images re~resented by quadtrees.
~ he u~e o~ ~n 8-ary hierarchical tree to represe~t three-dimensional objec~s has been .suggesked in ~un~er, G. M., "Ef~icient Computa~ion and ~ata ~ructures for Graphics, n PhD dissertation, Electric~l Engineering and Compu~er Sci~nce Department~ Princeton Universi~y, June 1978 as a possible extension of quadtrees. This concept was later independently proposed in Jackins, C.L., and Tani~o~o, 5.L., ~Oct-Tr@es and Their U~ in R~pre-senting Three-Dimensional Objects," ~echnical Report 79-07-06, Depar~men~ oÇ Co~put~r Science, University of W~shing~on, 5eattle, July 1~79 ~ackins, C~L., and Tan~oto, S~L~, ~Oc~-Trees and ~heir Use in Repre~entin~ Three-~imensional Objects," Com~uter ~ ~ Dec. 1980; Srihari, S.N,, ~epresentation of Three-Dimensicnal Digital ~mage ~ Technical Report No. 16~, Dept. of Computer Soi~nc*, S~ate University o~ New York at Buff~lo, July 1980; Srihari, S~N., "Hierarchical Representatisn~ for Serial Section Images,~

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~roce~ding~ of ~he Stb International Conference on Pa~rn Re~ognition, Dec~mb~r 19~0 ~eagher, ~., ~Octr~e Encoding: A New Technique ~or the Repre~entation, ~anipulation and Display of Arbitrary 3-D Ob j~Ct5 by Computer," Technical Report IP~-TR-80-111, I~age Processing Laborato~y, Rensselaer Polytechnic Institu~e, October lg80~
Later papers discu~sing octree encoding include Doctor, L.J. and ~orborg, J.G., "Display Techniques for Octree-Enood~d Objects, n , ~ol. 1, NoO 3, July 19~ o~t~r, L., "Solid hodeling ~lgorithm~ Utilizing Octree ~ncoding,~ Center ~or Interactive C~mputer Graphics, Rensselaer Polyte~hnic Institute, December 1980;
Iftikhar, A.~ ~Linear Geom~tr.ic Trans~rmations on Octrees,H ~.SO th~sis, Electrical, Computer and Systems Engineering DepartmenS, Rens~elaer Polytech-nic In~titute, ~ay 1981; and Ya~, ~.M., and Srihari, S.N., ~ecur~ive Generation of ~ier~rchical Data Structures for Multidi~ensional Digital Images,"
Technical Repo~t No. 170, Dept. o~ Computer Science, State University o New York at Buffalo, January 1981.
~ ditionally, the pr~sent inven~or h~s published several papers discussing octree encoding. After publishing the paper in October, 1 2 3 ~ 7~

octroee ~s3codlng Jche~ he pr~6er.t ~nves~tor pr~ented ~dition~ u1t3 ~n ~ea~her, D.
W5~eo~aetr~ Mode~ 9 Us~ng Octr~e Encoding,~
~=L~, 19, June 1982.
~31i$p~ 1y ~1qorit2u~ wa~ cu~ed in Meagher, D., a~igh Speed ~l~p1ay ~ 3-D ~edical I~ag~ tJsiny Oc~re2 E:n~od~ng, " ~PL-TR-021, IDsage ~oce~sing La~or~ory, Rensse1aer Po1ytechni~ Inst~tu~, Sept.
1981, ~nd ~n upda~ed ve~ion of ~he displ~y ~1gorith~ W~3~ p~e~erlt~d ~n M~agher" D., UEffieient Synthetic I~age Gener~eion of ~itrary 3-D
Object~ ro~. IEEE Computer Soeiety Corlfer~nce on ~atte~n Reeogni~cion ~nd I~age ~roce~sing, June 1982.
Th~ de~elopJnen~c of eficient objec~ g~neratiorl d~lgorith~ w~ docum~n~ed ~ ~ea~her, E~ Oct2ee Si;eneration~ ~n~lysi~ ~nd Manipulation," IPL-TR-027, Im~ge ~roce!s~ing ~bor~tory, E~enssæl~er ~31y~echrlic In~tigu~e, Ap~l 1982. rinally~ a 3umn?~riz~ion of the oetr~e erl~oding ~ch~e ~nd ~l~orithms U5ed in coniunction with ~hat ~ch~r~e ~or e~icient ~olid ~deling ~ ~iwlos~d in Meagher, D., ~ 3rhe Octree E:ncoding Method or E~ i@nt Solid ~o~eling,!' IP~-2R~032, I~ge Pr~c~ssir.g ~boratory, Ren~ er ~slyt~chn3Lc ~n~lti'cut@~ ~ugu~ lD82.

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~4 ~M~Y OF rEIE INvENTlota ~ he presen~ ;nventiQs~ is; a ~ethod ~nd ~y~tem for ~ffiei~ntly ~ener~ting t~do-diMen~ion~l images of th~ee-diDIensional ~oli~ obj~ctsO Th~@e-dimen~ion~l sb~t~ to ~ age~ ~r~ d~fin~d wi~hin ~ uboid three dimen~ional univ~r~ ~hich ha~ been h~erarehic~lly ~ubdivi~e~l into ~ num~er of lev~
E3~h l@v@l in 'ch~ tbree-dilaension~l univer~
compsi3es ~ plusal~y of disc~/e~e ~rolu~es of uniform 3iæe ~nd ~i~ilar or~ene~lon. E2!~ch ~olu~e i~
characterized by th~ de9ree to which i~ ~ oc~upi~d ~y an object to be displ~yed. 15~ch volume ~n each af the levels o~ t~ hie~ chy i~ ~ ~ub~ivi~ion o 'ch~ ~c>luslle ~n the l~vel ~ ve i~ ~hich i~ parti~lly occupi~d by ~he o~j~c~ but RO~ o~cupi~d go ~
predet~r~ degr~. 3Cach ~ubdivi~d volum~ in the hie~archy ~ ~ubdivi~d into ~ight volumes of i~ent~cz~ ize7 ~hap~ ~nd c~sient~t;on.
~ h~ charac~ri~ation o ~he ~e9rg!@ to ~hich the ob~ct ~cs:up~ ch o~ tP~e volu3~e~ ~n tbe ~ree~di~@n~ional univer~e i~ ~to~d in node~ ~n ~n o~tree ~truc~tur~ ~ont~ined in an ~ctree ~n~oded 1 ~3 1 7~

~to~g. Object~ of arbitrary complexi~y and ~llape ~ay ~ repYesented by ~ho oc~ree $~ructuze.
A u~er ~y interaot wi'ch ~he iallage ~i3play proceRs by 3p~ci~yiny, among other thing~, ~he point of view for vi~win~ ~he object.
A two-dimension~31 view plane is established. The view plane i~ organized into a hieraschy of a prede'cermined nu~ber of levels. ~aoh level in the hierarchy co~Dpris~s a plurality of di~crete area~ of unifor~ ~ize and orientation.
ach of th~ ~rea~ in ea~h of the levels is a subdivision of an a~ea in the l~vel in ~he hierarchy above ~hat level.
Nod~s in the octree struc~ure ar~ visited in a sequenc~ determiFled by the point of view sele~ted by the user sv that nodes corresponding to volumes which arQ unobstructed by other volum. ~ are visite~a fir~t. Volume~ occupied by ~he object are projected onto the view plan2 at a location a~nd orientatiorl determined by ~he ~elect~d point o view an~ the locatio!- of th~ volù¢le in the thre~-di~enslonal univer~e.
arQas of ~he view plDn2 are tes~d e~
deter~ine if they are c4mpl~tely ~nclose~ by ~he projeceion, intersect but are nc~t en lc~sed by ~che projection, c~r are ~ompletely disjoint with the 1~317~Q

, proj~ctionO ~r~a~ which ~r~ ~o~l~tely en~lo~ed by th~ p~ojection ar~ p~in~e~ onto ~ display ~cr~en ~ n ~r~ o~ ispl~y ~creen corr~po~ding to th~ enclos~d ar~a on the vie~ plane i~ shade~ in wi~h a given int~nsi~y~. ~reas wh;ch inte~sect but are not 2nclo~ed by the pro~ction are further subdivided to loc~te thos¢ area~ which ar~ enclosed so ~hat ~hey, too, can be painted. This ~ubdividing proc~ continues untal a predeter~ined tegree of resolution i~ reaohed.
Because o~ th~ ilarity in the shape and o~i~ntation of the volum~s of the thrce-dimensional l-niver e, ~he shape and orientation of the proje~tion of any volume will be precisely the same, differing only ~n location and Riæe. Likewise, beca~-se of the symmetry in the geometry o the ar~as in the vi~w plane, any two ~reas will diff~r only in siz~ and locatio~. For ~his reason, the calculation~ requar~d to test ~reas for intersection and enolosure with projection~ ~re ~imple tan~ can ~e saleulated ~y ~impl2 a~i~hmetic opera~ions which can be performed quiokly). Likewi~e, obje~es o ~rbitrary complexity may be represented by the octree ~tructure. In thi~ w~y, amages o ~hre~-dimen~ional objects of arbitrary complexity ~ay be ~ ~3 1 79~

g~ner~t~d wi~h a ~ini~u~ o ~al~ula~ion time, p~r~itt~ng high-~pee~ image generation.
~ quadtree ~tructure corresponding t~ the hierarchieally subdivided ~iew plane i3 ~tored in a separato ~tore. ~ac~ ti~e ~n area of the vi~w plane i~ p~inted, a loeation in the quadtree s~ruc~ure corresponding ~o that area is m~rk~d.
~ efore ~n area of ~he view plane is pain~ed, the location ~orresponding to that are~ i~
- the ~uad~ree structur* i~ checked. Areas corre~ponding to windows in the quadtree structure which have been ~rked will no~ be paint@d again.
In this way, hidden surfaces are not included in the image ge~rated.

3~cau e the projection o each ~f the volume in the three-dimension~l universe is a six-sided polygon having three internal faces, it i5 possibl~ ~o ~ t the area3 of the view plane for enclosuxe with the pro~ection of a face of the volume rather ~han with the ~ntire projection.
Areas enclosed by the projection of different aces ~ay be painted di~ferent colors ~o produoe a more reali~tic three-di~ensional image.
- A u~er may define a ~ub~et of the three-dimen3ional universe to ima~e. Volumes out~ide of -``` 123~79~

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thl~ ~ubset ar~ not projected o~ltO th~ vi~w plane, p~r~i~ting ~he creatiorl o sec~ional ~i~!WSo Due to th~ ~ieralchieal ~ructure o~ ~h~
~hr~e-di~nsional and the two-dimen~ional universe and the symsnetry o~ subdivi~ion3 of ~hose en~ities a~ well as to ~he simplici'cy of the calculations neces~ary to create an image, real time image generation i~ made possible.
Ths~e as well as othe~ objects and advan~ages of this inven~ion will be bet~er appreci~ted by study~ ng the following de~ailed description o the pre~esltly preferred exemplary embodim~nt of this invention in conjunction with the accompanying drawin~s.

BRIE~ DESC ~PTION O~ TEIE DRAWINGS

~ IGU~E l~A) is a graphic illustration of a three-dimen~ional universe and a thr~e-dimensional objeet de~ined within that universe to be imaged;

~ IGURE 1~) is ~ graphic illustration o~
the ut~i~rer~e shown in ~IGURE l(A) organized into an octree hierarchy whereirl the univer~e i~ de~ined as the root node of the octree;

1 2 3 1 ~ ~0 FIGURE l~C) gr~hically illustrat~s ~
fur~her ~ubdivision o child nod~ 1 of t~ ot nod¢
~how~ in FIGUR~ into ~ight children no~e~;

~ IGURE l(D) graphic~lly illus~rates a further ~ubdivisio~ of child node S of the root node show~ in ~GURE llB~ into ~i~ht childr~n nod~;

FIGURE 2 is a ~c~ematic representation of ~h~ octr2e ~tru~ture corresponding to the universe shown in ~IGURE l;

FIGURE 3(A) schematically illustr~tes a ~wo-dimensional viewing plane organized into a quadtree hierarchy, ~ome o the windows o~ whi~h are subdivided in~o child and ~urther subdivided into grandchild window~, wherein some of the defined windows o~ ~he viewin~ pl~n~ are p~inted;

~ IGURE 31B~ is a s~hematie repr2senta~ion of a quadtree ~tructure ~osre~ponding to the viewing plane ~hown in FIGURE 3~

FIG~RE 4(A) ~chematically illustra~s a traversal sequence of O to 7 of the eigh~ childrcn 3J7~

nOæe~ 0~ ~ny given node in ~h~ oct~ee ~tructure for a g~v~ viewing angle;

FI~U~ 4~) gr2phie~11y illu~tra~e~ ~n objec~ (co~pri~ing a single lev~l 3 nod~) within the octre~ structure ~hown in FXG~R~ 4lA);

FIGURE ~(C~ is a schematic representation of the recursive application of the traver~al sequence in the octr~e shown in PIGURE 4~) to further subdivide node 7 of the octree int~ children and grandchildren node3 in order to locate th~ node representing the obje~;

FIG~RE 5 i~ a schemat:ic representation of a threeodim~nsional object node projected on~o a two-dimensional viewing plane, the viewing plane being organized in~o a guadtree strue~ure:

FIGU~E 6[A) i~ a graphic illustra~ion o a projection oÇ the thr~e-dimensional sbject node chown in PIGURE 5, wherein th~ three visible faces of the node at a ~ivcn viewing angle are de~ined in th2 proi~Gtion;

" ~2~7~1~

FIaURE 6~EI) i~ a gral~h~s: illu~cra'ci:sn of a bo~nding box defin~d by th~ no~ projectio~ ~h~wn in FIG~ 6f~);

FIGURE: SIC~ i~ a graphic ~llus~ration o~
window overlay construeted 2Isound the node projection and the boundin~ box shown in ~IGURE 6t~) which it deines;

.
FIGUR~ 6(D3 i~ a graphic allu tr~ion of the su~diYision of the window overl~y ~hown in FIGURE 6(C) into a 4 x 4 winds~w array, and the selec~ion of ~ single 3 x 3 window array within that

4 x 4 array;

FIGllRE G(E~ i~ a graphic illu~'cration o~
the selection of a window overlay f rom the selected 3 x 3 window array shown in FIGI~RE 6(D~;

FIGURE 6 5 F) i~ a grapilic illustration of the selel:~ioa~ of on~ window from ~he ~leoted window overl~y ~hown in FIGURE 6~E);

~ IGURE 7 i~2 a graphic illustration of l~lle geome~ry assooi~ted wi th a bounding box te~t, a- test which determines whether the bounding box ~hown ~ ~2317~1~

def inod ~y ~h&~ proj~c~ios~ o~ ~n octr~e obiect r~ode in~l?IGURE 6(B) is~tersect3 a given quadtre~ winâow of the vi~r plzme;

FIGU~E 8 i~ ~ graphi~ illu~tr~tion of a projecl:ion o~ a nod~ wherein the si~t exterior edge~
and thre~ in~erior ~dges of the projection are numbered for the purpo~e of omparisons performed by a polygorl inter~ection test and an enclosux~ test, test~ which aid in determining wheth~r a projecti:on o~ an octree node intersects ~nd encloses a quadtree window, respectively;

~ IGURE 9 is a graphic illustration o~ the selection of c~itical vertice~ of a quadtre~ window for the polygon in~ersection test as a function of the slop~ and in~erior ori~ntation o~ edges of a node project~d onto the vi~w plane;

FIGURE: lG is a graphi~ illustration of the geom~try a~sociated with ~he polygon irltersection test, wherein the po~ition of each ex~erior edg of a node projec~ed onto ~he vies~ plane i~ ~ompared with the po~ition of ~n as~oci~ted cri~iczll ver~e~
of a quadtree window to de~ermine if the window in~er~ect~ the node projection;

~1179~ ~

~3 F~GURE 1~ ggalphic ~llu~t~a~iorl ol~ ~he et~on ~f ~r~t~c~l ~erti~ o~ ~ qu~atree ~in-30w ~or t~e ~nclc~ure te~ func~ion of 'eh~
and in~rior orien~atior~ e~ge~ of ~I no~
p~o~cte~ ~nto the v~ ~w pl~n~; ~Flg . 11 ls on sheet 7 w~th Figures 8 and 9 ) FIG;URE 12 i~ a gr~phic: illustra~ion o~ ~h~ ~s 9eo~etry ~s,s~clzlted with the ISnclosure t~, wh~rein the po~ition of e~ch edge o e~ch face o~ a node p~ t~d ~snto th~ v~ew pl~ne i~ co~pareæ with the po~itii~n of an ~s~ciat~d ~itic~l vertex o ~
quadtr~e window in order ts ~eter~ine 1~ ~h~ window i5 com~ tely enelo 2~1 by a f~ce o the no~e pro jection;

FIGtJRE 13 i~ ~ fun~ional block dia~r~m showinq the ~pplication of the r~sults o~ the ~ounding box ~e~t, th~ polygon int~r~ection t~t and ~h~ en~Lo~u~ ~est to genera~e ~ r~sult in~ eing whether ~ quædt~e window ir~t~r~ or 1~
ct~mpletely enclo~ed ~y ~ ~a~e o~ ~ node projecti~r.;

URE 14 ~A) i~ a gr~phic ~llus~r~tlon o~
tho~ port~on~ of Node 60 ~ho~dn ~n ~IGURE ~ ) which ~1~ w~t~l~a~ ~ r~gion de~ined by ~ p~ir o~ cut pl~ne~;

3179~ , FIG~R 14 ~ a qraphic illu~'cra~ion ol~
the geo~etry as~:iarced wi~ the cut plan~ te~
which deter~ln~s whether a nc~de i~ in~ide or ou~lde of the regic~n dof aned by &~ pai~ of cut planes and whe~her the node i~ interseeted by a cut plane;

FIt;URE 15 is a block diagram o a three-dimensional Solid Ob~es:t Image ~enera~or according to the present invention;

~ I~URE 16 i~ a graphical illustration of the ~onve~sion o input data to an octr~e tructure as performed ~y the Octree Dzlta Conversior~ block shown irl FIGURE 15;
-~ GURE 17 is a diagram of an octreestructure a~ ~tored in the Octree-Encoded Object Storage block shown in FIGUR~ 15;

FIGUR~S l~a) l8(~) show a flow ch~rt describing the function of the Image Display Proce3sor block ~hnwn in FIGUR 15;

PIGllRE 19 i~ a modi~ication of the ~lo~
chart Rhown in FIGURES 18lA)-18l~) showing t~e opera~iorl of the Image ~isplay Processor block shown 317~

in F~G;~E: 15 w~Aen th@ cu~ ~lane test i~ utili~d to produ~e 3~t ion~l im ag~

~ IGtlRE 20 ~ a graphic illustratiorl o the 3-dimen~ional o~tre~ universe pro~ected on~o the 2-dimensisnal ~uadtree univ~r~e for zl çliven view point defining ~he rela~ions~ip~ betweerl the two-dime~sional and three-dimensional ooordinate systems in accordanee wi~h ehe presen~c invenltion;

FIGURE: 20~E3] is a graphic illu~tration of the de~inition of ~che bounding box o~ the projes:tion of th~ root node;

FIGUR. 20~C1 is a graphic illustration of the definition of bounding box offse~s in the X
direc~ion, indicatlng the displaoement of ~he bounding boxe~ of ~he eight children node pro jection~ on the two-dimension~-l vi~wing plane fro~n the bounding box of theis parent node ~shown in ~IGURE 20 ~ 8 11;

FIG~JRE 21 (A~ i~ a graphic illustr~tion of nod~ edge off~et~ indicatang ~he displacem~nt of ~he W edg~ o each ~-hild node proje~tion ~rom th2 W

~ 2 3 1 7~

e~g~ of th~ ~are~t node project~on ~how~ ~n FIG~E
2olAa;

F~GURE 21~) is a g~aphic illu~tration o~
~ode edge off~e~s indic~ting the displa~emen~ of the Dl edge o~ each child node proi~c~io~ from the Dl edge of ~he parent node projection shown in ~IGURE
20(~;

FI~URE 21lC) i~ a graphic illustration of node edge off~e~s indicating the displacement of the D2 edge o~ each child node projectiQn rom ~he D2 edge of a parent node projection show~ in FTGURE
2Q~

FIGURE 21(D) is a graphic illustratio~ o~
of~sets o ~ae~ face edge of a child node pro jection parall~el to the D0 edge from th~ DO edge of tha~
child node p~ojection;

FIGURE 21(E) iB a graphic illustration o~
~he ofsets of @ach face edge ~f a chald node projec~ion pa~allel to ~he Dl @dge ~ro~ ~he Dl edg~
of that child node projection;

1 79~

~ IGUR~: 21~F~ i~ a graphic illustFa~io~ o 'che of~t~ of ~ach f~ce ed~ of a cllild no~e ~o~eceion ~r~llel ~o th~ D2 edge frolQ the ~i ~dge of thæt child nodæ projection;

FIGURE 22l~) is a graphic illus~ration of of~s~ts from a vertex of a par~nt node projection to the vertices of each ~hild node projection, the of ~sets shown needed for the cut plane t:~5'C, a test which deterlaine~ if a node lie~ in a region d~f in~d by ~ pair of parallel plan~:

~ I~;URE 22tB~ is a graphic illustr~tion of the measurem~nt of a dim~nsion of a node prs~jection f or u~e in the cut plane test;

- ~IGURE 23 (A) i a graphic illustration of offset!3 ~rom the origin o~ the ~uadtre~ universe ~o the critical vertex corners of a 4 x 4 window array ea~h ~in~low of whi-~h i~ the ~ize of the Display Screen, r~lative to the DO ~ D1 ~nd ~2 edge~ of the rooe: node projec~ion, and ~l~o ~e~ines the di~en~iorl~ o~ ~he ehildren windows in the ~ ~ 4 arr~y;

2~ 1?~3~ ~790 FIGUR~ 23(~ gr~phic illu~tration of of~ defi~in$ ~he displace~ent~ ~ro~ ~he ~rt~
defin~d relative to the ~0 ~dg~ of ~he roo~ n~d~
projoction ~hown in ~IGURE 23~A) to each o ~he other ~riti~l v~rti~es ~or ~he DO edge) of ~ given quadtree window ovcrlay;

FIGURE 23(C) is a graphic illustration of offse~ defining the displacQ~e~ts from the vertex defin@d relativ~ to the Dl ~dge of the root node projeceion ~hown in FIGURE 23(A~ to each o ~he other ~ritical vertices (for the Dl edge) ~Ç a given ~uadtre~ window overlay;

FIGURE 23(D) is a graphic illust~ation of offsets defining ~h~ displacements from the v~rtex defi~ed relative to ~he ~2 edge of the root node p~ojection ~how~ in FIGURE 23~A~ to each of the other critic~l vertic~s (or ~h~ D2 edg~) of a given ~uadtree window overlay;

FIGURE 23~E) i~ ~ graphic illustration of ofs~t~ between opposi~e v~rtices of a given gua~tre~ window rel~tive to e~ch o the DO, Dl and D2 edge~ o~ ~he root node proje~tion shown in FI~U~E
23(A3;

~-.'. ?~ 'V~ t ~3~
2~

FIGUR~5 ~4(A)-2~ how ~ 10~ ch~rt .
illu~tr~ting ~he function o the Ini~ zin9 Con~roll~r block ~ho~n in FI~URE 15;

~ IGUR~ 24(C) i~ a graphic illustration of the view plane shown in F1GUR~ S defined within its own thr~e-dimensional coordinate ~yste~, wherein one point on ~h~ view plane 1~ defined ~y ~ us~r for -locating the projection of th2 ~h~ee-dimensional universe onto the view pl~ne;

FIGURE 24~) i a graphical illus~ration of the thre~-dimension21 o~tree univer~e and the coordin~ate ~ystem which it defines, the coordinate ~ystem shown in FIGURE 24(C) defined by th~ view plane being ~perimposed onto the coordinate system de~ined by the three~dimensional universe, wherein a center of rot~tion about which the three-dimensional univer~e may be ~otat~d is defined by the user:

FIGU~E 2~E) is a graphi~al illustration of the thre~-dimensional universe shown in FIGURE 2~D~
~te~ it h~ been scaled by block 256 shown i~
~I ~R~ 24~A);

~3~9~

~ G~hE 24(~ a graphi~l illu~trAtion o thé sc~l~d ~hree-dimensional univer~ shown i~
FIG~R~ 24(E) wherein the origin of ~h~ coordina~Q
~y~te~ shown in FIGUR~ 24(C) defin~d by the view pl~ne iQ posi~ion~d at the ~en~er of ro~ation by block 258 of FIGURE 24(~);

~ IGURE 24lG) is a graphical illustration of the thr~e-dimensional univer~e translated as shown in FIGU~S 24(~) and rotated about its ~enter of rotation by blo~k 260 ~f ~IGURE 24(A):

FIGUR~ 24lH) is a graphical illustration o~
the three;di~ensional universe ro~ated as shown in F~GURE 2~lG~ and transla~ed by block 262 of FIGURE 24(A) so ~hat its cente~ o~ ro~ation corresponds to ~h~ user-speci~ied point on the view plane shown in ~I~VRE 24lC);

FIGURE 24~I) is a graphical illustration o~
the three-dimensional univer~e s~own in FIGURE 24 projec~ed onto the view plane by blook 264 of FIG~R~ 2~A~;

~L~33 l?Is;~EaE: 2q~J) i~ ~ graphic~l illu~t:ration of the ~ounding ~ox def in~d by ~he ~chreeodimen~io~lal uni~er~e ~hown in FIGU~: 24 ( I ) a~ locat~d by b~oek 268 of FIGURIE 2~

FIGURE 25 is a block diagram further de~ailing the Image ~isplay Proeessor blook shown in FIGURE 15, FIGu~aES 26l~)~26~) are a schematic diagram of the Me~ory Addre~s Processor blo~k ~hown in ~IGURE 25;

FIGURE 27 is a schematic diaqram of a gene~al Stark ~rchitec~ure used for the Memory Rddr~e~s Stack, ~che Ob ject Node Packet Stack, the Object Node Geom~try Stack~ e WBITS Stack; the Imag~ ~indow Pack@t Sta~k, the Isr~a~e Window GeoMetr~ he 13-~o~ E~esults Stack and ~he Cut Plane G~ometYy Stask ~hown in FIGURE 25;

FIGURE: 2~ a schema~ie diagram of l:he Objeet Node Packet Proce~sor block ~howrl in PI~UXE
25;

7~

F~B~E ~ h~ gr~ o t~
ob~ce ~d@ G~o~etry Proce~ lock ~hown 1~ FIC~
25;

FIGU~E 30 5~ hem~tic ~iagram of 'ch~
~aye ~in~low ~esllory block shown ;n PIGURE 25;
FIC~R~ 30 ~13) i3 ~ graphic illu~tration o~
pæ~t of ~h~ Di~play ~cr~en ~u~divid~l in~o windows a'c ~o~e ~rbitr~ry leV@l of ~h~ qu~dtree ~}~OWi~lg how !
the win~low~ ~g ~to~ed by the ~ntesle~vo~ ~rr~ys (A, nd D) ~hown ~n l~SG~E 30~A); (Fig. 30(B) is on sheet with Fig. 23E~

~ IGURES 3051:)o30(F~ 8hos~ the ~our pos~ible configurlltion~ o a given winflow over1~y ~ith re~pect to thc inter1~ve~1 Arr2lys (A) E3p C, 1~ hown in FIGUE~: 3a (A), FIGURE 31(A) ~ a ~Ch~tic di~gra~ the ~dtr~!e ~ddr~ss ~p ~hown in FIGU~E 3C~A~;

~ ICU~E 3l ~ a ~ch~mati~ ~iagr~m of one of the s~ur ~rr~y~ ~A, E~, C ~na D) ~hown in ~IeURE
3~ )1~);

~ IGURE 32 i~ ~ ~ch~e~tic diagr~ of t1he Ouad~ree ~1~ck ~l~ hown in FIGURE 30 ~3;

l ~3 l 7~b FIGUR~ 33 is a ~hemat~s: diagram of 1:he Qua~tr~ Clear ~ddre~ nera~o~ bls~ck ~hown in FIGllRE 30 (A);

FIGU~E 34 ~A~ is ~ ~hematie diagram of the Data ~ead Map shown in ~IGI~E 30 (A);

FIGURE 34(~3~ is a ~chematic diagram of the Data Write l~ap shown in FIGURl: 30lA~;

F~GUR~ 35 is a sch2~tic diagram of the Image Window Pa~ket ~?rocessor block shown in FYGURE
2 5 ;

FI~;URE 36 (A) i~ a ~chemati~: diagrarn of the t:hild Modiy ~ogi~ shown in FIGURE 35:

~ IGURE 36~ is a scheA~ic dia~ram of the Grandparent Modify Logic ~hown in FIGURE 35;

~ IGURE 37 i~ a schematic diagram of the P~rellt Redut:tion LogiE shown in ~IG;URE 36~

FIGI~RE 31EI i~ a ~chematic diagram of ~he Image Window Geometry Proc~s~or block ~hown in PIGUR 25;

1 ~3 ~ 7~1 FI~:~RE5 39(A) and 39~J ~ho~ ~ ~chelæatic dia~r~ of ~he Window Overlay Sel~c~ Logi~ block ~hown in ~Ie~ 25;
FIGVR~: 4û i~ ~ ~chematic diagram o~ the lNindow ~el~et I,ogis block shown in FIGURE ~5;

FIGURE 41 i~ a ~chema~ic diagram of the Cut Plane Processor block ~hown in ~IGUP~E 25;

FIGU~E 42 i~ ~ schematic di~gram of the Cycle Result~ block shown in ~IGU~}: 25;

FIG~RE 43 (A) is a ~rap~ic illustration of a 4 x 3. window array such that the ~iZ~? of a quadtree s~indo~r is equal to that of éhe Display Screen, one of the situa~cions in which 'che Scre~n Inter~e~tion Logic block of FIGUR~ 42 i5 used to perform the screen inters~ction te~t in li~u of the ~BOX ~est:

~ IGURE 435E3~ is a sch*mati~ diagram of the Screen Intersection Logic block shswn in FI~URE 42;

~ IGURE 44~A) is ~ block diagram o a Window Loca~on ~ogic block, one of the component~ o ~he B~OX Arithmetic block shown in FIGURE 42;

3~7~

~ I~uEaEs ~4(~3 i~ ~ ~ch~ma~ic di3gra~ Oe a por~ion of ~he ~0$ ~ ic 13loek ~hown in ~ E
42 ~hich perform~ th~ ~BOX ~t on one of th~ l~our ~indow~ in ~ window sverlsy;

FIG~RE 45 i~ a ~chematic diagram of the ~oly5~on In~er~ection Arit}lmetic block ~hown in FIGURE 4 2;

FIGU~E ~6 i~ ~ chematio diagram o a one o th~ Face Arithmetic block ~hown in FIGURE 42 ( used to per f orm ~h~ ~ te~t on one of the three ~aces o~ ~ node pro~ec~ion~;

FIGURES 47(A) and iB~ are a schematic diagram o~ the Nindow Writer block shown in FIGUR~
2~;

FIWRE 48 is a ~tatE diagram illustrating ~h~ . unc~ional opera~ion o the Sequence Controller block ~hown in FIGURE 25; ænd FIGURE 49 i~ a sch~matio diagram o the Sequ~llce Controller block ~hown in FIGURE ~S.

3179~

~ he hierarchical organization of th~ three-di~ensional univer~e and its repre~entation by an oc~ree ~ructur~, and ~he hierarchical srganization Gf th~ two-dimensional univers~ and its represen-~ation ~y ~ quadtr~e stru~ture will first be ae~eribed. The proce~s of pro~ecting objects defined by th~ octre~ structure onto the two-dimen~ional vi~w plane and testin~ windows o~ th~
view plane ~or inter~ection and en.lo3ur~ with the projection using th~ eonstructs o~ ~ bounding box and a window overlay will then b~ described. Nex~
descri~ed will be ~he cut plane test, ~hich allows sec~ional views to be ~enerat~d.
Next d~ccribed will be a func ional repres2n~ation of the pref~rred embodiment of ~he present invention. The Octree Data Conversion and Initializin~ Controll~r blocks of the unc~ional repr~3entation will be di~cuss~d in detail. The r~maind~r of th~ disclosure will describe in detail the algorithm performed by the I~age Display ~roc~330r block of th~ func~ional representation (t~ portion of the pre~ntly preferred embodiment which a~tually generate~ an image) 9 and th~
archite~tur~ and op~ration of the Image Display 12~7~ ~

Pro~ or as it i~ impl~ment~d in the pre~ntly pre~rr~ exemplary embodi~ent o th~ pr~sent inv~nl: lon .

ORe~NIZATION OF ~E 3;DIMENS~ON~L

Referring to FIGURE l~A), shown is an ~rbitrary 3-dimen~ional obj~c~ 30 def~ned within a 3-dimensional universe 32. A parallelepiped has been cho~en to define univers~ 32 in order to ~i~pl~y ~he ~athemati~al ascertainment of ~he position o~ the ob~e t 30 within universe 32. The preferred embodiment only generates image~ of object~ or portion~ of objects within univer~e 32, ignoring any ob~ects not withln the universe.
. Referrin~ to ~IGUR l(B), universe 32 is su~d-ivi~ed in~o eight ~all~r parallelepipeds of identic~l ~ize, ~hape ~nd orientation Ithe "child"
parallelepiped~ of th~ universe)0 ~n object 30 contain~d ~y univer~e 32 will be ~ontained ~y one or mor~ o the child par~ lepiped~ (here, ~y child p~r~llelepipeds 34 and 36J. Obje~t 30 need not b~ a ~inqle ~on~inuous object, but ~ay rather be æn assembly of multiple di join~ part~.

1 ~ ~ 1 790 J

33~

Re~rrin~ to ~IGURES l(C) and 1~), child node~ 3~ and 36 eac:h h~ve b~en fùrther i~ut~divis3~d into th~ eight children parall~lepipedq. ~hu~, the ~hildren parallelepiped~ of nodes 34 and 36 are the qrandchildr~n o~ univ~r~e 32. Objec~ 30 completely encloses child para~lelepiped 38 o parallelepi~ed 3~ and ~hild parallelepiped~ 40 and 42 o parallelepiped 36. ~y subdividing universe 32 recursiv~ly, it i~ possibl~ to determine the exact po ition and dimen~ion~ o~ ~ny arbitrary object 30 wathin univ~r~e 32 ~y determining all o~ ~he descende~t parallelepip~ds of the universe 32 which are completely filled by the object. The resolution in the dQtermination o~ the posi~ion o object 30 wi~hin univer~e ~2 is thu~ limi~ed only by the number of subdivision~ of the univers~ that are recur.~ively performed.
A parallelepiped at any given level may have one of ~hres rel~tion~hips.(~property values") w;th r~pect to object 30 indicating the degree to which it is o~cupied by ~he obje~t. A
parallelepiped may be empty IE~, where it ~nd the ob~ect ~re completely di~joint, (as, for example p~rallel~piped 35): it may be full (F), ~eaning tha~
~ completQly containe~ by the objec~ (a~ are parallelepipeds 38, 40 ~nd 42); and finallyO it may --` 1~179~

be p~rti~ aning that it con~ains ~om@ p~r~
of the object ~u~ i~ not completely con~ain~d by ~he object 1~-9. pa~allelepipe~ 34 and 36).
I~ a given parallelepiped i~ E (empty), all of the children o that parallelepiped will also be E. Likewi~, if a given parallelepiped i~ F (full~, all of i~s children must al50 be F. Finally, if a given parallelepiped i5 P (partial), some of its descenden~ ~ust be F ant ome ~u~t b~ E (depending upon the subdivision at which th~se ~ and E
descenden~s occur, ~om* or many of the descend~n~s o~ a P parallelepiped ~ay also be P)O Thus, a P
parall~lepipe~ must have at leas~ on~ non-EMPTY (P
or F3 ~hild but not all F ehildren.
~ eferring ~o ~IGURE 2, chown is an octree structure rep~esenting the three-dimensional space shown in F~GURES l(A)-lID3. The structure shown is a "tree" structure organi~ed hierarchically into an arbitrary number of levels of "nodes" (three levels are shown, beginning wi~h level 0, i.e. the Nroo~
node~ ach successive level representing, ts a high~r lev~l of preci~i~n~ ~he ~ame ~pace as the lev~l above i~. ~Oc~ree" denotQ~ that each node is subdis~d~d into eight children nodes. I ~ node i~

subdivided in~o its eight children nodes, it i5 ~ 1 ~3 1 79~

~o called a ~br~nch noden; nodles not ~ubdivid~d ~re cal~ l aleaf node~ or "terminal nodesn.
The root node represents ~h@ en~ir~
univor~ 3~ o ~IGURE l~A~. Ea~h node ~t any lower level in the octree ~tru~ture rspresent~ orle of the disjoint ~eqment~ of space defined by ~he subdivi-sion of universe 32 shown in FIGURE5 ltE~)-l(D).
Referring ~o FIGURES l(A)-l(D) and 2, root node 32a rQpres~n~ uriverse 32 7 while each of th~ eight level 1 nodes represent one of the eight children parallelepipeds of univers~ 32 ( thus, level represents the level of ~ubdivision shown ira l?IGURE
1~3); node 3~a represent~ par~llelepiped 34, node 35a repres~nts parallelepiped 35, etc. ) . Likewise, ~ch o~ the level 2 nodes in the oc'cre~ repre~ents one of the eight grand~hildren parallelepipeds shown in FIGURES llC~ and l(D). There are 8 po~sible node at level 1, 64 pos~ible node~ at level 2 and 8n po~sible nod~ at level n.
Referring to P~IGIJRES l~A) llD) and 2t each node in the oetree ~tructure has a sociated with it a proper~y value corr~sponding to the rela~ionship b~e~n ~he parallelepiped in three-dimes~ional ~pace ~hich it represent~ and the object 30, as discus~e~ above. Thus, a node is marked E: lf the parallelepiped which it represents is Empty, marked ` 123~79l~

he p~rallelepiped which it repre~ent~ ull, ~nd ~ark~d ~ if th~ p~rallelepiped which i~ .
r~pre~nt~ i~ only p3r~ally f illed ~y the o~ ject 30. As shown, all ~u~ ~wo of th~ lev~1 1 nodes have been mark~d E because they represen~c empty parallelepipeds sbown in FIGURE l(B) (for example, node 35a repre~ents emp'cy parallelepiped 35 ~ .
Likewi~e, the level 2 (grandchildr~n~ nodes ~8a, 40 and 42a h~ve been marked F because the parallelepip~ds in universe 32 to which these nodes corre~pDnd (parallelepipeds 38, 40 and 42, respectiv~ly) ~re completely conSained by object 30. Since none o~ the oth~r level 2 nodes represen~
paralle`~ epiped~ cont~ining any part o~ ob~ee~ 30, they 2~ave all been ~arked ~;QTY. The parent node 34 sf node 38 and ~he par~nt node 36 of nodes 40 and 42 have both been marked PMTI.9~ becau~e they each have a~c leasi~: on~ non EMPTY child bu~ all of their childr~n are not FULL. Likewise, root node 32 has been m~rked ~A~TIAL .
A~ ~entioned previously, an a~bitrary nu~b~r of ~ubdivi ions of n~de~ partially filled by an object may be r~quired to locate de~cenderlt nodes which ~re completely conta;ned by an obje~t.
}~owever, ter~in~l ~ EMPTY ~nd ~ULL ) nodes need not be subdivided in order to determine the prop~rties c~

1 ~ 3 ~ 7 9~1 ~2 ~heir ~e~cendent nod~ lall EMPTY ~nd all FV~L, ~spec~ively). ~h~s, t~e o~tree structure ~how~ ~n ~IGURE 2 haa been ~rimmed~ or ~pruned", ~eaning ~hat only the ~ubdivisions for PARTIA~ nodes have been ret~ined in the ~tructure. Gr~at increases in efficiency and sa~ings in hardware resul~ from the "tri~ming" of the octree, as will 500n be apparent.
It will b* understood by those skilled in ~he art that ~ three-di~ensional object o~ arbitrary complexity and shape may be represented by an octree ~tru~ture o the type shown in FI~URE 2. ~oreover, the degre~ of resolution of the representation may be incrc~sed by slmply addin~ more levels to the octree stru~ture.
Referring o FIGURE 3(A), shown i5 a 2-dimensional view plane 66 defined by a rectangle, suitably a square. (It will be understood by those skilled ln the art that any primitive geometric shape could be used)~ View plane 66 (also referred to as ~he 2-dimensional universe) is subdivided into four square children ~window~ ~2, 54, 56 ~nd 5~, all of identic21 size and orientat;on. Th~ e children windows c~n ~e ~ur~her subdivided into the~ ~our ~hildren window~ which in turn ~ay ~e fur~her recursively ~u~divided. This hierar~hic~l ~2~7~

organiza~ioa~ of th~ vi~w plan~ ilar ~:o that di~clo~d in Warnock, di~cu~d previou~ly.
So~ne of the ~indow~ of view plane 66 are shown a'paint@d", m~anin~ that they are ~ompl~t@ly f illed by an i~age being di~;played on view plane 66. ~ window may eil:her be ~ull liOe~ "painted"), Emp~y, or ~artial (meaning tha~ so~, but s~ot all of the de~cendent~ of that window are Full ~ .
Ref~rrirJg to ~IGURE 3(~ nquadtree"
structure representi~g ~ch* ~wo-dimen~ional ~iew plane 66 shown in ~IGURE 3lA) i5 shown. It will be apparent that the quadtree structur~ of FIGURE 3~B~
i5 analogou~ to the octr~ structur~ of FIGURE 2 except that each parent wirdow is subdivid~d into only ~our (not eigh~ children q~indows (because window~ in view plane 6~ are subdivided into four rather than eight children). Each window in ~he quadtree struc:ture analogou~ly h~s as~ociated with it a prop@r~y valuQ of ei~her EMPT~ (E), PARTIAI (P) c~r ~ULI. (~), depending upon ~he relationship between ~he window and th~ image b~ing di$played on view pl~ne 66.
Note that the quadtree i~ comprised of "nod~ representing two-dimen onal window~ ~U5~ as the oc ree i~ compris@d of ncdes representing three-di~ensional parall~lepiped~. Quadtree "nodes" will 7 ~ i3 . , .

~4 ~e r~f@rr~d to as ~window~ ~o ~void confu~ion.
~ikewi3e, the three-di~en~ion~1 parallel~piped~ in the three-dimensional univer~ which octree node3 represent will al 50 be ~eerr~d to as "nodes~ ~or the ~ake o~ simplicity, although it should be reMembered ~ha~ a node is an ~ntry in the oc~ree struc~ure r~pr~sen~ing a parall~lepiped in th~
thr~-di~eneional universe~

~IDDEN SUR~ACE REMOVAL AND
T~AVE~SAL OF THE OCTREE

Referring ~o ~IGURE ~(A), the octree traver~l sequence for the eight children of an arbitrary parall~lepiped descendent 6~ of three-dimensional universe 32 Eor a predetermined viewing a~gle i~ shown. It will be understood that for any given vi~wing a~gle, an object contained in some of the children node~ may ob~truct th~ view of differ-~nt obiects ~or p~rts of the ~am~ object) contained in others of the children node~. For instance, for the v~wing ansl~ sho~n, on@ o the children nodes (nod~ 0) canno~ b~ se~n at all bec3us~ it i~ ~
ob~tru~ted by the other nodes. For the viewing angle shown, child node 7 is "closest" to the vi~wer, ~o ~h~t an object ~ont~ined in child node 7 7~1 w~ll not ~e obstruct~d by ~ny of thc vther ~hildren no~
~ he octree traver~al ~equ~n~e, i.e. ~h~
order in which the eight children nodes o a giv~n parent node ih t~e octr~e ~tructure are visited, ~u~t conform to the way in which some of the repres~nted parall~l~p~peds ob~truct others if a realistic three-dimensional image which doe~n't show hidden ~urfaces i~ to be gen~rated. ~or the viewing angle shown, nod~ 7 i~ vi ited first, node 6 i~
visited next~ etc., and node O i~ visited last (a 7-to-O tra~ersal seguen~e). A sequence which visits nodes such tha~ no node later in ~he sequence can obstruct the view o~ a nod~ earli~r in the sequence i~ call~d ~ "front-to-back~ ~ansver.al ~equence.
The order of ~ome of the variou~ nodes in the traver~al sequence will b~ arbitrary for a given view ~oint ~for instance, for the viewing ~ngl~
shown, it does not ~atter whether node 3 is visited be~ore node 6 or ~te~ it3, As the viewing ~ngl~ changes, the traversal sequence m~y change. For instance, if the node ~hown in F~ W RE 4~A) we~e ro~ated lBO about each o~
the xv y and z axes~ the view of child node 7 would be ob~ru~ted ~ompletely and node O (no~ shown) would be ~he first node in the ~raversal ~equen~e.

-`-~ 3~31~

.

tolt~l Q~ 8 ~uch seguenc:es ar~ needed, corre~
g to the 8 oc~ants of the thr~e dim~n~iQn~l univer~e in which ~he observer may be looa~ed ( 'ch~
eight "viewing o~tants" 3 . The presently preferred embodiment of the present invention uses the tr~ve~al sequence ~or ~he viewing ~ngle shown in FIGURE 4~A) to number and process each of the ~hildren node~ of a pa~en~ node. The hardware translates the node visited in this traversal sequenc2 a~ a function o viewing angle.
PIGURE 4 ~B) show~ an ob~ec~c 62 de~ined wi~hin ~he paren~ nod* shown i.n ~GURE 4l~).
Referring to FIGU~E 4(C), shown is the parent node of FIGURE 4tE~) subdivided into d~scendent slodes in order to i~olate th~ position o~ ob~ec~ 62 within the parent node 60. Thus, child node 7 of node 60 is ~ubdivided into its eight children, each of which is labeled according to the 7 to-û traversal sequence shown in FIGURE 4 ~ 7 5, ~ -, 5 ' ~ 4 " 3 ' 2', 1' and 0' (not ~hown)3. Lilcewi~e~ node 7' is fllrther subdivided into it~ eight children, ~ach o hich i~ al~o numbered according to the 7-t~0 t~av~r~l a2quen~e. Objeet 62 is ~ontiguow with node 7W, (the great-grandchild nod~ of node 60)., A5 di~cu3sed previou . ly, a node containing an obj~ct (or part o6 an object) may obstruct the 3 ~J7~1D

? ~7 ~iew o~ no~e~ cont~ining ~nother obj~ct ~o~ ano~her part of the ~ame obJect) ~or a given vie~ing ~ngle. Of cour~e, E nodes will not ob~ruct any other nodes. ~ikewis~, it can be determined with certainty which nodes ~r~ obstructed by a ~ nod~. A
P node, however, ~u~t be further ~ubdivided into the E and ~ nodes whi~h comprise i~ in order to determine with certainty which node~ it obstructs.
T~u~, unless t~e first ~ild node in ~he traversal sequ~nce is E sr Ft i~ i~ neces ary to subdivide that child node in order to det~rmine which nodes in the three-di~ensional univ~se it obstructs.
For this re~sonO th~ octree structure is traversed by comPletel~ procsssing ~i.e.
~ubdividing~ nodes occurring @arlier in ~he 7-to-0 traversal sequence ~and the des~endents of those nodes3 ~efore visiting late~ nodes in the trave~sal sequence. ~ence, node 7n of FIGUR~ 4(C) is visited before, for exa~ple, node 6n~ node 6', node 6, any ~siblings~ (i.e. nodes havang a common parent~ of node 60 occurring later in the 7-to-0 traversal sequence than node 60 or any siblings o the Wancestors" of node 60 whi~h occur later in ~he traver~al ~equence than those ancestors.

Thi~ "depth-~ir~t" tr~v~rsal of the octree strueture ti~e. traversal of the octree downward `` 1 2 ~

~1~

fro~ p~rent 'co child, and re~ rning to th~ pare~l:
only ~hen ~11 of it~ d~cendent~ have ~eer proce~sed) i~ uti~Lize~d by the pre~f!n~cly pre~rred embodiment of ~he pre~ent invention beGau~e it p~rf~ hidden ~urfaee removal whil~ the image i5 being gerl~rated. Other trav~r~al schemes ~f the octree ~such as Hbreadth-~irst" traversal, where an entire ootree level is processed before the next level down i5 visited, or a hybrid of l'depth-first"
and "breadth~first'^ traversal~3 might be ~ui~able for the generation of images other than realistic 3-dimensional imag~s r~quiring hidden surfa~e removal, where the octree was defin~d âifferently, or where constraints w~r~ placed upon t:he structure o~ the ~b je~t being imaged. Xowever, as will b~ explained later, this "depth-f irst" traversal sequens~ is also utilized by the presently preferred embodimen~ ~o prevent quadtric: groweh ~f the calcula~ions required for image generatioll.
Those skilled in the art will recog~ize that a "back-to-fron n ~ravers~l 3e~uence could be used instead of the ~front-to-b~ck~ sequence. If a "ba~k-to-front" ~raver~al sequence is used, hidden surface removal i~ accomplished by "overpainting~
portions of the ~bject by sther obstructing portions of the object visited later in the back---- I 2317~

~o~ront traver~ e~uence. A3 will beco~e appar~ a ~rs~-to-back tr~ver al ~e~uenc~ i~ far more ~fici~nt ~ince whole ~ubtree~ o ~h~ oct~ee ~truceure may not h~ve to be proe~ssed. ~owever, a back-to-ron~ traver al ~equence of ~he octree structure ~ight be warranted for particular applications or implementations.

The Pro-ection of_the Thre~-Dimen~ional Unl~ erse onto the Two-Dimensional View-~rane Referring to ~IGURE 5, shown i a parallelepiped 64 of the three-dimensional univ~rse repre~ented by an ~ node in the octree tructure proie~ted on~o 2-dimen~ional view plane 66. The projection 68 of parallelepipgd 64 onto view plane 66 in the general case will b~ a 2-dimensional polygorl with six exterior edges 68a, 68b, 68~, 68d, 68e and 68f. It will be understood tha~ just as a maximum of three fac~s of 3-dimensional parallel~-piped 64 may be seen from any given viewing angle, a maxi~um o three face~ of the parallelepiped will be projected on~o view plane 66 for any given viewing angle ~of cour~e, if t~e viewing 3ngle i~ ~u~h that only one or two ~ace3 of parallelpiped 6~ may be seen, then only one or two faces, respectively, o 2~179~

~o obj~c~ ~ode 64 will ~e p~oj*et~d on~o Yiew plan~ 66, and th~ proje~tion 6a will be a four-3id~d polygon~0 ~ h~ ided polygon projection 6~ of parall@lepip~d 64 on~o vi~w plane 66 in ~he g@neral case c~n also be regasded a~ the projection of three fac~s of a parallel~piped, ea~h of which is separat-ed by an edge internal to the projection. Referring to FIGURE 6(A), each of the three visible aoes of parallelepiped 64 are projec~ed as a four-sided polygon in the projec~ion 68. Thus, faces number lf 2 an~ 3 larbitrarily numbered) of ~he object node appear as faces 70, 71 ~nd 72 in projec~ion 68.

~eferring o FIGUR~ 6~), shown is a -"bounding box~ 74 defined by th~ node p~oj*ction 68 shown in FIGURE 6(A). ~ounding Box 74 is defined as the ~mallest rectangle of predetermined orientation (i.e. having edges parallel to th~ view plane coordinate ~xe~, not shown) which comple~ely ~on~ains node projec~ion 68. (Note that bounding box 74 nee~ not be ~quare, and in general will not ~) T~e origin 76 of bounding box 74 i5 arbitrarily defin~ed to be the lower lef~-hand corner o the bounding box.

1 79~

Ref~rriR~ to FIGuaE ~(c)~ a window overlay 78 i~ ~up~rimpo~d on node proj~ction 68 and the ~ounding ~ox 74 which it de~ine~. Window o~rlay 78 comp~ises ~our ~ontiguou~ windows 78~0)~ 78(1), 78(2) and 78(3) of equal 5ize (iOe- at ~he same level of th~ quadtree shown in FIGURE 3(B)).
Because windows of ~he view plane exist o~ly in fixed and discrete sizes and locations (the length of an edg~ of a window at level n equals the len~th of the edge o~ the view plane/2~, it will not be possible in ~h~ general case ~o find a single window which encloses bounding box ~4. Becaus~ the bonding box is randomly loc~tedi it often lies on window edges, intersecting multiple wandows. For this reason, window overlay 78 i~ deined a~ tha~
set of four contiguous windows at the 3.owest common level of the guadtree stru;:ture whioh is ju~ lar~e enough to comple~ely contain bo~nding box 74 regard-l~ss o~ ies location (so tha~ ~ SQt of four windows of common Si2~ of the ne~t level of subdivision o~
~he view plane will be ~oo s~ o ~ompletely contain the bounding box in all cases). Thi~
impli~ th~t ach of the four w;ndows in th~ window ov~rl~y ~u~t be the same size as or larger th~n bounding box 74.

7~

~2 Giv~n thi~ deini~ion of window ov~rlay 78, ~ 30unding box 74 ~o~ ~ny nod~ 6B will be enclo~d by ~t l~a~t one window o~erlay 78 of four con~guous window~ all sel~c~ed ro~ the same level of the quadtree ~ructure. A given bounding box 74 will u~ually be enclosed by only one window overl~y.
~ow@v~r; some ~ounding boxes may b~ enclosed by more ~han one window overlay, depending upon ~he orienta~ion of the ~ounding boY on the view plane (for in~tance, a boundi~g box that a~ completely enclosed by a single window will b~ ~nclos~d by four different window overlays, each containing that window). In such cases, any one of the enclosing window overlays may be arbitrarlly selected.
Obviously; if' ~ode 68 ic subdivided into its eight children nodesJ the projection of each child node will also be contained somewhere within the sel~c~ed window overlay 78, as will be the bo~nding box of each child node. ~lthough not immedia~ely apparent, ~ue to the symme~ry between node and window geometries, ~he bounding box de~ined by any one o the eight children node projections will b~ enclo~ed by a contiguous window overlay ~electe~ f~o~ the sixteen child window~ obt~in~d when each of windows 78(0)-7~(3) is subdiviJ~ into its our children.

'3 1 7 ~

rn other wo~d~, when ~he quad~r~ ~tructur~2 i~ tr~versed one lev~l down to ~ubdivide al wandow overl~y o~ a given node projeotion in~co a 4 a~ 4 ~indow array (co~E~oscd of four famili2s o four children eac~l~, the window overlay of e~ch o~ the eigh~ child node projec~ions of the given node proj~ction (i.a. 'che four contiguous windows just larg~ enough to ~o~pletely contain the bounding box of that ~hild node projection~ ~y be sel~c~ed from thaS 4 x a~ window arr~y. Of sourse, di~eren~
window overlays ~ay and in the general case will be selec~ed for diff~rent child node proj~ctions.
Moreover, th~ our windows co~nposing the window overlay need not be childr~a of the same parent window (windo~s 78(O) 78(3)1, although th~ four window~ must be contiguou~ (i.e. "neighbors").
Thu~, once the window ovexlay ~or a given node projeotion i~ located, both the quadtree and the oc'cree s'cructure~ ~y be subdivided tog~h~r to loc~te the window overlay for ~he children of the given nodeO EIence, only a downw~rd ~a3 opposed to later~l ) traver~al of the quad~r~ struc~ure is l~e e . ~ary to locate the window overl~y o~ ~ny of the de~cen~ent node E~roj~c'cions of a given nod~ o-lce the window overlay for that given node is located.
~inally, i ~he window overlay of ~ny given node 32317~

~ .

p~o~ect30n i~ always loGate~ b~fo~e ~he quadtre~
~tru~ture i~ Srav~rsed downward and the quadtr~e is only ~raver~e~ downward on~ level a~ a ti~e, then any quadtree subdivision will be a ~ubdivision of a window ov~rlay into a 4 x 4 window array. Thus, only a s~all number of windows need ever be kept track of ~ny one time, and downward trav~rsal of the quadtr~e structure results in only a linear growth in the nu~ber of windows which need be ~anipulated at ~ giv~n time. This fea~ure is extsemely importa~t to the ~p~ed and efficiency of ~he preferrea embodiment, as will soon be apparent.
When a subdivision of a node and a window occurs, the presen~ly preferret embodimen~ of the present inv~ntion selects on~ child node projection at a time lfrom the eight children nodes resulting fro~ the octree subdivision), selects ~he window overlay or that child node pro~ection ~from the 4 ~ 4 window array resulting from the quadtree subdivision)~ and proceeds ts ~process" each of the ou~ windo~s in the window overlay individually in a mann~r ~hat will be explained hereafter. The s~lec~i~n of any given window overlay frQm ~h~ 4 x 4 window ar~ay may suitably be encoded into a 6~bit value, a3 is shown in FIGURES 6~D)-6~F) (it will be under~tood ~y th~se skilled in the art that other 3 1 7 9 ~

encodin~ ~cheme~ u~ing even few~s }~it~ a~e ibl~).
P~eferring ~o PIGURE 6(D) ~ th~ pre~rred e~bo~i~en'c of the presen~ inv~n~ion 3el~ct. rom the 4 x 4 arr~y (16 windows) the one of four pos~ible 3 x 3 array~ within the 4 x 4 ~rray which cortains the bounding box of the child node p~ojection. The variable W3x3X is ~et to logic level U if the ~el~cted 3 x 3 array ~ontains any windows ~o the left of line a and i set to logic level 1 if the selected 3 x 3 array i~ entirely t9 the right of line a. Likewi~e, ~h~ variable W3x3Y is set to logic level 0 if the selected 3 x 3 array contains any windows below line b, and is set to logic level 1 if the sele~ted 3 x 3 array is en~/:irely above line b.
Re~erring to PIGURE 6lE), the preferred embodim~nt ne~t selects one window overlay contaiDing the child node projection from the four possible 2 x 2 win~ow array~ corltained within the 3 x 3 window array selected in FIG~RE 6lC). The v~riable W2x2X i~ set to lagic level 0 if the sele~ted window ove~lay conta3n~ any window~ l:o t31e left of line c, ~nd is ~et to logic level 1 if ~he s~lec~ed window overlay is entirely to the right of lin~ c. Likewise, the variable ~2x2Y i5 set to 1 2 3 1 7~

5~

loqic le!vel O il~ t~ olected Idind~ ~veslay contain~ any windo~ b21c~w lis~e d, ar~d i~ ~et to logic lev~l 1 if ~he sele~ted window overlay i&~
entirely ~bove line d~
Onc~ the preferred embodiment of the ~re~ent inven~ion ha~ c~lected a window overlay from the ~ x 4 ~indow array (the sele~tion beir,g encoded in the varia~les W3x3X, W3x3Y, W2x2X and W2x2Y, collec~ively refe~red to as the WBITS~, sin~le Wil'l~OW5 ~ay be selected from the window overlay by a 2-bit variable ~l~q. A suitable enco~i ng of WNUM is shown in FIt;~ 6(F3 (while any numbering conv~ntion would be suitable, the presently preferred embodim~nt of ~he pre~ent inven~ion ~mploys a numbering ~y~te~ wherein the lower left-hand window is numb@ted window O ( 00 ), the lower right-hand window is numbered window 1 ( 01 ), the upper lef t-hand window i5 numberea window 2 ( 10 ) and the upper right-hand window i~ numbered window 3 ~11) ) . In "proce~ing" any family o~ four children window~, th~ n~bering convention is used as a "traversal se~uence" to determine 'che order in whieh the window~ ~re process~d~

~ 3~317~

~Ar~ ~ T ~ C~

.
The objec~ of the pr~erred embodimen~
according ~o the present invention i~ to locat~ and paint ~i.e. sh~d~ a ~orresponding ~rea of an Image ~i3play) all ~indows of ~he view plane which are oompletely enclosed by projections of ~ nodes o the octr~e (i.e. ~hose nodes which repres@nt parallele-piped~ which are completely enclosed by an object defined within the 3-dimensional universe).
Assuminq tha~ node projection 68 shown in FIGU~E

6(C~ i th~ pro~ection of an ~ node, it is necessary to determine which, if any, o the four windows of window oYerlay 78 are comple~ely enclosed by the projection. I any of the windows are completely enclosed, ~hose windows will be painted; however, i~
one or ~ore o~ those windows are only ~artiall~
enclos~d by projectio~ 68, the windows tha~ are partially e~closed will be ~urther subdivided in order to locate co~ple~ely ~nclosed windowsO
~Windows disjoint wi~h ~he projection are not paint~d, of ~our~e~
~ or re~sons of ~f~i~iency ~ . in order to quickly el;~inat2 tho e windows which ar~ no~
enelosed by a nodl~ proj~ction a~ will be further explained later), the pres@ntly preferred embodiment 123179~

~8 t~t3 ~h ~in~c3w in the windo~ overlay to dæt~r~ine lf ie i~3 co~pl@tely enclose~ Dy Zl no~e proj~ction by te~ting i~ in ~uc~ssion by ~hr~ independen~
t~stss the! bounding box te~t (BBOX ~t) 9 the polygon inter~ection tes'c (Pl t~st) ~nd the enclosure test (E t~st). The resu}ts o~ these tests indiGat~ whe~her the wir.~ow in~ersects or i5 enclosed by the node proj~tion.

THE ~OUNDING BOX TEST

~ eferring to FIGURE ~, shown is 'che geometry ~ssociated with the $irst of the three test~ ~entioned above 9 the ~BOX test . Node projection 68 ana ~che boundinl3 ~x 74 which it defines is located at an arbi~rary poin~ on the view plane; the origin 76 o~ the bounding ~ox 7~ is suitably define~ as (NPX + ax, NPY + ~y)O The dimension of bounding box 74 in the x' direction ti.e~ the Width) i~ ~uitably defined as bx, while th~ dimension of the bounding box in th~ y ' direction (iolD~ th~ height) i ~uit~bly defined as by. Thus, 'che four edg~s of bounding box 7~ deine l:h~ llnes 23PX + ax, NPX ~ ax + bx, NPY ~ y and NPY
+ ay ~ 'ay. No~e that the former two lin~ are bo'ch parallel lto ~ y' axis of the view plane, s~?hile the i23179~

latt~r 'cwo line~ are parall~l to aln x' ~xi~ o~ the vi~w pl~n~ (on~e of the con~rain~ o~ ~he definition of tn2 bounding box)~
A window 7853~ with origin (Wx~ Wy) and dim2nsion e (since all window~ ar~ square, their dimension3 in x' and y' ~re equal~ is shown. Window 7813) is suitably selected from the window ov~rlay 73 of node projection 68 shown in ~IGURE 6~C) (the particular window ~ele~ted here i~ the upper right-hand window of l:hat overlay~. The our edges of window 78(3) define th~ lines Wx, ~x I e, ~y and ~y e.
The object of the ~ounding box ~est is to determine whethe~ the bounding box def ined by the node projection under te~t is in~ersec~d by one or more of th~ four windows of ov~rlay 78 defined by that node projection. To determine thi5, the position o ea~h of the four edges of each o the windos~s in overlay 78 i5 compared ~o the position of a cQrr@sponding one o the edge~ of bounding box 74, as follows:

Is the bottom edge 80a of window 7û ( 3 ) lower tAan the top edge 80b of boundin~ box 74?

~ i~3~79~

6~ ' I~ ~he l:op edçle ~2~ o window 7~ ( 3 3 tharl the bo~cto~ edge 82b of bounding ~o~t 74 I~ the lef t edge 84a o~ window 78 ( ~ ) tc~ ~che lef~ of right edge 84b of bounding box 74~

Is the right edge 86a of window 78(3) to ~he ri~ht of lef t edge 86b of bounding box 74?

These four comparisons can be written in eSluation form as follows:

IF Wy c NPY ~ ay + by AND
Wy ~ e ~ NPY + ay AND
Wx ~ NPX ~ ax + bx P~ND
Wx + e > NPX ~ ax ther~ the bounding box test pa~ses for that window.

Because bounding box 74 is, in general, larger than node projection 6B, a window which int~ects the bounding box does not s~ece~sarily inter~ect ~he node pro jectis~n. ~owever, ~ny ttindow whi~h doe~ not intersect bounding box 74 o rlode projection 61B does not intersect with the nsde projection. Thus, a window which E~ the Bsox ~ ~3179~

l:le~t does not n~ce~arily inter~e~ct t~e nod~
proiec~cionV but ~ window whic:h ail~ the ~OX t~st d~finit~ly doe~ not $nter~ect with ~he nod~
pro~ection. A ~cond te~t i~ r~qui~d to det~rmine i ~he ~indow inter5ect5 the node proiection itself.

T~E POL _ON INTERSECTION TE5T

The object of the polygon intersection (PI) test is ~o determ;ne i~ a window that has be2n found to inters~t the boundin~ box of ~ node projection o~ interest intersec~s the node projection of itsel~. The PI test i~ per~ormed by selecting a "critic~l vertexH of the window for each of the six edgee of thc node projection and comparing the position of each edge of the node projection with the position of its corresponding critical vertex to determine âf the ~ritical vertex lie~ on the "side"
o~ the edge in~erior to the node projection. The PI
~e~t ac~ually comprises ~ix independent comparisons, one for each of the six edge~ o a node pro~ection.
Rof~rring to FIGU~E 8, ~hown i~ an a~bitrary window 88 and ~n arbitrary node projec~ion 6a h~vîng 5iX exter~or odge~ 16. The po~ition of window 88 must be compared wi~h the position of e3ch 12~79q , o~ e~gos 11~ o de'ce~in~ oRIe par~ of ~
~indow inter a~ct~ ~o~e p~rt o ood~ project~or 68.
R~f~rring to FIGURE~ 9tA), 9(~), 9(~
9 ~ hown i~ a gr~phic illu~'cr~tion of the seleotion of ~ PI test criti~al verte~ of window 88 for ~n edge of a nod~ projection as a func~cion o~
the slope of ~ch~ ~dge and ~he orientation of that edge with respect to ~he interior of the node pro~ection. Upper left-ha~ld vertex ~8a of windos 88 i~ ~elected al~ the criti~al vertex for the PI te~'c for edges ~urh as edge 90 which have a positive slop~ ~with respect to the view plane coordinate systeD~) and ~re segments of lines d~fining a halÇ-plan~ ~u~h that ~he node p~o~ction lie . above ( i ~e.
in th~ itlve y direction wi ~h re~pec~ t~) the edge ( ~or example, edge 11 of FIGU~E ~ meet t~lis desc~iption). The lower ~ight-hand s~er~ex B~b of window 88 i~ sele~ed as the cri'cical verl:ex for edge~ such as edge 92 which have a positive slope and are ~egment3 of lines def ining a half-plane su~h thzlt ~h~ node pro jection lies below th~ edge 5 for ex~nple, ~dge 14 of nod~ projec~ion 68 of FIçuEaE 8 ~e~es this de~ri~3~ion~. The upper righ~c-h~nd verte~t ~8c of window i3~ is ~elected as the cYi~ical verte~ for edges such as edge 94 wh;ch have ~
nega~:ive ~lope and are segments of lines def ining a - ` ~ ~
~337~

hal~-pl~rle ~uch that ~he nod~ proj~c~ion i~ albove t:h~ ~dge t fo~ mple, edge 13 o~ node pro j~ction 68 hc~wn in F~G~E 8 ~et~ ~hi~ de~c~ipl:ion). rin~lly, the lower l~ft-hand vertex 88d o~ window æ8 i~
selected as the critic~l v~rtex for edges su~h as edge 96 which h~ve ~ n~gative slop~ and are segments of lines defiriing a half-plane ~uch that the node proj~ ion lies entirely below the edge (for example, edge 16 o~ node projeetion 68 of FIGURE 8 meet~ thi~ description~.
R~erring to FIGURE 10, shown is the ~o~etry o~ the PI test for edge 11 of node projection 68. Becau~e edge 11 has a positive slope and i5 a segment o~ a line 98 def ining a half plane such that th~ node pro3ection 6~ lies completely above the line, vertex 88a of window 88 is selected as the critic~l vertex a~sociated with edge 11 ( the geometry, i~ analogou~ to that shown in FI~URE
9~A) ) . The ~I te~t detQrlaines whether critical vertex 88a lie5 within th~ h~lf-plane def ined by line ga whi~h contain~ node projec~ic>n 68. Thus, for this g~om~ry it mu~t be de~cer~ined whether the cri~ical vertex lies above th~ line ( i~ the nodg!
pro~ection 6~ wa~ contained by the halfop1an~! below line 98, ~:he opposit~ ver~ex 8~b would be selected a~ the critic~l vertex~ ~nd the test would have to ~2337~

6~

deter~in~ ~f verte~ ~Bb lie~ h~ h;~l-plan@ b~low lin~ 91 To d1!t~rmine i~ critical Yertex 88a li~
abov~ lin~ 98, two ~di~ional line~ 100 and 102 are oon~tructed~ Line lD0 i~ ~uitabîy the line parallel to line 9~ defilled by the ~dge of node projection 68 in interest (here, edge 11) which passes through the origin of the view plane 104 (how the or;gin of the view plan~ 104 is defined s~ill be di ~ussed h~r~after: it suffices here to define point 104 as 2n arbitrary ~ix~d point used for all six critical vertex~to-edge comparisons of the PI te~t).
Line 10~ i~ suitably the line constructed parallel ~o line 98 which passes through cri~ical vertex 88a. If line 102 lies within the half-plane def ined by line 98 which contains node pro jection 68, then csitical vertex 88a will 21lso lie within that half-plane.
A lin~ segment Ndl is ~ui~ably constructed ~ro~n line 100 to line 98 perpendicular l:o both of thes~ lines. ~he length of line segment Ndl i5 thus thg! distance between lines 98 and lOû. Analogously, line ~egment Wdl i~ constructed frs~ e 100 to l~ne 102 perp~ndicul~r to both o these lin~. The l~ngth of line ~egment Wdl i~ the distanc~ b~tween line~ 102 and lOû. The length of line segment ~dl

7~

6~

is co~pared with t~e length o~ ~ine ~eg~ent Wdl: if ehe lengt~ of line ~g~ent ~dl i~ les~ th~n the length of line segment ~dl, ~ritical vert~x 88a lie~
in the same half~pla~e d~fined by line 9~ which contain~ node projection 68.
~ s ~ntioned prev;~sly, the ~omparison just described is made for all si~ of the edges of node proj~ction 68. Only i~ all six comparisons yield ~ pas3 re~ult (i.e. if the selected critical vertex for each of the six edg~s i5 ~ound to lie within the uinterior" half-plan2 defined by i~s respective edge~ does th~ w;ndow 88 pass the polygon intersection test. If a window passes the PI test, i~ doe~ no~ nec~ssa~ily in~r~ect nod~ projection 68; this i~ becau~e all six o$ the compari~ons are made with respect to hal~-planes rather than with respect to the node projection itsel~.
As mention~d previously, a window which Passes t:he ~OX t~st cannot be guaranteed ~o in~er-sec~ the node projection, al~hough a window which fails the B~OX test can be guaranteed not to inter~ect the node p~ojection. Likewise~ ~ window which ~sses ~he PI te3~ cannot be guarante~d to inter~ct the node projectionr although a window which fails ~he PI ~es~ can be guaranteed not to intersect the node projection. ~owever, iÇ ~ window ` 1~2317~

pa~s~ both the ~OX ~nd P~ ~e~t~, it can ~ ~roven thàt ~be window in fact in~ersects the node projec~ion.
Thu~, by ~uccessively applyin~ two rela~ively simple geometric test~ to a given window, the BBOX t~st and then the ~I test, it can be det~rmined with certainty whether tha~ wiQdow inter ects the node projection. The preferred embodimen~. o~ the present invention uses ~his method for testing intersection becau~e at may be ea~ily ca~ried ou~ using simple ~alculations and few operands (i.e. for efficiency r~asons)~ Those skilled in the art will, of course, bz able to devise methods for testing geometric interse~tion be~ween window 82 and node projection 68 which yield more determinative results with fewer comparisons.
~owever, by employing a series of r~latively simple tests r~ther than one single, more complex test, the presently preferred e~.bodiment quickly determines cases o~ non-intersection ~nd non-inter~ec~ing windows are quickly di~carded. ~St~tistic~l analy~i~ ha~ shown that approximately 80~ of the ~indo~ th~t do not intersect node projection~ are eli~inated by the BB~X tes~. ) .~ J23~79~

2NC~O5~RE TSST
. ~

As mentioned previou~ly, the objec~ o~ ~he presen~ in~ention i~ to loea~ and paint all o~
those window~ on the view plane which are entirely enclosed by the projection of a F node (i.e. one which is enclosed by an objec~). A window which does not intersect a givEn node projection cannot possibly be enclosed by th~ node projection.
~owever~ only a subset o~ ~hose windows which in~ersect a node projection (as determined by the combined results of the 8BOX and Pl tests) are enclosed by the node projection. Thu~, a third test, c~lled the ~nclosure (E) ~e~t, i~ neces.ary to de~rmin~ enclosu~e.
The preferred embodimen~ employs a techni-gue call~ed "block shading'`, an added enhancement which nec~ssitate~ dividing node projection 68 into th~ee faces (~5 w~s shown in FI~URE 6~AI ); the E
te~t det~rmines not whether a given window i5 enclo~ed by the node projection, but whether it i5 e~clo~ed by one of the face~ of ~he node projection~
Whil~ the algorithm executed by the preferr~d embodiDIent of the pre~ent invention would be somewhat simplified if the E te~t was performed with respect to the entire node projection~ separate E

3~ 3 61~

t~-t~ for e~ach o the ~hree ~aces of the ne~de projection ~re peror~ed in orde~ 'co permit lth~
~r~a~ion 9f a~ 21ore! realixtic 'chree-dimension~l image. ~An alterna~ce ~hading ~ethod called ~sl~rface normalC~ ~hadin~ use~s the ~ntir~ node projection, not the individual faces9 and ~ill be discussed below).
Wh~n a ~ive~ window i5 painted, the colo~
or shading which it is painted may be affect~d by a number of fac~ors; windows may be painted any ~olor or ~hade desi~ed. It has been ound that by painting windows on~ e~f th~ee dif ferent colors or shades depending upon which one of th~ three ~aces of the node projection encloses that window, a sense of depth i~ added to the f inal imasl~ because th@
viewer is abl~ to di~tinç~uish ~hree directi~n planss of the obje~:t ~as d~fined by the three visible faces of the parall~lepiped three- dimensional universe) from on* another. In order to mak~ this shading distinction, it i~ thu~ n~ces~ary to determs ne not merely whether th~ node proj~ction enclo~s ~ gi~en window, but whether one of ~he thr~e face. of the node projection enclo~es ~ha~ window.
~ he objec~ o:E the 1: test, then, i~ ~o determine whether a window i~ completely enclo~ed by one of the three Eaces c~f th~ node proj~ction. The geome~ry of ~he E test i similar to that o~ the PI

317~

t~t. R~ferrin~ to FI~RES ll~A)-(D)~ ~how~
gr~phie~l illu~tr~tio~ o~ ghe ~elec~ion o critical vert~ of an abi~rary ~indow 8~ for ~he ~
te~t as a unotion of the ~lope o a f~ce edge o a node projection and the orisntation of that faee edge wi~h respe~t ~o ~he interior o ~he fac~ of the node projectionO It will be noted by comparing FIGURE5 9(~)-(D) and ll(A3-(D~ th~t the vertex opposite that selected for the PI test is sele~ted as the critical vertex for the ~ test in each of the four case~ 7 Thus, a ~ac~ ~d~e 5uch as edge 90 having a positiv~ slope (with resp~ct to the view plane ooordiante system) and i3 a segment of ~ line defining a half-plane containing the interaor o the face which li@s above the line selects vertex ~8b of w~ndow 88 as the critical vertex for the E test.
Vertice.~3 ~8a, ~8d and sac of window 8~ are selec~ed a~ the critical v~rtex or the E test for ~ace edges 92, 94 and 96t respe~îvely, in an analogouc manner.
Referring to FIGURE 12 D shown i the geometry a ~ociat~d with ed~e 11 of f~ce 71 of node pro~ection 68 for th~ E 'c~st. It will be understood ~hat th~ E test irlvolv~s ~our such cosnparison~ for each ace o~ the nl~de pro jection ( for a tot~l o twelve c:omparisons) in order ~o te~t each o ~he ~hr~e faces of ~che node projec~iosl.

3179~

.

A line 9B defined by ~ ll caf ace 72 i~
~uitably con~tructed, a~ ~or the PI ~e.~. Likewise, a ~econd line 100 i5 3uitably cGnstructed parallel to line 9~ and passing ~hrough origin 104 af the view plan~ hir~ line 106 i~ cons~ructed parallel to line 98 which passes through the crlti-~al vertex 88b of window 8~. A line ~egment Ndl is constructed betweerl lines 100 and 98 and perpendieu lar ~o boeh of these lines, ju~t a~ for the ~I ~est.
Likewise, a giecond line segment Wdl i~ s:onstructed between line 100 and line 106 perpendicular to both of these linesO
For the geometry ~hown, if window B8 is complet~ly ~nclos~d by face 71, then all of the following ~u t be 'crue: critlc!al v~r~ex 88b mus'c lie above edge 11; critical vertex 88a must lie below edge i3: critical vertex ~8c mus~ lie to the left o ~dge 16; and critic:al vertes~ 88d must lie to the right of edge 7.
To determine if criti~al verte~ ~8b lies wi~hin the half-plane defined by line 98 in which ~he in~e~ior of face 71 ligs, it i~ necess~ry only to comp~re the po~ition of line 1~6 with th~
position.Q~ lin~ 98; for the geome~ry ~hown, if line 106 lie~ above line 9d, then critical vertex B8b must also l;e above line ga (ar~d thus in the 7~ ~3~.7~

rio~ hal~-plane)~ Thi~ c~anparison may 3uit9'D1y ~e acco~ hed by comparing the lerlgth of line ~egmen~ Ndl ~ith the leng~ch of line segment Wdl; if Ndl c Wd~, therl the E test for ~he criéical ver~ex ~8b i~ satisied ( i~ will b~ understood that th~ diree~ion o~ the inequali~y ~ign will change i~
the half-plar~ def ined by line 9~ csneaining face 71 lies below ~he line, ju~t as ~he opposite critical vertex 8~a would bs ~elected for the comparison~.
An analogous co~npari~on is performed for each of the four ed~es of face 71. If it i~ found that all of ~che four compari~on~ are ~rue, ehen ~:he window }?asses the E test for ~hat face, meanirlg that the window .i5 coMpl~ely enclosed by the face.
Obviou ly, a giYen window ean only be enclosed ~y on~ of the three Çaces of a given node pro jecti~n. Neverthel@ss, because all of th* twelve compari..~on~ require . imil~r information, all twelve comparisons may ~uitably be performed . imulSaneou~ly to determine ~1 ) whether the win~ow i~ encl~sed by a fa~e ~ in which ca~e an EPASS signal is genera~ced) ~n~ ~2) which o~ the ~hree faces i~ enclosed by if it 1~ ~o enclo~ed ( indicated by ~CE NUH~
inor~ation specifying which of the three ac~ the window i~ enclosed by so that the window may ~uit~bly b~ p~inted a proper colorl.

1 7 9 ~

Referring to ~IGU~aE 13e ~ is func~iona~l bloc:k diagra~ o how ~h@ resul~ of ~h~
~BOX, P~ and E tes~s are us~!d by the preferr~
embodim~nt of ~he present inver, ionO As discussed, ~ach o~ ~he ~hree ~e~ re carried on indep~ndently. Lik2wise, each of the three ~est~
use si~ilar information about the location and orientation of node pro jeotions ( "NODE GEOMETRY" ) carri~d on bu~i 108 a~d the position and orientation of windows in the view plane l"WINDOW GEO~TRY") rarried on bu~ 110. The BBOX test block 112 genera~e~ an output BPASS indic~atin~ w~ether ~he window passes the B~OX te~t. The PI test block 114 gener~tes an outpu'c PPASS indicating whether the window pas~es the PI ~est. ~3P~SS and PP~SS ar*
ANDea toge~her ( by ~ND y~te 115 ) to generate ~he signal INTERSECT, which is asserted if the window inte~ ts th~ node proje~on, a~ diss:ussed abov~.
The E test blosk 116 genera~es an output ~iqnal ~:~ASS which is a~sert~d if the window passes the E test, ~sd alsv gen2rates a signal P~CE NUM~ER, which indicate~ which face of the node projection the w~ndow i~ enclo~ed by (i~ it i~ enclo~ed by any of ~besn~. The EPASS signal i~ ANl)ed with the INTEP~5~CS signhl by AND ga~e 117 to generate ~n output ~ignal PAI~T.

~L~3~790 It ~houl~ be no~e~ eh~t. ~ile the proces~
~ho~n ~n PIG~E 13 perfor~ each ~ ~he thr~ te~t~
~imultaneously, ~he pre~ently preferred exempiary embodiment in accord2nce wi~h ~he prssent invention actually perfor~s ~uece~sively the ~indo~ No~ FULL
and BBOX te~s, then the PI test and finally the E
test. Only if the window i4 not FULL, and the BPASS
signal is generated will the PI te~t be performed~
and only i~ the PPASS signal is generated will the E
test be performed. Efficiency is increased in this ~anner, ~inre windows which fail an early one of the te~ts are disposed of early a~ter a minimu~ number of calculations.
It will be under~tood that simultaneous performance of these tests may be pr*ferred eo allow even greater effioiency if sufficent hardware was availab].e (such as in ~ VLSI envir~ment). ~ndeed, differeJ~t eesting algorithm~ might be pre erred for other hardware implementations. ~or instance, the PI te~t could be perfor~ed on faces of the node projection rathe~ ~han on the en~ire node projection ~ ju5t ~3 the E te$t 1B performed on the individual fac~)O Some of the features o ~he testing ~lgorithm are arbitrary or determined by the par~i~ular hardw~re implementation employed, and might not be preerred for different hardware ~23~
7~

impl~mentations ~e.g. VL5I~ of the inven~ion.
Mor~ov*r t it will b~ under~tood by ~hose 3kill~d in .
the a~t that th~ PI and ~ tes~s could in act be completely di~pensed with entire~y, ~nd the ~OX
test alone relied up~n to determine whether the node projectio~ inters@cts the window under test. While substantial ineÇficieney would reqult by using only the BBOX test (a~ will become apparent), the image generation could still be successfully carried ouk. The added inefficiency might be tolerable in, for instan~e, VLSI hardware environment~, where high speed could compensate for inefficiencies in ~he algorithm executed.

In the course of discussing ~he oper~ion of each of the three te~t~, an a~bitr~ry node projection and an arbitrary window we~e as umed. As mentio~lad before, however, window B8 is actually one of th~ four windows of window ~8~01-78(3) o window overlay 7B in ~IGURE 6(C). Ea~h of the windows in the window overlay mu~t be tested ~or the ~BOX, PI
and E test~.
Only the projections of non-~mpty (i.e. P

or F) nodes are tested for intersection by the preferred em~odi~ent, sincæ only nodes cont~inin~ or cont~ine~ by ~n ~bjec~ will p~oje~t an i~age onto ~h~ view plan~. Lik~wise, only ~ull nodes are suitab~y ever test~d for ~closu~e, ~ince it would not be known with c~rtainty whether a window enclosed by a Partial node ~hould be painted or not (part or no~e of such a window might actually be enclosed by the projection of nodes contained by the object1~ Partial nodes are tes~ed for intersection (by the BBOX and the PI tests), however9 since descendents of a window can only be enclosed by descend2nts of a node if the window and the node intersect. Determination of non-intersection may eliminate m~ny unnece~sary tests at lower levels.
~ence~ ~n ~MPTY node may be dis~arded, while a PAR~IAL intersecting n~de must be further cubdivided until its F~L~ descenden~s are en~ountered if it ~ontinues to intersect at least on~ wi~dow that was not previously paint~d.
I~ a window i5 found to intersect a FULL
node projection li.~. the INTERSECT signal shown in FIGURE 13 i~ assert~d) but fails the E test, then only p~rt o th~t window is enclosed by the node pro~ection. R~calling t~e quadt~ee strueture o the vie~ plane shown in FIGURES 3(A) and 3~, at least one of the descendentY of the window must be a FU~L

7~ ~ 3~ ~9 ~

window ~hich i~ co~ple~ely enclosed by the node projection (~s~u~ing a quad~re@ ~tructure with an in~ini~ number of l~v~ n this ca e, the window is ubdivided into it~ ~our children and the ~BOX, PI and E test~ are performed on ~ach child window ~o determine if one of them is completely enclosed by ~he node projec~ion. ~e~ce, in this special case, the window overlay will be comprised of four childr~n windows having the same parent.) This process continues recursively until all partially-enclosed windows have been subdivid~d into windows that are eith~r FU~L or EM~TY lor until a predetermined resolution limit is reached).
I a window is found which p~sses all three ~ests and i ~hu~ completely ~nclosed by a FULL node projection, it must be marked ~U~L (F3 in the quadtree ~rueture shown in FIGURE 3IB). ~n order to keep the guadtree structure accurat@~ all of the a~oestor~ of thi~ FU~ window ~arked E must be marked P~RTIAL (p). Mor~over, if it happens ~hat the other three ~iblings ~children oE the same par~nt window in th~ quadtree) of thi~ FU~L window are ~l~o FU~L, then i~5 parent window must b~ ~arked FU~. T~e Quadtree Storage blo~k 118 shown in FIGURE 13 is used to store the upd~ted quadtree struc~ure~

23~79~3 The reader should now begin to appr~ei~te th~ r~cur~ive nature of tho algorithm in accordanc~
wi~h ~he pres~nt invention. The octree ~ructu~e representing three-dimensional spaGe is traversed to locate FULL nodes, and si~nultaneously, ~he quadtree structure of FIGURE 3(~ i traversed to locate windows which are completely enclo~ed by the projec-tions of those full nodes. At any given level of the octree structure, all eight children nodes must be proc~ssed: EMPTY nodes are disposed of immediately; FULL nodes are processed by qubdividing the win~ows of th~ window overlays defined by those .ull nodes (by traversing the quadtree structure downwar,d) to locat~ those windows which are complet~ly enclosed by the projections of tho~e ~UL~
nodes; ~nd PARTIAL nodes are subdivided (together with the window overl~ys de~iled by the projections of such nodes) to locate PULL nodes unless all in~er~cting windows are ~U~L (already painted).
Onc~ a FULL nod~ is encountered, each of th~ intersecting~ non-~ULL ~indows in the overlay which it defines are tested ~o see if they ar~
complet~ly enclosed by the projection o~ the P~LL
node~ Window~ which are completely enclo~ed by the node projection are painted; windows which do not intersect the node projectlon are discarded; and 7 ~ ~

window~ which in~r~e~t ~u~ are no~ enclo~d by th~
node p~a~ction are ~ur~her ~u~ivided (given ~h~
limitation~ imposed by the window resolution) to locate windows which are ~nclosed.
A~ di~cu~sed previou~ly, in order to avoid diqplaying surfaces hidden from t~e viewer or a given viewing angle, only a subset of the nodes marked as FULL in the octree struc~ure of FIGURE 2 will actually cause painting on the display creen because the ~iew o some o~ ~he ~U~ nodes will be obs~ructed by other FU~L node~. ~ecau~e the objec~
is ~hree-dimensional, some windows may be completely enclosed by several ~ node projections simultaneously: only the p~ojection of the first-~ncountered enclosing node in the traversal sequence should be permitted to paint such a window since this first FULL node, being visi~ed ~irst in ~he ootr~e traversal sequen~e, visu~lly obstructs the portion~ of ~he objec~ repres2nted by later-visited FUL~ nodes. Of~en, such later nodes are never visited be~u~e an ance~tor node was found to not intersect any non-FU~L win~ows and it and i~5 deso~ndant~ are discarded ~i.e. nev~r acee3~ed)~
~owev~r, when the l~er node or nodes complet~ly enclosing the window are visited, the window will be found to be FULL and not painted. Thu~, only the `-` 1231790~

~ir~t ~uch enclosur~ will r~ult in paislting.
Co~ r~lativ~ to ~hi ~ wbil~ 2~ny ~iven node in ~h~
octree i~ vis~ted only once; a given ~indow ~n~y be vi~ited numerc~us ~imes tbut may be painted only c~nce ~ .
Referring once again to FIGURE: 13, to ensure that ~ given window is painted only once, the guadtree storage blo~k 118 generates an output WINDOW EMPTY indicating whether the window under test h~s previously been painted. Thi~ ou~put i5 ANDed toge~her with the ~N~ERSECT and the ~:PASS
signals by AND gate 117, so that the PAINT si~nal is only produced if the window is both enclosed by a face o the node projection and has not been painted previously.
I~ ~he PAINT signal is asserted, the window will be pa~nted on a display screen according to one of thr~e shadec or colors determined by the F~CE
NUMBER signal (for block sh~dinq) and in a location specifîed by ~aindOw t;eometry bus 110.

CUT Pl.,9NE TE:ST

One of the prinicipal advantageous features of the algorithm discussed above is tha~c a realistic two-dimensional image of a three dimensional object --~` 123179~

i~ g~nerated ~n which ~11 surfaees ~hich are hidden fr~ view ~ro~ the given viewing ~ngle ar~
elim~nated fro~ th~ i~ag~ It i~ often u5efuiv however, to generate sectional or cut-away images of ~he three-di~ensional obje~t, permitting a user to define portions of the objec~ which are not to be displayed so tha~ those por~ions do not obs~ruct the view of the portions of the object which the user desires to see.
An enhan~ement o~ the ~lgorithm executed by the presently preferred embodiment of the present invention permits a usar to define a three-dimen ional subset o the three-dimensional universe. The al~orithm will only produce the PAINT
signal when an F node completely encloses the window under test, the window has not previously been paint~d ~nd the ~ node lie comple~ely within the user-d~Eined ~hree-dimensional spaee. ~y defining this space in different ways, the user may view areas c~f the object which would ordinarily be hidden from view rom the p~rticular viewing angle (or per~ap~ fro~ every viewing angle)O
Referring to FIGURE 14(A), shown i~ ~
graphie illustration of three~dimensional universe 32, portions of which have been eliminated fro~
interest. In order to ~implify the calculations -" 12~17~

~1 in~olved, th~ pr@ferr~d ~mbodi~nt permit~ tho us~r to ~efin~ ~ sub$~t of universe 3~ of in~ere$~ by d~fining a pair o~ parallel ~cut planeR~ 120 122. Cu~ planes 12U ~nd 122 may have any orient~tion with respect to univ~rs~ 32, the only constraint being that ~hey are parallel plane~.
The portion of universe 32 whieh will be displayed i. that ~ortion lying between cut planes 120 and 1~2 ~or out~ide o~ the space between the two planes, at the user's seleotionl. For the geometry shown, nod~ 7 and 2 and 0 (not shown) lie entirely within the spac~ defined by ~ut planes 120 and 122 to be displayed, and will be processed as previously discussed. ~ikewise, if cut planes 120 and 122 were situated su~h that some of th~ descendent nodes of root node 32 were located entirely outside of the re~ion to be displ~yed (for example, if the re~ion to be dlsplayed w~ defined as that portion o~ root node 3~ lying outside of the spase b~tween the two planes, nodes 7 and 2 and 0 would be such nodes)~
the~e nodes could be immediately disc~rded and not te~ted ~t ~11 for either int~r~ection or enclosure ce they ~ould never be u~ed to pain~ wi~sdow~
(~Yen if they were F nodes).
Somewhat analogous to the conoept of ~ P

node di~eu~sled previously, however, are those nodes ``` ~2317~

g~2 which ~r~ inter~ected by 05~ o~ cu~ plane~ 120 or 122~ ~or oxa~mpl~ hild node! 3 o ro:7~c node 32 ~g int~r~e~ted ~y cu~ plan~ 120, ~o ~hat some o~ lt~
child node~ are within th~ region to be d~ splayed while ~o~e of t~e~ are ou~side o~ that region. Just as a P node must be furthQr ~ubdi~Tid~d to determine which of its descenden~s are ~ nodes, a node which in~cersec~cs a cut plan2 must be further subdivided to locate all of it~ descerldent F nodes s~hi~h lie wi~chin ~he region to be displayed ~a~ defined by the cut plane~). Thus, child nodes 7' ~ 6', 5' and 4' of child node 3 are cont~ined within ~he region ~o be displayed def ined by cu~ planes 120 and 122, and will b~ proc~ss~d as discussed previously. Howe~er, chil~r~n nodes 3 ', 2 ', 1 ' (an~ peobably 0 ', not shown) of child node 3 are in turn intersected by cut plane 120, and must be fur~her subdivided.
While it would be pos~ible to first subdivide root node 32 in order to determine which of it5 descend~nts w~re loc~ted within the region to be displayed by ~ut plane 120 and 122, trim the oct~ee ~tructure to eli~inate all ~hose nodes which wer~ no~ ~o located, and ~hen perfor~ the algori~hm a3 di~u~sed previously orl the modif ied oct~ee structure, such a method would require a separate de inition ~ ~he octre~ ~tructure for each 83 ~ 3~ 7 ~ ~

differ~t d~initio~ of cu~ pl~ne$ 120 and 122. The presently preferred embodi~en~ of t~e pre ent invention traverses the oc~ree ~tructure only.once, and subdivide4 a node ~ither if it is a P node or if it is an ~ node and i5 interse~ted by a cut plane.
A PAINT signal is only produced if the contitions previously discussed ~r~ s~tis~ied ~nd the F node under test is completely contained within the region defined by the cut planes to be displayed.
~ e~erring to FIGURE 14lB), shown i~ a graphic illustration o ~he geometry of the cut plane test, which determines whether a node i5 contained within the region to be displayed defined by cut planes 120 and 122. ~he node under test is projected onto a ~wo-dimensional cut plane test plane perp~ndicular to ~he cu~ planes 119 (the plane of the page)~ resulting in a node projection 124 (while this proce~s is exactly analogous to projec~ing a node on~o the view plane discussed previously, the tes~ plane and the view plane are no~, in general, the ~ame entities in the presently preferred e~bodiment becau3e the cut planes can be randomly oriented with re~pect to the view plane.
A k axis perpend;cular to bokh ~ut planes 120 and 122 ic con~tructed. Cut plane 120 ~the "re~erenc~ ~ut plane) is located at k - 0, while 2~179~

cu~ pl~ne 122 is loc~t~d at ~c - ~DIAG l in the preferr~d ~bodiment, ~h~ u~or d~fines the lo~ations of cut plane~ ~20 a~d 122 by ~p~cifying th~
direction of the k axi~ on th2 t~st plane, the position in 3-D of point 126 ( k = O ) ehe di~tance LDIAG between cut planes 120 and 122, and whether ~he region to be displayed i~ either inside of the cut plane~ ~i.e. O ~ k s LDIAG) or outside of the cut planes (i.e. k 5 0 or k ~ LDI~G). Those skilled in the art will understand that it is not really necessary to project the node onto test ~ 119;
actually, nodes are pro~ected onto a line 7 the k axis lthu5i a three-dimensional parallel~piped is a tually projected into one dimension to determine distances?-It is necessary ~o isolate the two vertices128a and 1~8b of node proje~tion 124 whic~ have k coordînate~ ~h~t are most nega~iv@ and most positive. The k coordinate of the ~left-most"
vertex 128a of node projection 124 ~i.e. that ver~ex which ha~ the most negative k coordinate) is defined as ~PK~ Analogously~ tbe "right-most~ vertex 128b of nod~ p~o~ecti4n 124 1 ehat vertex which has ehe ~o~ pos;tive k coordinat~) i defined a~ NP~
KDIAGo ~5 ~ ~3~ 3~

If l:h~2 r~gion to be di~play~sd i~ de~ined as th~t re~ n in~ide of the ~ult planes 120 ~n~ 122, th~n node pro j~ction 124 i~ ent; r~ly within ~che region to be di~played if:

NPR > O A~aD
NP~ + KDIAG < LDIAt;

These eguations ar~ sa~:isfied i the left-mos~c vertex 12ga i~ t :3 the right of reference GUt plane 120 and the right-mos~ vertex 128b is to th~ left of out plane 122 (node projection 124 shown in FIGURE
14~B) sat;sfie- these conditions).
If th~ region to be displayed is selected as t~.e region outside of cut planes 120 and 122, then a nGde loca~ced wi~hin the re~ion to be di~played must atisfy the following e~uation:

NPK > LD~AG OR
NP}~ + RDIAG ~ O

Th~se equ~tions are satisfi~d if either the left-~o~t vertex 128z i~ to the righ~ of cu~ pl~ne 122 or th~ righ~-~no~t verte~ 12~b is to the left o referenc~ cut plane 120.

~L23~79 ~6 If neith~r of th~Re ~wo ~e~s of oondieions are ~ti~fi2d, ~hen the node progec~ion under t~t is neither co~pletely withln or completely out~ide sf the region to b~ displayed; in other words, it i5 inters~cted by one (or both) of the cut planes. ~5 dlscussed above, a node whioh is inters2cted by a cut plan~ must be further ~ubdivided in order to determine which o~ i~s deso~ndent lie within the .region to be displayed and which lie outside o~ ~he region to be displayed. Whil2 perhaps not immedia~ely apparent, all o ~he nodes along an "ed~e~ of ~he object ~efined by a cut plane (i.e.
along the flat surface defined by a cut plane which border~ the r~gion to be displayed as shown in FI~URE 14(A)3 will in ~en~ral be the lowest lev~l of subdivision permitted by the constraint of r~solution requirements.
While th~ u~e o~ a pair o~ parallel planes to defin~ a region to ~e display~d within ~he three dimens~onal univer~e i~ efficient and requires ~ew ~alcul~tion~ to implement, i~ has th~ disadvantage th~ only planar sectio~al views can be generated.
Such views are extremely useful in many applica~ions ~such a~ ;n CAD~CAM ystems~ where planar sectional views are the conventional ~ype of sectional views employed. It may be desirable, however, to allow i~3~79~

~7 the u~e~ to defin~ more eo~plex regions to be di~pl~yed.
One simple way So expand th~ user'~
capability to define complex region~ ~o be used for sectional views i5 to per~it independent de~inition a plurality o~ pairs of parallel cut planes. Only ~ho3e node~ which ar~ contained within the region~
~o b~ displayed defined by all of ~he pairs of cut planes will be permitted to paint windows; likewise, a node will be subdivided if it is non-Empty and is intersect~d by any one of th~ multiple cut planes.
Providing a user with the capability of indepen-den~ly d~Eining three pairs of cut planes (and, ind~pendently, whether ~he region to be displayed is inside or outside each pair) permits the generation of extremely complex ~ectiona:L views~ It will be understood that it would also be possible to define such regions through th~ use o~ secand-order equations (or e~uations of higher order ), althoush th~ co~plexity of the calculation~ required to de~ermine whe~her a node i5 within the region ~o be displ~yed would increaseO

.~ 3~17~1 i ~8 ~UNCTIONA~ REPRE~ENTATION
~9~

R~ferring to PIGU~E 15, ~hown i5 a block diagra~ o~ t~e unctional represen~ation of the preferred ~mbodiment of the present invention. The function o ~h~ pre~erred embodiment comprises seven blocks: the DATA ACQUISITION block 129, the OCTREE
DAT~ CONV~RSION block 130, th~ OCTREE ENCODED 08JECT
STORAGE block 140, the INTERACTION WITH USER block 150, th~ IN~TIALIZING CONTROLLER block 160, the I~AGE DISP~AY PROCE~SOR block 152 and the IMAG~
DISPLAY block 154~
The DATA ACQUISITION block 129 may suitably be implemented by a number o methods, depending upon t~e application. For instance, i~ the present invention i~ ~o be applied to the generation of imayeR ~Df sbjects existing in the physical ~orld such asg or example, ~edical image generation, th~
DATA AC9UIS~TION blo¢k 129 ~ay comprise scanning th~
obj~ct with a CT (Compu~ed To~ography) scanner and gener~ting a plurality of data ~lices, e~ch slice co~pri~ing a plur~lity of cell~ having attached ~o the~ location and den~ity infor~ation.
I the preferred embodiment of the present inv~ntion i~ u~ed in CAD/C~ IComputer-Aided Design and Computer-Aided ~anufacturing) applications, the ~ ~ 3 1 7 91~

DAT~ ~CQ~f~ITION block 129 m~y comprise ~ ~oPtware prog~ exe~uting o~ an interactive digit~l co~puting device which permit~ a u~r ~o ma~hemataGally ~ ine ~ur~ace or solids within a three-dimensional ~p~ce according to location, density, sh~pe, ete. Those skilled in ~he art will immediately recognize a wide varle~y of different ways in which data def ining an obje~ miqht be input and represen~ed, and the present invention is by no means li~ited to any on~ such representation.
The OCTR~E DATA CO~YERSION block 130 acceDts data from the DAT~ QUISITION block 129 as an input and ~en~rates an octree structure (as shown in FIGURE 2) a~ an ou~pu~ to be stored in ~he OCTREE
ENCODED O~JE:C:T STO~GE blo~k 140. The OCTREE DATA
CON~ERSION ~loek 130 ~ust organize the ra~ data into a hi~ra~chical structure o obj2ct nodes, each of which h~s an ~so~ia~d proper~y value o~ E, P or F.
The OCTREE DATA CONVERSION block 130 must also define ar~as of the three-dimensional universe not specifi~d by the data fro~ th~ DATA ACQUISITIO~
block 129 by generating EMPTY ~leaW3 node~ to ter~inate branches in ~h~ octree ~tructure.
Finally, th~ OCTREE D~TA CONVERSION block 130 ~ust "tr~ he generated oetree lei~h~r a~ it performs th2 conversion process initially 3r during a second `" 12~J~

pa53 through the stor@d octr~e) to ~nark $11L~ Ith~
parænt o~ any ~ight childr~n node~ whih ar~ ~UI,I., mark ~:M*TY the pars~n~ o any ~ight c~ildren nod~s whir~h a~e ~MPT~r, and m2lrk P~RTIPl. ~ny node hsving descendents which ar~ FtJLL and descendents which ~re EMP~
~ n ~he preferEed embodimen~ o the pres@nt invention, the OCTREE D~T~ CONVERSION block 130 is implemented Iby a sof tware program executing on a digital computer. ~e OCT~EE DAT~ coNv~as~oN block 130 for th~ preferred embodi!nent will be described in detail ~hortlyO
Th~ fun~tion of the OCTRE ENCODED O~JECT
S~O~AGE block 140 i~ to store ~he octree structur~
gen~rat~d by the Ol:TRlSE DATA CONVERSION bloclc 130 and ~o p~rmi~ the I~AGE DISPLAY PROCESSOR block 152 to randomly 3cce~i the stored octree structure. The OCTREE ~:NCODED OBJECT ~OR.4GE blo~k 140 ~ay suitably be implemented by ~ large ~emiconductor Random ~cces L~emory (R~M) or oth~r storage device pQ~rmi~ting high- peed rar.dom access of information.
- The INTERl~CT~O~ WIT~ USER block 150 allows a u3~z to interact with the IMAG DISPI~Y PIROCESSOR
blo~k 152 through the INITI~I.IZI~G CONTROI,LER ~iock 160 ~o select a viewing anyle ( i . e . to rotate and transla~e the ~hree dimensional object with respect 1 7 9 gZ

to th~ w ~î~n~ o s@l~ct th@ ~cDle o~ l:hc i~sge ~o b~ d~pl~y~, to ~el~lt the color~eion ~nd ~had~ng o~ the di~playe~ age, to de~ine ~ut planes for the gerleration of ~ectional vi~w~, to ~elec~
w~erl an image ~ ~o b~ di~play~d, etc. The IN~CTION ~ SER blo~k 150 in th~ preferred e~bo~iment of tho pres~ c invention is implement~d by an alphanu~aeric keyboard (suitably a Vr-10û
~anu~actu~ed by ~igit~ quipment Corp. ~; a Trackb~ suitably ~ ~odel 636-G893 manufactured by M.~asurem~n~ Syste~s, Inc. l; and a ~it P~d ~ uitably a Model ~Pol0 manuactured by Summ~graphics, ~nc.~.
The I~ITI~LIZIP3G CONTROLLER ~lock 160 accept~ i~formation rom th~ IN~E~CTION WIT~ U5ER
block 150 ~n~ g~ner~te~ ini~ializing values for the IMAGE DXSP~Y P~OCESSO~ bloc~c 152 and the IMAGE
DISPL~r block 154. In the preferred ~mbodiment of the pr~sent invention9 th~ LTIALIZING Ct:NTROLLER
block 160 gen~r~t~ a 5e!~ l~f initializing v~lues for any given s~t o~ p~ameters ~peciied by ~he ItiTE:~CTI0~3 WITE~ V5ER block 150 I i .e. or any given i~q~) . The INITI~SZI~ col~aTRoLI~E~ block 160 i~
i~ple~nted by ~otwaræ ~uitably executing on ~
C8000 ~icroproces30r Ibased compute~ manufactured by Plotorol~ c. Th~ operatio~ of the INITIALIZI~i;

` ~3~791~

~2 rONTROLLER block 160 will be discussed in detail her~after.
Th~ I~AGE DISPLAY PROCESSOR block 152 accesses the octree-encoded informatisn stored in the OCTREE ENCODED O~JECT STORAGE block 140 in accordance with user-defined parameters generated by the INITIALIZING CONTROLLER block 160, and generates an output to the I~L9GE DISPLAY block 154 consis~ing of addresses of pixels to be displayed and the coloration or shading for those pixels ~a pixel is a unit of display corresponding to one dot on the dot-matrix di~play ~creen). The structure and operation ~f the IMAGE DISPL~Y PROCESSOR block 152, which is implemented in the preferred embodiment of ~he present invention by hard-wired digital logic, will be discussed in detail herea~ter.
q`he I~9GE DISPI,AY block 154 accepts the output ~rom the IMAGE DISPLAY PROCESSOR 152, stores the pixel information generated by the IMAGE DISPLAY
PROCESSOR block ~in a dynamic semiconductor Random Ac~ess Memory, suitably a R~S-3000 frame buffer manufactured by Adage, Inc., Billerica, Mass.), and displays ~ompleted images (suitably on a video monitor utilizing a high-resolution Cathode Ray Tube having 1024 scan lines).

~ 1~317~

OCTR~E DATA CONV~RSION

Referring to FIGVRE 16, shown is ~ graphic illustration of the process used in the presently preferred exemplary embodiment of the present invention to convert raw data defining a three-dimensional object acquired by the Data Ac~uisition block 129 shown in FIGURE 15 into an octree structure to be stored in the Octree Encoded Storage block 140 of ~IGURE 15.
The Octree Data Conversion block 130 in the presently preferred embodiment is implemented by a software program executing on a model 68000 microcomputer ~anufactured by Motorola, Inc. A copy ~f ~his software is appended hereto as Appendix A.
Shown in FIGURE 16 are four arr~ys 132a-132d, each of which is comprised of ~lements organized in an array of four rows by four columns.
Each of the elements has associated with it a gray scale image value indicating th~ density of that particular element. Arrays 132a-132d are the type ~f information conventionally generated by a medical CT (Computed Tomography) scanner. Such a conventional scanner produces a plurality ~f "slices" of the object being scanned, each of which comprises an array of elements sorted by location.

I 2 3 1~

~ssociated with each of the elements in each ~rray is information indicating the density of the spa~e of the object corresponding to tha~ element. Such information is conventionally produced and stored on a bulk information storage device such as a magnetic disk or tape.
While each of the arrays 132a-132d are in fact planar images representing often disjoint slices of finite thickness in the object to be imaged occurring at various depths in the object, they are treated by the preferred embodiment as approximating three-dimensional, contiguous slices of the object of uniform thickness, each element of each slice having a uniform density (this represen-tation of the arrays as slices of uniform thickness is indicated by the linec in phantom). In some cases, additional slices are generated between original slices by interpolation in order to improve image ~uality.
Because a CT scanner normally produces a very large amount of information/ the presently pre~erred embodiment only ~perates ~n four "slices"
of raw data at a ~ime. These four slices of data are read from the bulk informati~n storage device discussed above and stored in a random access memory. The Octree Data Conversion ~lock 130 then ., . '~ ~
~ 2 ~

divides each slice into 4 x 4 arrays (of 16 elements each) and ~perates on four such 4 x 4 array at one time, one from each of the four slices. ~n the representation shown in FIGURE 16, the slice from which array 132a is extracted is the bottommost ~lice, and the lices rom which 132b, 132c and 132d are extracted are stacked on top of this bottommost slice (in that order~. Thus, arrays 132a-132d as they exist in the object t~ be imaged are stacked one on top of another, thus defining the same two-dimensional area of their respective slices for a viewer observing the object in plan.
It will be understood by those skilled in the art that any conventional scanner or other data acquisition device has only limited resolution.
Thus, each of ~he elements of arrays 132a-132d is actually an average uniform den~ity value for a small volume of the object. The actual volume corresponding to a given element may not (and in the general case will not) have uniform density. Due to this limitation in resolution, the octree structure generated will not have an infinite number of levels, but rather will have an arbitrary, limited number of levels. In the preferred embodiment of the present invention, eigh~ to ten levels are typically used with 16 being the current hardware `` 1~3~79~

i~it, but, ~f course, any number of octree 1eYe1S
~ay be employed ~onsistent with the trade-off b@tween the resolution of the qenerated image and the time and hardware necessary to generate an image, limited only by the resolution of the Data Acguisition block 129 ~and the resolution of the Image Display Processor 152 and the Image Display block 154).
Thus, the elements shown in arrays 132a-132d constitute volumes represented by the bottom level of the octree (level eight, for example). The Octree Data Conversion block 130 of FIGURE 15 must therefore generate the ~ctree structure from ~ottom to top (the octree structure may suitably be generated from top to bottom if the three-dimensional object to be imaged is represented by a well defined set of parameters, such as a set of equation!s input for use in Computer-Aided Design applications; those skilled in the art could readily devi~e an algorithm to generate an octree from an analytically defined object).
The first step which the Octree Data Conversion block 130 must perform is to convert the density information of each of the elements in arrays 132a-132d Lo binary values suitable for compact storage in a semiconduct~r RAM. As ~ 2 3 1 7 ~

~7 previously mentioned, each of the nodes a~ ~tored in the octree structure can have one ~f three properties~ Empty, ~artial or Full. ~hus, at i~s most simplistir level, the Octree Data Conversion block 130 must determine whether each of the elements of arrays 132a-132d are Empty or Full (note that none of these elements will ever be marked Partial because such a marking indicates that the node has some ~ull descendents and some Empty descendents; because these elements are at the bottom level of the octree, they have no descendents).
Of course, it may be desirable to store information a~out each of these nodes ~ther than merely whether they are Full or Empty~ ~or instance, it might be desirable to represent o~jects of different densities with different c~lors in the generated image (in order to distinguish, e.g.
between ~one and flesh in medical imaging). It would be pos~ible to store such auxiliary information together with the E, P and F property information within the octree structure itself.
Indeed, it will be apparent to th~se skilled in the art that every node in the octree structure could have a plurality of Pields, each of which represents a property value for a different physical or ~ther 1 2~ J 7~1~

pr~perty of the three-dimensional object. The pre~erred embodiment of the present inventi~n, however, attaches ~o each node in the oc~ree structure only a two-bit property value, and thus may repre~ent only whether the node is Empty (00), Full (11) or Partial ~01). ~Even with this minimal representation, it will be noted that one more bit combination llO) exists which may be used to repre-sent a Full property value for a second physical property of the three-dimensional object or for distin~uishing between dif~erent disjoint objects contained within the three-dimensional universe.) The preferred embodiment of the present invention employs an auxiliary "property memory"
(not shown) to store additional property information about each node in the ~ctree which may he directly accessed by the lmage Display block 154 before the node is written.
~ uch additional information might include the actual density Df each node, a color for each node (encoded in intensities for ea~h of red, green and blue), an intensity for each node (determined, for instance, by the orientation of a plane tangent to the surface of the object and passing through the node with respect to an imaginary light source positioned ~behind" the viewer, the distance of the node fro~ the viewer~ or other factors)~ or other properties ~ssociated ~ith each n~de to per~it the yeneration of a l~ore realîstic image or to provide other information about the object.
Once the density values f~r each of the elements of arrays 132a-13~d have been converted into either an E (for a gray scale value below a user-defined predetermined level) or a ~ (for a gray scale value above the user-defined predetermined level), the parents of these elements may be generated. It should be noted that more complex E/F
determination methods ~han a .simple threshold determination may be used~ In the oetree structure, eight ~ontiguous level eight nodes will be g;ouped together int~ a family, and a single parent node will be generated from that group of ei~ht children.
The groupings of four sets of eight children into four families of eight are shown by each of the structures 134a and 134b~
The Octree Data Conversion block stacks the 4 x 4 array 132b ~n top of the 4 x 4 array 132a to generate a 4 x 4 x 2 array 134a~ The 4 x 4 x 2 array 134a thus contains four families of eight level 8 nodes. Analogously, the 4 x 4 x 2 array 134 is generated by stacking the 4 x 4 level 8 array 132d on top of the 4 x 4 level 8 array 132c.

1 2 ~

Once eight level 4 nodes have been grouped together, the property value o the parent of those eight nodes may be determined by examining the property values of all of the eight nodes. If all of the eight level 8 nodes are E, then the parent is also marked E. Likewise, if all of the level 8 nodes are F, then the parent o~ the eight nodes is marked F~ Finally, if some of the level 8 nodes are E and ~ome of the level eight nodes are F, then the parent of the eight nodes must be marked P. In other words, the property information must be identical for all eight children nodes of a parent node for the parent node to be given the same node value ~nd property lnformation as its 8 children nodes; otherwise-the parent node is given a P value.
Thuc, each vf the 4 x 4 x 2 arrays 134a and 134b represents not only oomprise a qroup of thirty-two level 8 nodes, but also a group of four level 7 parent nodes. These two groups of four level 7 nodes may be stacked one on top of the other to form a family of eight level seven nodes 136, which may be furth2r combined to form a single level six node.
Each of the level 7 nodes is now marked either E, P, or F; the property of the level ~ix node may be directly determined by the property of its children. As before, if all of the level 7 ~; 123179~

nodes in the group of eight are E, the level 6 parent node is marked E. Likewise, if all of the level 7 children are F, ghe level 6 parent n~de is marked F (property information is handled as noted above). Otherwise, the level six parent must be marked P (lndicating that ~ome of its descendents, but not necessarily children, are E and some of its descendents, but not necessarily children, are ~;
some of the level 7 children may be E, some of the level 7 children may be F and some of the lev2l 7 children ~ay be P).
It will be recalled that the octree struc-ture generated by a preferred embodiment of the present invention is "trimmed,1' meaning that the descendents of a ~ or an E node are not included in the structure. Hence, only if a level 7 n~de is marked P need its eight level S children nodes be stored in the octree. Likewise, the eight level 7 childrer1 nodes need only be stored in the octree structure if their level 6 parent is marked P. The Octree Data Conversion block generates as an output a "node packet" comprising a ~amily of eight children noaes; it will only generate such a node packet if the parent node of the node packet is marked P. Otherwise, it will generate no node packet and instead keep track of the property value -"` 12337~

of the parent node and use it to generate the next level ~ode (i.e. its parent).
Each time the Octree Data Conversio~ block 130 generates a node packet, it stores the node packet i~ the Octree Encoded Object Storage block 140 (shown in FI&VRE 15~, suitably using Direct Memory Access (DMA) techniques. In addition, it retains the property value of the parent node just produced whether or not a node packet is generated.
This parent node property value is used to combine with contiguous nodes of the same level in the octree generated later to produce even higher levels of the octree and further node packets. Although FIGURE 16 shows only the generation of node~ at levels Q, 7 and 6, the algori~hm used to genera~e those levels is carried through recursively up to the level zero, or the root n~de.
Every one of the 4 x 4 arrays in the four slices of raw data stored in the Octree Data Conversion block 130 random access memory must be completely processed as described above before four new slices of raw data may be read ~rom the bulk information storage device. As this process is recursively performed, higher ~nd higher levels of the octree will be generated. It may be necessary for the Octree Data Conversion block 130 to genera~e 2 3 ~ 7~

slices ~f empty data in order t~ complete the octree structure (i.e. if the number of slices stored on the bulk information ~torage device is not ~qual to 2n where ~ is the l~west tree level). Likewise, depending upon the ~ormat of the data gener~ted by the Data Acquisition block 129, it may be necessary for the Octree Data Conversion bloek 130 to add Empty elements to each of the slices obtained from the ~ulk information storage device if the number of rows of elements in each slice does not equal the number of columns, or the number of rows and columns is not divisible by four. Finally, it may be desirable to provide ~urther processing of the raw data in order to provide compa~ability with a variety of different data acquisition devices or to permit a user to modify or define some of the octree structure.
Sequential storage ("heap stora~e") formats wherein ~he descendents of a given node are stored adjacent to that node ~sequentially according to the 7-to-0 traversal sequence) could be used in the Octree Encoded Object Storage block 140 because of the sequential nature of the depth-firs~ tr~versal of the octree structure. Thus, in order to tr2verse the octree, ~torage locations could be merely read sequentially. While this meth~d represents the most `` 12317~

10~

e~ficient use ~f s~orage space, it provides no way to skip internal subtrees if, for example, ~ P node is found to not intersect any non-~ULL ~v~rlay windows. Sequential octree traversal must always begin at the top of the tr~e and traverse the entire tree. If it became necessary to alter the tree structure ~for instance, to insert another three-dimensional object into the universe), the entire octree would have be rewritten. More importantly, the octree strllcture would vary according to the traversal sequence and thus would have to be rewritten each time the viewing angle en~ered a new viewing octant, or alternatively, multiple copies of the octree would have to be created, one for each different traversal sequence.
Another possible method of stvring the octree is by using a totally Random Access linked-list type Storage ~ethod, wherein a giv2n node is stored together with two fields, one containing the property value (E, P or F) of the node and the o~her containing the absolute address in memory of a block containing its eight children (which would be stored sequentially). This method of storage is perhaps the most versatile, because any given "nsde packet"
(a family of eight children) may be stored anywhere in memory, and the parent of that node packet can be `` 123~79~

~05 made to point directly to ~he location of that node packet. Because the ancestors of a given node are always accessed before the node itself, the f~ct ~hat all of ancestors of a node must be accessed to arrive at the absolute address of the node poses no inconvenience whatsoever. Sinc2 a given parent node ~knows" the absolute address o~ its family of eiyht children, the eight children may be stored anywhere in memory (so long as they are stored together in a blo~k~. NDdes may be added to or subtracted from the ~ctree by merely manipulating the fields containing ~bsolute addresses. Moreover, the same octree may be accessed in different orders according to the traversal sequence for the selected viewing angle.
The disadvantage of this method is that for a memory with sizeable storage capacity, each field containing an a~solute address may be required to store a large number (as many as thirty-two or more) bits of in~ormation, The Octree Encoded Object Stor~ge block 140 would necessarily be a very large memory~ a large portion of which would be used merely to store the address pointers. Because the octree is preferably ~tored in Random Access Memory (such as semiconductor memory) in order ~o reduce access time, ~uch a mem~ry would.be extremely e~pensi~e.
Referring to FIGURE 17, the presently preferred exemplary embodiment of the present invention USe5 Relative Addressing Format, a refinement of the ~andom Acces linked-list ~ethod discussed above. A family of eight children nodes are always ~tored together as a unit (called a "node packet") in memory. It will be recalled that each node may take on one of three property values ~E, P
or P); thus, the property value of each node may be encoded into only two bits, as discussed previously. The property values of an entire node packet of eight children nodes may ~hus be ~tored in

8 fields o~ 2 ~its each for a total of only 16 bits (2 bytes).
Each child in the node packet mu~t ~lso "point" ~o the block containing its eight children. Thus, a n~de packet ~ust point to, at most, eight grandchild node packets, ~ne ~or each of the children nodes in the node packet, all of which are ~tored sequentially in a "node packet block".
Because the octree s~ructure is "trimmed,l' the children of only p~rtial nodes land not ~ull or Empty nodes) are stored; blocks will have variable leng~hst containing between 1 ~nd 8 grandchild node 317~

1~7 packet~ dep2nding upon the numb~r ~f Partial children nodes within that given node packet. In order to ~implify addressing, ~ach node packet is stored together with the memory offset ~rom its own address to the starting address of the block containing the children node packets of the nodes which it contains. The length of that block and the address of each individual node packet within that ~lock may be readily a~certained ~rom the number of P child nodes in the given node packet, as will be seen shortly.
Referring to FIG~RE 17i an arbitra~y node packet 138 containing 8 level n nodes of the octree structure is stored in a 32 ~it word at a location x in memory. Node packet 138 is stored in a w~rd containing two half-word fields: the least ~ignificant 16 bits holds 8 two-bit fields, each of which contains the property value (E, P or F) of one of the ~amily of eight children in the node packet;
the sec3nd half-word field holds an address offset OFPSETA, which points to the block of node packets containing the children of the nodes in node packet 138. Because only three of the eight children nodes in node packet 138 are marked P, the block ~f node packets representing the children of these nodes 1 2 3~ 9 ~

lo~

will comprise only three node packe~s, and will be found beginning at address locati~n x 4 O~FSETA.
~ lock 139 contains nvde packets 14OJ 1~2 and 144, each of which contain the children of one of the nodes in node packet 138. Block 139 is stored beginning at location x ~ O~FSETA. The structure o~ each of node packets 140, 142 and 144 is similar to that of node packet 138. Each of node packets 140, 142 and 144 must likewise point to a block of node packet~ containing the children of the nodes which they contain.
OFPSETA, the address field of node packet 13B, only points to the beginning of block 139.
Thus, node packet 1~0 of block 139 has address location x 4 OFFSETA ~ 0; node packet 142 of block 139 occupies address location x ~ OFFSETA ~ l; and node packet 144 of block 139 occupies address location x + OFFSETA ~ 2. The address of any given node packet may thus be regarded as comprising a base address ~X)~ an offset from the base address lDcating the be~inning of the block containing that node packet, and ~inally, a second offset indicating the position of that node packet within its block.
This second ofset may be easily calculated by merely counting the number of P nodes occurring "before" the parent node in the given node packet as ~3~

~tored in the parent node packet. In the preferred embodiment~ "children" node packets containin~
information about the children of ~he nodes whose property Yalues are stored in the right-most positions in the property value half-word fields of a parent node packet are stored upper-most in the block to which that parent node packet points.
Thus, the children of node 158a of node packet 138 are stored in node packet 1~0 of block 139.
Likewise, the children of node 158b of node packet 138 are stored in node packet 142 of block 139, etc~
Assuming that the location of node packet 138 is x, the address for the block of node packets representing the children of the nodes contained in node packet 138 is calculated as location x +
OFFSETA, as already mentioned. The nodes contained in node packet 138 are scanned from right to left beginning with n~de 158a. Only nodes 1 8a, 158b and 158c in n~de packet 138 will have descendents because ~hey are the only nodes which are marked P. The address of the node packet containing the children ~f node 158a is computed as x + OEFSETA + 0 (the ~econd offset is equal to 0 because node 158a is the first P n~de encountered in node packet i38 as it is scanned from right to left). The address of node packet 142 (containing the children of node 1~ 2 3 J! ~ ~1 l3t J r _ A ._ . ~ ' .. . _ . .. _ _ 1~8b~ is calculated as location x + OFF5ETA ~ 1 (the value of the ~econd ofset equal to 1 becau~e node 158b i~ the second P node encountered in node packet 13~ as it i~ scanned from right to left). The address o~ node packet 144 (containing the children of node 158c of node packet 138) is calculated as location ~ + OF~SETA + 2 (the value of the second offset egual to 2 because node 158c is the third P
node encountered in node packet 13~ as it is scanned from right to left).
None oÇ the nodes contained in node packet 144 of block 139 have descendellts because none of those nodes are marked P. ~owever~ some of the children in node packets 140 and 142 have deseendents and must thus be Eurther subdivided.
The block 145 of n~de packets containing the children of the nodes in node packet 140 begins at memory location x + OF~SFTA + OF~SETB ~note that while for the present calculation three offsets are now reguired for a block address, the preferred embodiment of the present invention simply updates the base register Yalue x so that ~ = x + O~S TA;
thus, for the calculation of the address of any ~iven block of node packets, vnly one simple addition is required).

~ ~
1~17~ .

~ ecause node packet 140 of block 139 contains four nodes ~arked P, block 145 contain four node packets, each one storing the eight c~ildren for one of those P nodes. As before, the offset of ~ach of these fsur node packets within block 1~5 is calculated according to the occurrence of its parent node within node packet 140 as node packet 140 is scanned ~rom right to left. Thus, for example, node packet 150 within block 145 (storing the eight children of node 159c of node packet 140) has address location x + OFFSETA + OFFSETB + 2 ~because parent node 159c with.in block 140 is the third P node encountered as node packet 140 is scanned from right to left~. The addresses of node paokets 146, 14~ and 152 would be calculated similarly.

The node packet~ storing the children of the nodes stored in node packet 142 of block 139 are located in a separate block 153. The address of block 153 is calculated as x ~ OFFSETA + O~FSETC.

Note that block 153 contains only two node packets 154 and 156, because there are only two nodes marked P in node packet 142. The addre~ses of each of node packets 154 and 156 within block 153 are calculated as above.

-~ ~ 3 ~ ~ 9 ~J

It ~ill be understood that node packet 150 within block 145 contains two P nodes, and thus would point to yet another block (not shown) containing two node paokets, the block being stored beginning at memory location x ~ OFPSETA ~ OF~SETB
OF~SET~. Likewise, node packet 156 within block 153 contains a node marked P, so that node packet 156 would point to yet another block (not shown) comprising one node packet stored at memory location x + O~FSETA + OFFSETC ~ OPFSETJ.
As mentioned a~ove, ~ given node pa~ket will not point to a block of node packets if it contains no P nodes. Thus, no me~ningful address offset is stored in such a node packet. Hence, node packets 144, 146, 148, 152 and 154 do not contain of~set values. Nevertheless, space is reserved for offset values in these node packets even though this space is not used. Although this represents some waste of memory storage space, the spaces are retained for uniformity in manipulation of node packets and to provide versatility should the octree ~tructure later be modi ied.
The presently preferred embodiment stores a node packet in a 32-bit word (four bytes) of memory;

sixteen bits are used to store the E, P and F
property values for each of the eight nodes; sixteen 113 ~23~7~

~its are then left ov~r ~or storing address offsets. The preferred embodiment employs ~nly positive address of~sets. Those skilled in the ~rt will recognize that according to this scheme, the beginning of a block of node packets to which a node points must be located in the Octree Encoded Storage block 148 within a range of addresses 0 to 216 from the address of the node packet. While usually enough for lower levels of the octree, this range of memory may not be sufficient to allow addressing of some of the highez levels of the octree (because as the octree is traversed from level O to the lower levels, the amount of required storage space typically increases by a factor of four for each level).
In order to provide a wider addressing offset range, the node packets containing nodes at the higher leYel~ o~ ~he octree may suitably use a "Long" ~elative Address Format wherein the address offset already discussed is stored in an additional word iso that each node packet requires two contiguous words in memory). As discussed above, 16 bits are still required to represent the E, P and F
property values or each of the eight children of the parent node. The 16 bit short address field is available for ~ther purposes, while the relative -~23~L79~

address is stored in the next 3~ bit oontiguous word of memory. Thus, each node packet occupies a t~tal o 64 ~its. The 32 bits of address offset provide addressing anywhere within a range of 232 locations. Depending upon the complexity of the thr~e-dimensional objects stored in the octree, the "long" format method may suitably be used for the first one to several levels of the octree, while the "Short" format previously discussed may be used for the remaining levels o~ the octree. Those skilled in the ar~ could easaly devise a scheme wherein a field in cach node packet could be used to indicate wh~ther the node packet is stored in "long" or "short" format. In one such format, nodes are in long format until a flag bit (c~ntained in the 16 bit offset field) indicate that all lo~er level nod2s are in short format~
The above description is for "packed"
format in which no space is allocated for unneeded node packets in a block. An "unpacked" format may also be used. In the unpacked format, each block contains eight node packets, one for each parent node (even for E and ~ nodes). This facilitates the random addition and deletion of nodes in an octree needed for many operations to be performed on the tree structure. Numerous algorithms for tree ~231791~

11~

management are used. They are ~imilar to the ~emory management techniques on general purpose computer operating systems and are easily devisable by those skilled in the art.
The property information can be stored as additional words attached to each node packet for F
node and possibly P nodes. Alternately, for increased processing speed, they can be stored in an auxiliary memory at the same relative memory locations (so that different address offset values need not be calculated for the additional property memory). Depending on the number of bits needed for each property, the relative addresses may be multiplied by an integer con-tant to locate properties for specific nodes. It will be understood by ~hose skilled in the art that any method permitting random access of nodes would be suitable for storing the octree.
As mentioned previously, an image generator in accordance with the present invention i5 by no means limi~ed to displaying images of objects da~a about which is acquired by a computed tomography scanner. Those skilled in the art could readily devise a vari~ty of different techniques which could be used to define objects to be imaged. For instance, the object to be imaged could be defined `` i23179~D

by data input by ~ user to an automated interactive input devi~e which analytically specifies an object to be i~aged. Such an analytically-specified object might be defined entirely automatically by an automated device, partially by user specification and par~ially automatically by the automated device, or entirely by the ~ser. The automated device could then produce and store the ~ctree structure in the Octree Encoded Object Storage block 140 (of FIGURE
15) .
Alternativelyl the Octree Encoded Object Storage block 140 could be replaced by a function block which both analytically specifies the object to be displayed and produces node packets on demand.
Such a ~un~tion block would not have to store an octree structure at all, since i~ ~uld compute the property values of a demanded node packet by merely comparing the location of ~he nodes in the three-dimensional universe with the position of the analytically-defined object ~o be displayed. Those skilled in the art could readily devise various methods of implementing such a function box to provide flexibility in a variety of different applications.

~ 1 23 1 7~

T~E ALGORITHM EXECUTED BY
T~E IM~GE DISPLAY PROCESSOR

Before describing ~he operation of the Initiali~ing Controller block 160 of FIGURE 15, it is necessary to familiarize the reader generally with the method in which the Image Display Pr~cessor block 152 of FIGURE 15 accesses and tests nodes by traversing the octree and then comparing those nodes with windows obtained by traversing the guadtree.
- Once the general algorithm is understood, the specific initializing parameters p~oduced by the Initializing Controller block 160 will be discussed in detail.
While the general algorithm executed ~y the Image Display Processor block 152 has already been descri~ed in some de~ail, ~ more precise description is expressed by the following PASCAL program:
Proce~Lre PROCESS(NODE3 begin If NODE intersects any non-FULL window then I NODE is FULL then begin ~or WIND~ ~ n~n-FULL intersecting window be~in TERM(NODE,WINDOW) end end else beg i n PROCESS(CHI~D(NODE~) end else NODE ~ NEXTlNODE) .J

~3~7~

end en~~~
procedure TERM~NODE,~INDOW) , bealn if ~INDOW is EMP~Y and encloced by NODE then ~Q~
PAINT WINDOW
mark WINDOW ~ULL
end else for I:=l to 4 do TERM (NODE,CHILD2~WINDOW~I))) end end end rocedure CHILD(NODE~
(~ subdivides NODE into its children and returns first non-empty child ~) procedure CHILD2(WINVOW,I) (* returns child number I of WIN W *) procedure NEXT[NODE) (* returns next node in front-to-back t~aversal sequence, i.e. the fir~t non-empty node in sequence not a descendant of NODE *) The variable NODE stores a single node in the octree structure, and is initialized to the root node (the node at level 0) before the program begins. The variable WINDsW stores a single window in the quadtree structure, and is selected during algorithm operation from the our overlay windows associated with ~he node currently being processed.
Vepending upon the ~ize of the node projection (as deter~ined by the user specified scale factor), the overlay i5 ini~ialized at a specific level relative to the root of the octree. This initialized level ~ 12317~9~

11~

is the lowest level such that the bounding box of the node projection is the same size or smaller lin each dimension) as a window at ~hat level. The initial overlay is~ of course, composed of the four windsws at that level which enclose the projection of the octree root node (the universe~.
The algorithm is entered at the procedure PROCESS, and is initially passed the root node. The algorithm first determines if the node projectisn intersects any non-full window in the current window overlay ~any of the four). If it does, that node i5 "processed." If the node do2~ not intersect any non-full window, then the next non-empty node in ~he front-to-back traversal sequence is obtained by the procedure N~XT. The algorithm terminates when NEXT
is called with the root node.
As mentioned above, if the node does inter-sect a non-full (i.e. Empty or Partial) window, then ~hat node is "processed." First, it is determined whether the node is Full. If it is not ~ull, then it must be a Partial node at some level other than the bottom of the octree (because the procedure NEXT
returns only non-Empty nodes)~ and that node is subdivided into its children and the children processed (when PROCESS calls itself and passes itself ~he children of the current node). If the -` 123179~

node is Full then it will not be further ~ubdivided;
ratherr the ~indows in the overlay will be subdivided to locate all o~ those windows c~mpletely enelosed by the Full node. ~owever, the windows are not subdivided unless they are either ~mpty or Par~ial (since Pull windows have already been painted and will not be painted again). If the window is not Full and intersects the node, then the window is processed by the procedure TERM. It is only during the procedure TERM that windows completely enclosed by ~ull nodes are located and painted (which is the output generated by the algorithm).
Procedure TERM first tests to see if the window passed to it is Empty and enclosed by the node. If it is, then that window is painted and is marked Full (so that it will not be painted again).
If it is not Empty o~ not enclosed by the node, then either it must be a Partial window or it is not enclosed ~y the node being processed, both conditions indicating tnat at most only some of the descendents of the window are to be painted. In such a case, the window must be further subdivided to locate all of those windows which are both Empty and enclosed by the node. This is done recursively for each of the four children (and all of the 3 1 7 ~ ~

descende~ts of each of ~hose chiidren~ o~ ~he window in the loop section of the procedure ~E~M wherein the procedure calls itself.
Those skilled in the art will recognize that the recursive nature of this algorithm permits the algorithm to proces~ all o~ the levels of the quadtree and the octree. To implement a recursive process such as TERM, all of the present values of all of the variables of the recursive procedure are suitably ~tored in a Last-In-~irst-Out (LIFO~ stack, after which all of the variables are reinitialized 50r set to the appropriate par~meters passed to the procedure by ~he statement call:ing it~, and the procedure is executed again from the beginning with these new variable values. When the procedure completes a given recursion, it reloads all of its variables to their former values (obtained from the stack)~ ,~nd resumes exeeution exactly where it le~t off before it called itself.
Those skilled in the art will also understand a LI~O stack to be a common general structure used in computer science. A LIFO stack is a variable-length storage structure used to temporarily store a plurality of values. The stack has two operations, PUS~ and POP. A PUSH operation places a value at the "top" of the stack. A POP

~ 1~3~7~

operation remoYes a value from the ~top" of the ~tack. The last v~lue placed at the top of a ~ta~k by a P~S~ operation will be the first one r~mbved from the stack by the next POP operation. (Thus, a LIFO stack may be analogized to the simple devices ~ommonly found in cafeterias to store empty food trays; the last tray placed in such a device remains at the top and is the first one removed when a tray is needed.) Each time the procedure TERM calls itself ~thus traversing down one level of the quadtree), a P~5H operation i5 perormed on the stack to store the present values of the variables used by TERM. Likewise, each time the procedure TERM completes processing a given recursion and returns t~ itself (i.e~ returns back up the quadtree structure one level), a POP operation is performed on the stack to retrieve the old values of all of the variables of TERM so that the procedure can begin executing right after the point where it called itsel~.
It will be understood that the algorithm shown is ~ctually recursive (it calls itself) in two places: the procedure PROCESS calls itself, and the procedure TERM calls itself. Whenever PROCESS calls itself, both nodes and windows are subdivided, i.e.

~oth the octree and the quadtree structure are --` 12317~1~

traversed one level down simultaneouslyO Nodes are subdivid*d explicitly because PROCESS calls i~elf and pas~es itself the children of the current node. ~indows ~re impli~i~ly subdivided in that WINDOW is always ~elected from the four overlay windows at the quadtree level comprising windows of a size that are jU5t large enough to contain the bounding box defined by the projection of the node being processed~ While the subdivision of windows along with nodes is not essenti~l to the operation of the algorithml this feature makes the algorithm far more efficient by preventing a quadratic increase in the number of win~ows to be tested with respect to every F node.
When the procedure TERM calls itself t only the quadtree structure is traversed one level down, while the octree level remains constant. This can be intll..itively understood by realizing that the procedure TERM is ~alled only once a Terminal node has been located, meaning that the node cannot be further subdivided iit does not have children in the octree).
~ eferring to ~IGURES 18(A)-lB(B), shown is a more detailed ~low ~hart of the algorithm in accordance with the preferred embodiment of the present invention. The ~low of this flow chart is `-' I 23 1 7 from top to bottom, and is entered at the entry point 162. Block 1~8 reads in the next node pa~ket.
Decision block 170 tests to see if there are ~ny non-Empt~ nodes le~t in the node packet. If so, biock 172 obtains the next non-Empty node in the traversal sequence in the node packet read in by block 168, and locates the window overlay in the ~uadtree structure (i~e. those contiguous four windows in the quadtree structure which completely enclose the bounding box defined by the node).
Block 17~ performs the BBOX test, suitably on all four windows in the window overlay simultaneously, to determine which of the four windows passes the BBOX test lat least one of the four windows must pass the BBOX test because of the definition of the window overlay~.
The algorithm proceeds down to decision block 176, which determines if there are any non-Full (i.e. E or P) windows left to be processed of those w.~ndows which passed the BBOX test. It will be recalled that Full windows are never painted, and thus are quickly disposed of by decision block 176.
If no non-Full windows are left, then the algorithm jumps back to decision block 170 to get the next node in the node packet, if there is one.

1 23 1 791~

I~ there are E or P windows left of the windows ~hich passed the BBOX test, block 178 obtains the next such window according t~ the traversal sequence by which the quadtree is accessed. Decision block 180 performs a PI test on the ~one~ window obtained by block 178. If the window fails the PI test, then the algorithm jumps back to decision block 176 to determine if there are any non-~ull windows left, and if there are, to obtain the next such window. If, however, the window pa ses the PI test, decision block 182 tests if the window level i~ at the bottom level of the quadtree.
~ window at the bo~tom level of the quadtrPe [i.e. at the level of resolution of Image ~isplay ~lock 154 shown in FIGIJRE 15), cannot be subdivided, so it must ~e handled dif~erently. If the wind~w is at the bottom level, block 190 paints the win~low to the Image Display block 154 of FI~URE
15, and marks the window F in the quadtree. It will be recalled that once a window is marked P~ it will never be painted again (i.e. no F windows will ever reach decision block 188 because they will be discarded b~ block 178). It will be understQod that it i~ somewhat ~rbitrary what action is taken for windows at the bott~m of the quadtree. Another . 12317~

presently pre~erred embodiment of the present invention only paints ~indows a~ the bottom level of the quadtree having a center point which int~sects the node projection ~50 that some area of the window is guaranteed to in fact intersect the node projec-tion). In ~act, for windows at the lowest level, the PI test can test the center point of the window rather than the window it~elf. ~or P nodes in the octree, the above method makes the ~ssumption that the node is, in fact, an F node. Several other methods could be used. The window could never ~e written in such a situation (i.e. assumed to be E), or P nodes could be further subdivided with the window center used for the PI test. Alternatively, the su~trees of the P node could be traversed to determine if more than half of the volume which they represent i5 occupied by the object (F nodes). If so, the node is assumed F. If not, it is assumed Those skilled in the art could easily devise other "center point intersection tests" analogous to the tests previous~y described. ~xperience has shown that the exact window termination method used ic not of great concern in most rases.
~ he algorithm jumps back to decisi~n block 17~ to process any remaining non-Full windows which passed the BBOX test from both block 190 and block - - . ~ . --~ 12317~0 !

l~D (if the window ailed the PI test). As mentioned ~bove, because block 190 is executed only ~or windows at the bottom level of the quadtr2e, its function is somewhat arbitrary (i.e. it will not greatly aFfect the image generated if a different action other than that described is taken for windows at the level of resolution~.
If the window is not at the bottom of the quadtree, it may be further subdivided. Decision block 1~1 tests to see if the node is a Partial node. I~ the window is P, block 184 causes the current node packet (as well as information concerning which nodes in the node packet have been processed and the geometry of their common parent node projection~ to be PUSHed onto a LIFO node stack, and likewise causes the current window packet (including information a~out which windows in that window palcket have already been processed, which ones have passed the 3BOX test but have yet to be processed, and the geometry o~ the window packet) t~
be PUSHed onto a LIFO window stack. While these stacks are not shown, they function as described previously. The algorithm recurses/ i.e. it j~lmps back to block 16B to obtain the node packet containing the children of the node just PUSHed onto the node stack, and then processes that node packet 3179~

.o~ ~hildren with ~ new window overlay of four windows, each of which i~ a ~hild of one of the ~our windows PUS~ed onto the window stack.
After processing these children nodes and windows (and recursively, all of their descendents), a point will ~inally be reached, as tested for by decision block 170, when there are no nodes left in the child node packet. At this point, decision block 164 tests whether the node packet just procesced was at level 1 of the octree; if so, the octre2 has been completely traversed, and the algorithm exits through exit point 166. If the node packet just processed is not at level 1 of the octree, the algorithm is not finished, and block 186 POPs the parent node packet and its associated geometry from the node stack, POPs the parent window packet and its associated geometry from the window stack, and resumes processing the node and window packets exactly where processin~ was left off at block 191. Thus, decision block 170 then determines if any non-Empty nodes are left in the POPped node packet, the next node ~rom the node packet and the appropriate window overlay for that node is obtained by block 172, etc. Block 166 also updates the quadtree structure by marking the parent windows of 1~9 the overlay window~ P or F (as appropriate) if any descendants had been painted.
If the node does not satisfy decisi~n block 191, the node is ~ull, and the algorithm mus~ now search for windows which are completely enclosed by this Full node, Once the algorithm reaches this point, it likewise has located a window which intersects the Full node (tested for by block 180~.
Thus, some of the descendents of the intersecting window ~re enclosed by the node projection. (The window itself cannot be enclosed by the node projection because the window :i8, by definition, larger t.han the bounding box of the node projection).
Block 192 PUSHes the window onto the window stack, thus subdividin~ the window into its four children ~the node is not subdivided at this point). The four children form the "overlay" but, in fact~ this "overlay" is no l~nger a legitimate overlay because it won't, in general, enclose the node ~the node is now too big because it wasn't subdivided). Thus, the window "overlay" located by block 192 at this point is in act the 4 children of the window just PUSHed, (unlike the general c~se in blo~k 172 where the overlay need not be, and generally is not, comprised of 4 windows having the ~ 1 ~3 1 7~

...... .

1~0 ~ame parent). ~lock 194 performs the BBOX test on the new window ~verlay" ~f four children wind~ws.
Decision block 196 then determines i~ there ~e ~ny non-Full ~i.e. E or P) windows which passed the BBOX
test remaining in this overlay. If so, then block 198 obtains the next such window according to the traversal sequence used to traverse the quadtree structure.
Decision block 200 tests the window obtained by block 198 for the PI test. If the window fails the PI test, the algorithm jumps back to block 196 to obtain the next non-Full window which passed the 8BOX test. If the window passes the PI test, decision block 2Dl te~ts the window to see if it is Empty. If th~ window is not Empty, it must be Partial (since block 198 discarded any Full windows~. P windows cannot be painted, but must be further subdivided to locate its E descendants.
Becaus~ no windows at the bottom of the quadtree can be Partial (all terminal windows are either E or F), all Partial windows can be subdivided. If the window is Partial, the algorithm jumps back to block 192 to subdivide tAe window into its four children.
If deci--ion block 201 determines that the window is Empty, decision block 202 tests the window for enclosure (E test~. If the window is enclosed 131 ~3~

by the projection of the current (P) node, iS is pain~ed to the ~age Display block 154 of ~IGURE 15 and is marked ~ in the quadtree memory (so it will never be painted again). If the window fails the E
test, it ~ust be further subdivided, if possible, to locate those o~ its descendents whieh are completely enclosed by the node projection. At the bottom level of the quadtree, the E test determines enclosure for the center of the window rather than for the window itsel~ . Thus I if the ~enter of a bottom level window is enclosed by the ~ node projection, it passes the E test and is painted.
Decision block 206 determines if the windo~ is at the bottom o~ the guadtree; if it is, the window is discarded and the algorithm jumps back to decision block 196 to prDcess any rema:ining windows. If the window is no~ ~t ~he bottom level o~ the quadtree, it is ~ubdivided into its children ~y block 192.
If decision block 196 determines that there are no non-Pull ~indows remaining in the current window packet which anterseet the node projectivn, the algorithm proceeds to decision block 208, which determines whether the window level ~nd the node level are equal. IP the window level is still below the node level, then the algorithm must traverse yet another level back up the quadtree (by performing 72~179~

another POP ~n the window stack in blo~k 209). The windows so PO~ped must then be processed, beginning at the point where processing left off before they were PUS~ed by block 192 (a POP includes upd~ting the quadtree by marking the parent of windows just painted (or their descendants~ P or F, as appropriate)~ ~owever, if decision block 208 determines that the window and node levels are equal, then the quadtree has been completely traversed below the level of the quadtree that the algorithm was processing before block 192 was executed. The algorithm returns to block 176 to determine if there are any non-Full windows left to ~e processed at this level.
It will be understood that blocks 162-191 of FIGUR~ 17 approximately correspond to the procedure PROCESS of the PASCAL program, while blocks 192-209 approximately correspond to procedure TERM of the PASCA~ program.
Referring to FIGURE 19, sh~wn is a modi~ication of a portion of the flow chart shown in FIGURE5 18(A)-lB(B) to include the cut plane test.
Dec;sion block 175 is added between block 174 and decision block 176 to determine whether the cur~ent node is at least partially within the region to be displ~yed defined by the cut plane (i.e. either ~179a entirely within the r~gion, ~r partially within it~ If it is not, the node is disearded and the algorithm ju~ps back to decision block 170 to process remaining nodes in the node packet. If the current node is at least partially within the region tQ be displayed, the algorithm proceeds to decision ~lock 176, as before.
Decision blo~k 183 is inserted between decision blocks 182 and 191~ and determines whether the current node intersects a cut plane. If the node does not interse~t the cut plane, then it must lie entirely within the re~ion to be displayed, and the algorithm proceeds as before to block 191.
~owever~ if the node is intersected by a cut plane, it must be ~urther subdivided to determine which of its descendents lie within the region to be displayed ~nd which lie outside of that region. The algorithm jumps to block lS4 to further subdivide the node ~and the windows).

INITIALIZING CONTROLLER

The Initializing Controller block 160 of FIGURE 15 has ~everal ~asic functions. First, the Initializing Controller block performs linear transformations on the three-dimensional universe 3~7~1~

according to parameters input by a user through the Int~ractio~ ~ith User bl~ck 150. The Initi~lizing C~n~roller block 160 then projects the thr2e-dimensional universe onto the two-dimensional view plane. Finally, the Initializing Controller block 160 performs a "protractor" function on the projection of the three-dimensional universe in order to determine the geometric relationships between parent node projections and child node projections, parent windows and children windows, and between the projection of the three-dimensional universe and the view plane origin. From these calculated geometric relationships, the Image Display Processor block 152 can calculate the geometric relationship between windows of the Yiew plane and the projection of any node in the three-dimensional universe.
The flow chart shown in FIG~RES 18(A)-18(B) assumes that the geometric locations of a given node within t~he three-dim~nsional universe and the dimensions of that node can be obtained from the level in the octree ~tructure at whieh that node appears and knowledge of which node is the parent of that node. Likewise, the flow chart of FIGURES
18(A)-18(B) assumes that the location of a given window ~n ~he view plane and the dimensions of that 3 ~ 7 window can ~e obtained .~rom the level in the quadtree s~ructure which that window appears and knowledge of which window is ~he parent of that window. These geometric locations and dimensions are required for the BBOX, PI and E tests, the cut plane test and the PAINT blocks.
The calculations performed by the preferred embodiment of the present invention to obtain this location and dimension information are in ~act that simple (those skilled in the art will understand that if such calculations were complex, the generation of an image would re~uire a great deal of time). 8ecause the geometry of the eight children n~des with respect to their parent node is precisely the same ~or ~ny level of the ~ctree structure, once the geometric relationships ~or one level are derived ~or a selec~ed view, they can be applied to any level of the octree. M~reo~er, since the dimensic~ns of any child node are exactly one half those of its parent node, the geometry of child nodes to parent nodes for adjacent levels of the octree stsucture are all related by a ~actor of 2.
Likewise, because the geometric relation-ship between four children wind~ws and their parent is precisely the same ~r any level in the quadtree structure, once the geometric relationship is ~ 1 23 ~ 7~

deriv~d for one level of the quadtree, it can be applied to any given level. Analogously, $ince a child window has dimensions exactly one-half that of its parent, the geometric relationships between children-to-parent windows for two adjacent levels of the quadtree structure are related by a factor of 2.
It will be understood by those skilled in the art that simple calculations such as addition, subtraction and magnitude comparison can be changed by a ~actor of 2 by simply shifting, using shift registers, the operands used for those calculations.
Thus, once the relatively complex descriptions of the geometric relationships between child-to-parent node projections and child~to-parent windows are derived9 the preferred embodiment of the present invention utilizes those derived parameters for every l~vel of the octree and the quadtree, respectivcly, merely shifting those parameters an appropriate number of places to the left or to the right Idepending upon the level of the oc~ree or quadtree being accessed). The derivation of these parameters in the ~irst place is performed by the Initializing Controller blo~k 160 of FIGURE 15, which then initializes the Image Display Processor block 152.

3179~

Referring tD ~IGURE 20lA~, hown is a graphical illustration of the three-dimensional universe 32 (shown in ~IGURE l(A)) pr~jected onto the two-dimensional view plane 66 for a given viewing angle. ~efore the Initializing Controller block 160 can relate any of the geometry of the projection 2il Qf the three-dimensional universe 32 to the view plane 66, it muct determine the orientation of the three-dimensional coordinate system ~x, y, z~ with respect to the two-dimensional coordinate system ~x', y'~ of-the view pl~ne.
The Interaction With User block 150 shown in FIGURE 15 suitably permits a user to per~orm a variety of linear tran~formations of the three-dimensional universe with respect to the view plane 66. ~or instance, a user may translate the origin 210 o~ the projection 211 to any point on the view plane 6~. The Interaction With User block 150 further permits the user to rotate the three-dimensional c~ordinate system (x, y, z) about a user-defined point in the three dimensional universe with respect to view plane 6~ to any given rotational orientation. Finallyt a user may scale the dimensions of the three-dimensional universe (the Interaction with User block 150 suitably permits indepen~ent scaling for each of the x, y, z - ~ ~ 2 ~

dimensions). Another possible linear transforma~ion that ~ould be performed by the Initializinq Controller block is skewing of the three-dimensional universe in each of the x, y and z dimensions.
Shown in ~IGURE 20(A) is a three-dimensional coordinate system for a given translational and rotation~l orientation and having a given set of scaling factors with respect to the two-dimensional view plane 66.
As shown in FIGURE 20(A), the view plane comprises sixteen windows, each of which are the size of a Display Screen 212 (that portion of the view plane 66 which is actually displayed ~y the I~age Display block 154 shown in FIGURE 15~. The quadtree organization is not impo~ed upon the entire view plane 66, but only that portion of the view plane of interest, i.e. Display Screen 212. View plane 6~ is larger than Display Screen 212 to permlt a projection 211 that is likewise much larger than Display Screen 212 (so that, for instance, the projection of the three-dimensional object may be scaled to permit generation of "close-up" ima9es).
Referring to FIGURES 6(D), 20(A) and 43(A), Display Screen 212 comprises window number 12 of the ~ x 4 window array while still permitting window overlays for the largest node projections of the universe.

~317~1~

The origin 104 of the view plane 66 may suitably be assigned to the lower left-hand corner of Display Screen 212. ~he view plane 66 i~
dimensioned in pixels (the smallest unit of ima~e information that will be accepted by the Image Display block 154 o~ FIG~RE 15~, Display Screen 212 suitably having dimensions of 51~ x 512 pixels.
Dimensions in the three-dimensional coordinate system are not measured in pixels, but rather are indexed in terms of node number and level. Fsr a given viewing angle and scaling factor, the Initializing Csntroller block 160 computes the various dimensions of the projection 211 of root node 32 in ~nits of pixel width scaled up by a factor of a power of two (such as 256).
~henever the geometry of the three-dimensional octree universe is to be compared with the ~eometry of the view plane 66 f the former is converted into scaled pixel widths.
FIGURE 201A) also shows the r~lationship between the projection 211 of three-dimensional universe 32 and the two-dimensional view plane 66 as defined by three offsets NPD~, NPDl and NPD2, each of which is constructed from the view plane ~rigin lO~ to perpendicularly intersect one of three lines defined ~y three edges of projection 211O Three--~` 12317~

l~o dimensional universe 32 suitably.defines a parallelepiped, three intersecting ~rthogonal edges of which define the three-dimensional orthogonal axes x, y and z. The position of the projection of the x, y and z c~ordinate axes onto view plane 6S
must ~e defined with respect to the x' and y' coordinate axes of the view plane in order to define the position of the projection of any of the nodes in three-dimensi~nal universe 32 onto the view plane.
Although it will be understood that there dre several possible methods of defining the position of the projection of the x, y and z axes with respect to the x' and y' axes, the presently preferred embodiment o~ the present inventi~n defines three additional lines each of which is defined by an edge of universe 32 and then computes the dis~:ance from each of these lines to ori~in 104 of view plane 66. The three edges of universe 32, D0, Dl and D2, are selec~ed as follows:
Edge D0 is that edge of universe 32 which is parallel to the z axis and which intersects the x axis;

~23~
1~1 Edge Dl is that ed~e which is parallel to the y axis and whi~h inters~cts the z axi 5; and Edge D2 is that edge which is parallel to the x axis and whi~h intersects the z axls.

A line segment NPD0 is constructed from origin 104 of Yiew plane 66 to perpendicularly inter ect the projection of the line deined by edge D0. Likewise, a line segment NPDl is constructed from origin 104 to perpendicularly intersect the projection of the line defined by edge Dl, and a line segment NPD2 is constructed from origin 104 to perpendicularly interseet the projection of the line de~ined by edge ~2. ~PD~-NPD2 are constructed in this manner regardless o~ the viewing angle (i.e.
the oriPntation of the three-dimensional coordinate axes with respect ~v the two-dimensional c~ordinate axes~. Edges D0-D2 are suitably used for nearly all calculations involving node geometry (since every edge of the node projection is pa~allel to one ~f these three ed9es)~ while NPD0-NPD2 are used or nearly all cal~ulations which compare the loc2~ion of a node projection to the location of a window.

14~ 7~

A graphic illustration of geometric measurements required for the ~BOX test i5 ~hown in YIGURE 20~ A ~ounding 90x 74 defined on view plane 66 by the projection 211 of the entir~ three-dimensional octree universe 32 is constructed as previously described. This ~ounding ~ox 74 suitably has origin 76 ~t the point (NPX, NPY), a dimensi~n in the x' direction of 2bx, and a dimension in the y' direction of 2by. It will be understood that the dimensions of Bounding Box 74 for any child node projection at a given octree level for a given view will be the same, althou~h the origin 76 of that Bounding Box will, of ~ourse, change by an offset.
Moreover, the dimensions of Bounding Box 74 of a child node projec~ion will be exa~tly one-h~lf th~se cf the projection of its parent because the dimensi~ns of the child node itself are exactly one-half those o~ its parent ~for example, the dimen~ions of the ~ounding boxes defined by the projection of each child node of root node 32 will be bx and by). Thus, once the dimensions of the Bounding Box 74 for the projection 211 of root node 32 ar~ determined~ the dimensions of the B~unding Box for ~ny node in the octree structure may readily be arithmatically calculated as a functiGn of the node level.

~3~79~

Re~erring to ~IG~RE 20(C3, shown is a gr3phi~ illustration of the of}sets in the ~' direction of the left-most edges of the bounding boxes of the projections of e2ch of the eight children nodes of root node 32 from the left-most edge of Bounding B~x 74. The origin o$ each bounding box may ~e defined as the origin 76 of the parent bounding box plus a positiv~ offset ~possibly 0) in both the x' ~nd the y' direction. As is shown in FIGURE 7, the origin 76 of any bounding box may be written as (NPX + ax, NPY ~ ay). The offsets ax and ay will, of course, be different for each of the children nodes. The calculations shown in FIGURE
20~C) must be made in the y' direction as well as to obtain analogous ay off~ets.
Referring tv FIGURES 4(A) and 20(C~, the eight children nodes of root node 32 are numbered 0 to 7 laocording to the seven-to-zero traversal sequence). The left edge of a bounding box for any node defines a line parallel to the y' axis passing through the left-most vertex lwith respeot to the view plane) of the projection of that node onto the view plane ~which vertex is the left-most one will depend upon the viewing angle). Thus, line 74b is parallel to the y' axis of view plane 66 (and -` 123i79~

analogously, line 74a is parallel ~o the x' axis of the view plane).
~ he left-most vertex of root node projection 211 is 214(1), the lower left vertex of the projection. Because of the symmetry of the thre~-dimensional uniwerse, the left-most vertex of the projection of each of the children of root node 32 will likewise be the lower left vertex of its projection. These vertices are labelled 214~0) through 214t7~, where, for instance, the left-most vertex of the projection of child node 6 is 214(6).
To calculate the offsets from the left edge 74b of the boundinq box 74 of root node projection 211 to the left edye of the bounding box defined by the projectiun of any given child of root node 32, a vertical line is first constructed through ~he left-most vertex of the child node projection of inter2st. A hori20ntal line segment perpendicular to both the vertical line 74b defining the left edge of bounding box 74 and the vertical line passing through the left-most vertex of the ~hild node projection is then constructed between the two vertical lines. The length of this line ~egment is the offset from the left edge 74b of the parent node projection bounding box to the left edge of the child node projection bounding box. ~or example, - .

~23~'~9~
1~
.

the len~th of line segment ax4 is the offset in the x' direction from pasent bounding box 74 to the bounding box defined by the projection of child node 4. Similar offsets ayO-ay7 are constructed in the y' direction, suitably between the lower edge 74a of bounding box 74 to horizontal lines defined by the bottom-most vertex o each of the projections of the eight ~hild node This process of calculating ax and ay offsets results in sixteen different values ~axO-ax7 and ayO-ay7), one for each of the bounding boxes defined by the eight children node projections in both the x' and the y' directions. (It will be understo~d that for the vi2wing angle shown, axl = O
because vertex 214(1) happens to be the left most vertex f~r both root node projection 211 and the projec~.ion o~ child node l; analogously, ayS=O for the viewing angle shown).
The origin of the bounding box defined by any child node projection may be calculated by addirag the ax and ~ offsets corresponding to that child 'co the origin of the bounding box defined by the parent child node projection (thus, the origin of the bounding box de~ined by the projecti~n of child node 5, for example. is (NPX + ax5, NPY
ayS).

~t~ 3 1~6 Once the ~izteen ~x and`ay offset v~lues have been cal~ulated for the children of root node 32, the ax a~d ay offset values for ~he projection of any ~esc~ndent of the root node may be derived from these values ~s a function of child number and node level. For example, the ax offset value from j the origin of the bounding box of the projection of child node 1 to the origin of the bounding boxes of the projection of the children of child node 1 (i.e.
the grandchil~ren of root node 32) are simply one-hal~ of the ax offset values shown in FIGURE 20(C) (because the dimensions of any child node are exactly one-half of those of its parent3. ~ach time the octree structure is travers~d downward, the proper ax and ay offsets are simply divided by 2 (i.e. shifted right one place) and added to the or$gin of ~he bounding box defined by ~he parent node projection to obtain the bounding box origin of the projection of the selected child node.
Recursion is thus used to calculate the origin of the bounding box of the projection of ~ny node in the three-dimensional universe. The bx and by values shown in FIGURE 20lB) are also shifted one position to the right to accurately reflect the dimensions of the bounding box of interest.

~23~l7~

~ he bit~ shifted out of the value registers such as bx are shifted into an underflow register and are thus saved. When the octree structure is traversed upward, the values are multiplied by two by shiftinq left one place. The saved lower order bits are, of course, shifted back into the register on an upward~: transversal of the octree structure.
It will be recalled that the location and dimen ions of the bounding box only provide sufficient information about the geometry of a node projection with respect to the view plane to perform the B~OX test. The PI test a~d the E test both require information about the location of the six exterior edges of the node projection. In addition, the E test requires information about the location of the three interior face edges of the node projection. Referring to FIGURES 21tA)-21~C~, shown are qraphic illustrationc of offsets from the DO, Dl and D~ e~dges of the projection 211 of root node 32 to the DO, Dl and D2 edges of the projections of the ei~ht children nodes of the root node. These offets permit the projection of any child node to be located relative to the projection of it.s parent node.
Referring to FIG~RE 21(A), the offsets from the DO edge of the projection 211 of root node 32 ~23~7~) 14~

(a~ defined in FIG~RE 20(A)) to the DO edges of the projections of each of the children of node 32 is shown. The analogous offsets for Dl and D2 edges are shown in FIGURE 21~B) and FIGURE 21(C~, respectively. Thus, ~or instance, the location of the DO edge of the projection of child nodes 2 and 3 of root node 32 is giYen by NPDO ~ NDOOF~(2) (where NPDO in PIGURE 20(A) is the location of edge DO with respect to ~he origin of the view plane). Likewise, the loc~tion of edges Dl of the projection of nodes O and 2 are given by NPDl + NDlOFF(l), while the edges D2 of the projection of nodes 2 and 6 are given by NPD2 + ND20~F(2~. In this way, the projec~ion of any child node of any given parent node may be located with rcspect to the projection of the parent node. Note that just as for the ax and ay off et values, ~he offsets shown in PIGURES
21(A)-21(C) are suitably divided in half (shifted to the right) in order to determine the locations of, or example, the children of child node 2, and would be further divided by 2 for each further subdivision of ~odes.
As discussed ab~ve, the interior face edges as well as the exteri~r node projection edges must be located for the E test. Reerring to FI5URES
21(D)-21(F), shown are graphic illustratior,s of th - -location of interi~r face edges of the proje~tion of an arbitrary child node ~ root node 32 ~not the root node its~lf) with respect ~o the DO, ~1 and D2 edges v~ that child node projection. Referring to ~IGURE 21(D), shown are the offsets from the DO edge of the projection of a child node 217 of root node 32 to the two other edges of the projection of the child node parallel to edge DO which are necessary for locating the visible faces of the projection of the child node. FDIAGO i~ the length of a line segment constructed between and perpendicular to a line defined by the DO edge of the projection of ~hild node 217 and a line defined by the edge labelled 216 which separates two of the faces of ~he pr~je~tion of the ~hild n~de. Likewise, NDI~GO is the length o~ a line segment constructed between and perpendicular to the line defined by the DO edge ~f the projection of child node 217 and a line defined by an edge 218 of the projecti~n of child node 217. It will be understood that edges 216 and 218 are the two edges of the child node 217 parallel to edge W whieh are projected onto the view plane 66 f~r the viewing angle shown (there will be, at m~st.
two such lines, with a third parallel edge being located ~behind" the node and hence not par~ o~ the projection). Lihewise, ~DIAGl and NDIAGl shown in ~ 23 11 791~1 ~s~

FIGURE 21~E~ are ~nalogous offsets from the Dl edge o~ the projecti~n of the child node 217, and FDIAG2 and NDIAG2 shown in FIG~RE 21(F) are analogou~
offsets from the D2 edge of the projection of child node 217.
It i~ noted for completeness that some of the offsets shown in FIGURES 21~D)~21(~) are actually ~edundant, since they correspond to some of the offsets shown in FIGURES 21~A)-21(C). The preferred embodimcnt, of course, does not recalrulate redundant offsets again.
From the offsets shown in FIGURES 21(A)-?1~) the location of any given edge of interest of any child node projection may be located with respect ~o the D0, ~1 and D2 edges of its parent.
Referring to FlGVRES 4tA), 8, 21(A)-21~F), locations of the exterior edges and the interior face edges of, for example~ the projection of child node 2 of root node 32 may be c~lculcated as f~llows:

Edge 11 = NPD0 ~ NDOOFF(2) = NCD0 tthe D0 edge of child node 2) Edge 12 = NPD2 + ND20FF( 2 ) = NCD2 ( the D2 edge of child node 2) . 123l790 ~dge 13 - NPDl ~ ND10~`1) = NCDl (the Dl edge oP child node 2) Edge 14 = NCDO ~ NDIAGO

Edge 15 = NCD2 + NDIAG2 Edge 16 = NCDl ~ NDIAGl Edge 7 = NCDl ~ FDIAGl Edge 8 = NCDO + FDIAGO

Edge 9 = NCD2 + FDI~G2 Referring to ~IGURES 2~(A)-22(BJ, shown are graphic illustrations of the geometry required to perform the cut plane test described previously in conjunction with FIGURE 14~B). Referring to ~IGURE
22(A), æk offsets from ~he left-most vertex 228~1) (with respect to the k ~xis) of the projection 226 of root node 32 onto the cut plane test plane to the left-most vertices of the pro~ections of each of the children nodes of the root node onto the test plane are shown. These of~sets are calculated by constructing a line 74k perpendicular to the k axis 123~7~

15~

(~nd therefore parallel to each of the cut pl~nes 120 and 122 shown in ~IGURE 14~B)) passing through the left-most vertex oE the projection 226. A line i5 constructed parallel to line 74k passing thrsugh each of the left-m~st vertices 22B(0) 228~7) of the children node projections of the root node. Line segments are then constructed perpendicular to and between line 74k and each of the lines passing through the child vertices ~thus, the offsets depicted in PIGURE 22(A) are somewhat similar to the bounding box offsets shown in FIGURE 20(C)).
The point dt which line 74k intersects the k axis is defined as NPK. To det~rmine the location of any child vertex, it is necessary only to add the appropriate offset to NPK. Thus, for instance, the k coordina~e of the left-most vertex of the projection of ~hild node 4 (numbered ~s in FIGURE
4~A) ) C~ntV the test plane is given by NPK ~ ak4.
Because the cut plane te~t requires only inormation about the k coordinate of each of the vertices, ~imilar calculations do not have to be performed for coordinates orthogonal to the k axis (as was necessary for the bounding box offset~).
Referring to FIGURE 22(B), the distance along the k axis between the left-most vertex of the projection 230 of a child node of root node 32 onto 3179~

the test plane to the right-mos~ vertex is shown.
This offset, ~DIAG, is calculated by constructing a line parallel to line 74~ shown in FIGUR~ 22~A) (and thus perpendicular to the k axis) passing through the right-most vertex. Because this distance is exactly the same ~or each of the children node~ of root node 32, it does not matter which child node projection is used to perform this calculation.
Given the offsets shown calculated in ~IGURES 22tA)-22(B), the locatio~s of the left-most and right-most vertices of the projection of any of the eight children nodes of root node 32 onto the cut plane test plane may be located. For inst~nce, the left-most vertex of the projection of child node 4 of root node 32 is given by NPK ~ ak4, and the right-most vertex of this child node is given ~y ~PK ~ ak4 ~ KDIAG. The l~cations of the vertices of the projections of any descendent of root node 32 onto the ~ut plane test plane may similarly ~e calculated, merely by divid;ng the appropriate ak offset and K~IAG by an appropriate factor of 2, depending upon the level of the descendent in the o~tree.
Referring to PIGURES 23(A) and 43(A3, shown is a 4 x 4 window array each window of which is of size E (the size of Display Screen 212). View plane ~ 1~3179~

1~4 66 has origin 104, whioh is located at the lower left~hand corner of Display Screen 212. The 4 x 4 array has been selected so that the center of the array coincides with origin 104, as shown in FIGURE
43(A). The configuration hown is arbitrarily defined in the presently preferred embodiment to be the "window packet" at window level 0.
It will be recalled that for both the PI
and E tests, it is necessary to construct lines which pass through a selected critical vertex of the window under test and which are parallel to lines defined by the various edges of a node projection.
A line defined by any given edge (interior or exterior) of a node projection must be parallel to either edge D0, edge Dl or edge D2 of the projection. Likewise, any such line will exclude one of the two pairs of opposite vertices of any given window from servin~ as a possible critical vertex for the PI and the E tests as a function of slope alone (it will be recalled from the discussion of ~IGURES 9 and 11 that one vertex of the pair not so excluded is selected as the critical vertex for the PI test, while the other is selected as the critical vertex for the E test; which vertex is used for which tes~ is a function of the orientation of the edge of interest with respect to the interior of ~ ~3~7~1~

the node). ~ecause of these constraints, it is not necessary to locate the position o~ lines parallel to each of edges D0-D2 passing through each of the four vertices o~ a given window. Instead, the position of only six lines for each window (two parallel to each of edges D0, Vl, D2~ need be ascertained for ~ny ~iven window.
A line 220 is constructed through point (~2E,2E) (one of the two vertices of the 4 x 4 array not excluded from serving as a critical vertex for edge D0 for the PI and the E test) parallel to edges D0 of the projection 211 of root node 32 (note that line 220 could have been ~onstructed through (2E,-2E) just as well). A line segment ~PD0 is constructed from origin 104 of view plane 66 perpendicular to line 220 and intersecting that line. Analogously, a line 222 parallel to edge Dl of the E)roje~tion of rQot node 32 is constructed through point (2E,-2E), and a line segment WPDl is constructed from origin 104 perpendicular to line 222 and intersecting that line. ~inally, a line 224 is constructed through point (2E,2E) parallel to edge D2 of the projection 211 of root node 32, and a line segment WPD2 is construrted from origin 104 to and perpendicular to line 224.

~ ~3 t 7~

The presently preferred embodiment uses the lines defined by each of offsets WPDO, WPDl and ~D2 as reference line~ t~ which addit`ional offset~ are added to ~btain the position of appropriate lines intersecting any criti~al vertex of any given window in the 4 x 4 window array. Referring to ~IGURES
23tB)-23~D), shown are the offsets from each of lines 220, 222 and 224, respectively, to correspon-ding vertices of each of the four windows in a window overlay. Referring to ~IGURE 23(B), the offsets from line 220 tshown in FIG~RE 23(A~) to each of the corresponding critieal vertices in a window o~erlay is shown. These offsets are calculated by constructing lines through each of the - critical. vertices parallel to line 220 (and thus parallel to edge DO of the projection of root node 32), and constructing line segmen~s from line 220 to each o~ these lines and perpendicular to those lines. FIGURES 23~C)-23(D) show analogous offsets for the Dl and D2 edges.
Referring to PIGUR~ 23(E), shown are three offsets used to locate the opposite critical vertex vf a window from the critical vertex located in FIGURES 23tB)-23(D). One of these offsets is used for each of the DO-D2 edges. It will be unders~ood that some of the offsets shown in FIGURF 23(E) are 3 ~

the same as ~ome of the offsets calculated in FIGURES 23(8)-23(D); while these of~sets Are sh~wn separately for the sake of clarity/ the presently preferred embodiment does not calculate them separately for ef~iciency re~sons.
Given the offsets calculated in FIGURES
23(A)- 3(E), the distance from origin 104 of view plane 66 to lines passing through the critical vertex of any window in the level 0 node packet shown irl FIGURE 23(A) may be calculated. It will be recalled from the discussion of FIGURES 6(D3-6(~) that the presently preferred embodiment selects sinqle windows from a 4 x 4 window array (i.e. a window packet~ by first selecting a 3 x 3 window array from the 4 x 4 array, then selecting a window ~verlay from the selected 3 x 3 array, and ~inally, selecting the one window from the window overlay.
The calculations used to locate the crit;cal vertices of a single window follow this same sequence. Of course, those skilled in the art will be read.ily able to devise other, possibly more direot methods of locating the critical vertices of a single window on the view plane, the particular method used by the presently preferred embodiment being only one such method.

123~79~

Referring to ~I~URES 6(D)-6(F) snd FIG~RES
~31A)-23(E), the critical vertices of a 3 x 3 ~rray may be ~alculated by adding to WPD0 an appropriate one of offsets ~D0OFF(0)-~D0OFP(3) as a function of the ~BI~S. ~hus, for example~ the critical vertex for the D0 edge of projection 211 of the root node for the 3 x 3 array given by ~3x3X=1 r W3x3Y=l may be calculated as ~PD0(3x3)=WPD0-WD0OFF~3). The locations of the critical vertices for the Dl and the D2 edges for the selected 3 x 3 array may be similarly calculated.
Once the positions of the critical vertices for the 3 x 3 array are known, the critical vertices for a window overlay selected from the 3 x 3 array may be ~alculated by merely adding offsets as the functi~ns of the value W2x2X and W2x2Y. Por example, for the window overlay given by W2x2X-l, W2x2~=0, the critical vertex for the overlay for the D0 edge of the projection 32 of the root node may be calculated as WCD0=WPD0(3x3)-WDOOFF(l). The position of the critical vertices for the Dl and D2 edges would be similarly calculated.

Once the position of the critical vertices for the window overlay are calculated, the critical vertices for any one of the four windows in the overlay may be calculated by adding appropriate ones 317~

of the ~DnOFF values ~hown in FIGURES 23(~)-23(D) ~nd the WDIAGn values shown in ~IGURE 23(E) as a . function of the value of WNUM. For example, the &et of two critical vertic~s for the V0 edge for window 00 in the window overlay is given by ~CD0~WDOOFF(0) and WCD0+WD00~F(0) ~ WDIAG0. One of these two vertices will be used as the critical vertex for an edge parallel to the D0 edge for the PI test, while the other vertex will be used for the same edge for the E test (which vertex is used for which test depends upon the orientation of the edge with respect to the interior of the node projection).
Critical vertices for edges parallel to edge Dl and D2 will be calculated analogously.
The Initializing Controller block 160 shown in ~IGURE 15 is implemented in the presently preferred embodiment by a software pro~ram executing on a Model 68000 microcomputer manufactured by Motorola, Inc. A copy o~ this software pro~ram is appended hereto as ~ppendix 8. Referring to PIGURES
24(A)-24(B), shown i~ a flow chart describing the algorithm executed by the Initializing Controller block 160. The algorithm is entered through terminal block ~50, and first enters INPUT bl~ck 252. INPUT block 252 accepts a number of inputs rom a user through various I/O devices, including - l~o scaling ~actors for each of the x, y and z di~en~
si~ns of the three-dimensional universe, the .
location of a center of rotation 294 for the three-dimensional universe (as shown in FIGURE 24(D)), angles of rotation in each of three orthogonal directions in the three-dimensional universe, the location of a point 296 on view plane 65 to which the center of r~tation 294 of the three-dimensional coordinate system is to be translated (as shown in FIGURE 24(C)), the orientation and distance between a pair of cut planes, and whether the region to be displayed defined by the cut planes is inside or outside of the cut planes.
The algorithm then proceeds to block 254, which sets up a r~tation matrix. The use of a rotation matrix to permit linear transformations of a three-dimension~1 coordinate system is well known in the art, and is discussed in Newman, W.M. and Sproull, R.F., Principles o~ Interactive Computer Graphics, 2d. Ed., McGraw~Hill, New York, lg79, Appendix II, pp. 4~1-501.
As shown in ~IGVRE 24(E), block 256 scales the three-dimensional universe relative to the three-dimensional coordinate system using the independent scalillg fact~rs for each of the x, y, and z directions input in block 252 ~y fl~ating 79~

point multiplication on the microcomputer. ~5 showr.
in FIGURE 24(F), block 2;8 then translates the origin 104 of the view plane ~oordinate ~ystem to the point ~94 defined by the user as th center of rotation~ Block 260 uses the rotation matrix set up in block ~54 to rotate the three-dimensional universe about center of rotation 294 ~which may be a point defined by the user anywhere in the three-dimensional universe) by the desired user-input angle~ of rotation, as is shown in FIGURE 24(G) (note that this linear trans~ormation is performed not on the three-dimensional coordinate axes, but rather on points of the three-dimensional universe, ~uitably the three (non-origin3 vertices 297a, 297b and 297c of the parallelepiped-shaped universe that intersect the coordinate axes of the local coordinate system of the universe (and the origin of the uni~,~erse). A first user-specified anqle of rotation rotates the three-dimensional universe in the y'-x' plane (from y' to x'). A second user-specified angle of rotation rotates the three-dimensional universe in the y'-z' plane (from y' to z'). A third user-specified angle of rotation rotates the three-dimensional universe in the x'-z' plane (from x' to z'). Each of these rotation angles may be independen~.

179~
J

Once the universe is rotated, as is shown in FIGURE 24(~3, block 262 translates the center of rotation 294 of the universe to the point 296 on the view plane selected by the user. Block 264 then "projects' the three-dimensional universe onto the view plane by calculating the two-dimensional coordinate values (x', y'~ for each of the eight vertices 298(1)-298(8) of the cuboid three-dimensional universe, as is shown in FIGURE 24lI).
(Note that the projection process is performed by block 264 ~y setting the z' coordinate of every one of the eight vertices 298(1~-298(8) to 0).
Block 266 defines the pair of parallel cut planes in the three-dimensional universe, and calculates the ak o~fsets and the value of KDIAG (as shown in FIGURES 22(A)-22(B) (by projecting the unrotated three-dimensional universe onto a test plane in a manner similar to that performed in block 264).
As shown in FI~URE 24(J), block 2~8 determines which of the eight vertices 298~ 298(8) of the projection of the three-dimensional universe is the left-most one (299LE). the right most one (299R), the upper most one (299U) and the lower-most`
one (299LW) by simple arithmetic comparisons of their coordinates as calculated by block 264. ~lock ~ 12317~Ql 270 constructs edges between each pair combination of the eight vertices, ~efines which of these edges are the D0, Dl and D2 edges, and determines the slope and orientation of each edge with respect to the interior of the n~de projection. The slope may be easily arithmetically computed, while the interi~r direction is ascertained by keeping track of which edges of the projection correspond to edges of the parallelepiped universe which lie on the three-dimensional orthogonal coordinate axes.
Box 272 uses the results of box 268 to determine the origin and dimensions of the bounding box defined by the projection of the root node ~as shown irl FIGURE 20(B)), and determines the various - i ax and ay offsets shown in FIGURE 20(C). The method of computing these locations, dimensi~ns and of~sets is well-known in the art. Blocks 274-280 calculate the of.l;sets shown in FIGURE 20(A), ascertains the critical vertices of a given window for each edge D0, Dl and D2 of the node projection (as shown in ~IGURES 9lA)-9(D~ and ll~A~-lllD)) ba~ed on the information determined by block 270, and calculates the window offsets shown in FIGURES 231A)~23(E)~
Block 282 calculates the node offsets shown in FIGURES 21(A)-21~

~ J ~317~

Block 284 establishes the lower left-hand corner of the Display Screen to the origin of the view plane, as shown in ~IGURES 20~A) and 43~A3~
~lock 286 computes a unique shading for each of the three ~aces of the node projection based upon the orientation of that face. An imaginary point light source infinitely far away from the object is assumed. It is typically located at the same point as the viewer, but ~an be located anywhere. A
surface normal vector for each face is constructed.
The in~ensity of each face may be computed as the dot product o~ the surface normal vector and a vector to the light source, as is discussed in Newman and Sproull, cited a~ove, pages 393-395.
An alternative and more sophisticated meth~d uf calculating the in~ensity of each window to be painted is to compute an intensity ~or each ~ULL node in the octree structure. This technique, which is referred ~o as "surface normal shading,"
will paint every window enclosed by the same ~ULL
node with the same intensity. The intensity for each node in the octree structure is calculated by approximating the node as a point on the surface of the object to be displayed, and constructing a plane intersecting that point and tangent t~ the surface of the object. A surface normal vector for this 317~

16~

tangent plane is constru~ted, and the intensi~y value to be attached to that node may be ccmputed as the dot product of the ~urface normal vect~r and a vector directed toward the viewpoint. Surface normal shading ~ay reguire a property memory (as discussed previously) ~r storage of the intensity value of each terminal node. Computation of surface n~rmal shading intensity values can be performed by a ~eparate pass through the octree structure. Those skilled in the art will readily recognize a variety of different ways in which the orientation of the tangent plane may be determined (such as YiSiting nodes neighboring the node the intensity of which is to be determined to discover if they are FULL or EMPTY in order to determine the local profile of the surface of the o~ject).
Block 2a8 determines from the dimensions of the bounding bQx calculated in block 272 which level of the octree produces node projections which are smaller than windows of level O in the quadtree (i.e. windows of the size of the Display Screen).
The node level is set egual to the window level so that the window overlay will have the proper relationship to the node projection, as was discussed previously.

166 123~L7~C~

Block 290 performs the output ~tep o the Xnitializing Controll2r blo~k by down-line loading the various registers in the Image Display Pro~essor block 152 tshown in ~GURE 15) to initiali~e it.
The Initializing Controller block exits through terminal block 292, and generates a "GO" signal to the Image Display Processor ~lock 152 to inform it that initialization i complete and that image generation may begin.
.

IMAGE DISPLAY PROCESSOR

Referring to FI~RES 15 and 25, shown is a detailed block diagram of the Image Display Processor block 152 of FIGURE 15. The funotion of the Image Display Processor is to generate a single image of the projection of the three-dimensional universe represented by the octree structure onto the twc~-dimensional view plane according t~ the selected view. The Image Display Processor block 152 accepts as an input initializing values from the Initializing Controller block 160 specifying a desired view, accesses the octree structure stored in the Octree Encoded Object Storage block 140, and ~utputs the image which it generates to the Image Display block 154.

317~1~

1~7 The Image Display Processor 152 comprises a ~emory ~ddress Proce~sor block 300 and it~
associated Memory Address Stack 400, and Object Node Packet Processor block 500 and its associated Object Node Packet Stack 410, a Node Select Logic block 600, an Ob~ect Node Ge~metry Processor 700 and its associated Object Node Geometry Stack 420, an Image Window Memory block 800, an Image Window Packet Processor 900 and its associated Image Window Packe~
5tack 430, an Image Window Geometry Processor block 1000 and its associa~ed Image ~indow Geometry Stack 440, a ~indow Overlay Select Logic block 1100 and its associated WBITS 5tack 450, a Window Select Logic ~lock 12~0 and its associated 3BOX Results Stack 460, ~ Cut Plane Processor ~lock 1300 and its associated Cut Plane ~eometry Stack 470, ~ Window Writer block 1~00, a Cycle Results hlock 1500 ~nd a Sequence Controller block lS03.
The function of the Memory Address Processor block 300 is to obtain a specified node packet from the Octree Encoded Object Storage block 140 and to reorde~ the eight node- in the obtained node packet arcording to ~he traversal se~uence ~or the selected view. In ~ddition, the Memory ~ddress Processor block 300 keeps track of the a~solute address of the node packets being accessed, and 7 9 ~

16~

calculates the absolute address in the Octree Encoded O~ject Storage block 140 Qf the next node packet t~ be retrieved.
The ~unction of the Object Node Packet Processor bl~ck 500 is to demand node packets from the Memory Address Processor block 300 by providing the child number ~CNUM0~ of the child node in the current node packet to be subdivided. The output of the Objert Node Packet Processor block 500 is the curren~ node packet ~PROP, which provides the E, P
or F property values for the nodes yet to be processed in the current node packet. The Object Node Packet Processor ~lock 500 also keeps track of which nodes have already been processed so that they will not be processed again.
The Node Select Loglc block 600 accepts as an input NPROP, the current node packet, and generates several outputsO One output ~CNU~) indicates the number of the first non-Empty node in the seven-to-zer~ traversal sequence in the curren~
node packet. The Node Select Logic block 600 also generates two other outputs, ~oth of which are applied as inputs to the Sequence Controller block 1600. The irst output indicates whether the current node is P or F ~the current node cannot be E, so E nodes are skipped over), the second outp~t 3179~ i (NR~M) indicates whether or not the current n~de packet has been eompletely processed ~and thu~
indicat~s when the next node packet must be retrieved).
Object Node Geometry Processor block 700 derives the geometry of the current node from the various locations and offset values (which may be characterized a families of x and y values used for the BBOX test and families of D0, Dl and D2 values used for the PI and E tests) generated by the Initializing Controller block 160, the child number (CNUM) produced by the Node Select Logic block 600, and the node level (NLEV, not shown) which is generated by the Sequence Controller block 1600. In this way, the Object Node Geometry Processor block 700 keeps track of the posi~ion of the current node project.ion on the view plane.
The Image Window Memory block 800 organizes and stcres the windows in the view plane in a quadtree structure, and continually updates the quadtree structure as new windows are printed by the Ima~e Display Processor 152 to the Image Display block 154. It accepts an ihpUt WPROP (the E, P or F
property values of the current 4 x 4 window array) together with the geometry of the current window overlay, and outputs the next window packet.

1~3379~

The I~age Window Packet Processor block 900 processes window packets produced by the I~age ~indow Memory block 800 by g2nerat.ng the output WPROP discussed above. The Image Window Packet Processor block 900 must al so update the quadtree as stored in the Imaye Window Memory block 800 as new windows are painted ~by marking windows ~ as they are painted and changing the ancestors of those windows to P or F, as appropriate, whenever the Image Display Proces~or POPs up a level), and must further provide updated property values for the current windows even before the Image Window Memory 800 has been updated tthe quacltree structure is updated only as it is traversed upward to increase efficiency).
~ he Image Window Geometry Processor block 1000 generates information concerning the geometry of the current windows. The Image Window Geometry P~ocessor block 1000 derives the geometry of the current window(s) under test from the various l~cations and offsets calculated by the Initializing Controller block lÇ0, the window number (WBITS and WNUM) of the window(s) currently under test, ~nd the ~indow Level ~WLEV, not shown) generated by the Sequence Controller block 1600.

.
7 ~ ~

The Window Overlay Select ~ogic block 1100 selects the window overlay for the current node from the current node packet ~PROP. The Window Overlay Select Logic block 1100 accepts as an input WPROP
(the E, P or F property values for each of the sixteen windows in the current 4 x 4 window array) and outputs the E, P or F property values for each of the windows in the 2 x 2 window overlay which it selects from the 4 x 4 array. The Window Overlay Select Logic block 1100 also generates the WBITS
(W3x3X, W3x3Y, ~2x2X and W2x2Y) indicating the window overlay which it selects (encoded as shown in FIGURES ~(D)~IE)).
The Window Select Logic block 1200 accepts as an input the property values of the current window overlay, and generates an output WNUM which selects the next window in the overlay to be procec,sed and the property value of the selected window. The selection of a window i5 affected by the results of the BBOX test, so the ~indow Select Logic block 1200 must discriminate between thsse windows which have passed the BBOX test and those which have failed it. The ~indow Select Logic block 1200 also generates a signal ~WREM) which indicates if there are any windows semaining in the current window overlay to be processed.

317~

The Cu~ Plane Prsoessor block 1300 accepts as an input the child number (CNUM) of the node currently being processed and the node level ~NLEV, not shown). The Cut Plane Processor block 1300 derives the yeometry of the projection of the current node onto the cut plane test plane and performs the ~ut plane test described in connection with FIGURE 14(B). The Cut Plane Processor bIock 1300 generates two outputs: a signal Cut Plane OK
which is asserted if the current node lie~ at least partially within the region defined by the cut planes to be displayed; and a signal Cut Plane INT
which is asserted if the current node is intersected by one of the cu~ planes. These signals are provided to the Cycle Results block 1500 and the Sequence Controller block 1600, respectively.
The Cycle Results block 1500 performs the BBOX, PI and E tests and generates an output indicating pass and ail resuits. It accepts as inputs the geometry of the current node projection (the families of X, Y, D0, Dl and D2 offset values) produced by the Object Node Geometry Processor block 700, and the geometry of current windows (the families of X, Y, D0, Dl and D2 offset values) from the Image Window Gecmetry Processor block 1000. The Cycle ~esults block 1500 also accepts as an input 2~179~

the WBITS generated by the Window Overlay Select ~ogic bl~ck 1100 selecting a window overlay ~rom the current 4 x 4 window packet in order to determine which four o~ the sixteen windows form the overlay and, therefore, are to be tested ~y the BBOX, PI and E tests. Finally, the Cycle Results block 1500 accepts as inputs the E, P or F property value information of the selected four window overlay and the Cut Pl~ne OK signal from the Cut Plane Processor block 13~0. The Cycle Results block 1500 reduces these multiple inputs to a small number of outputs as it performs the various tests on command of the Sequence Controller block 1600.
The Cycle Results bl~ck 1500 performs the BBOX test on all four windows in ~he current window overlay simultaneously, and generates four outputs (BPASS0, BPASSl, BPASS2 and BPASS3~, each of which indicates the result of the BBOX test ~or one of the four windows. These four B~OX result outputs are sent to the Window Select Lo~ic block 1200 to permit selection of which ones of the four windows in the current window overlay must be further processed by the PI and E tests. The Cycle Results block 1500 also, on command of the Sequence Controller block 1600, performs the Pl test and possibly the E test ~n single windows from the overl2y and generates an 317~

output to the Sequence Controller block indicating whether the particular window hàs passea or fail~d the test performed. If, for an F node, a window passes the BBOX, Sut Plane, PI and E tests land is Empty), the Cycle Results block 1500 generates an output PAINT indicating that the window must be painted, and a Face Number output, which indicates which color or shading the window is to be painted.
These two outputs are sent to the Window Writer block l400.
The Window Writer block 1400 converts the location and dimensions of a window to be painted to an area of pixels on the Image Display block 154.
The Window ~riter block 1400 accepts as inputs ~he geometry of the rurrent 4 x 4 array of windows, the WBITS ~indicating the location of the current wind~w overlay within that 4 x 4 array3, WN~M (which locates the one window to be painted within that window overlay) and ~LEV ~the window level, no~
shown); from those inputs, it generates the address of each pixel in the area on the Image Display 154 corresponding to that windowO
If the Window Writer block l400 receives the PAINT signal from the Cycle ~esults block 1500 it will control the Image Display 154 to paint an area of the Display Screen corresponding to that window an appropriate color or shadin~ (as determined corrcsponding to the Face Mumber of ~he pro jec~iDn of the node wh~ch encloses the win~w).
(Note that at the same time that ~he Window Writer block 1400 PAINTS a window, the Image Window Packet Processor block 900~ which also receives the PAINT
- signal, must update the quadtree structure stored in the Image Memory block 800 so that the same window is not painted again later on.) The Sequence Controller block 1600 controls the sequence in which all o~ the other blocks of the Image Display Processor 152 perform their tasks.
The Sequence Controller 1600 also determines when windows and/or nodes must be subdivided. The Sequence Controller ~lock 1600 thus steps the Image Display Processor 152 through the algorithm shown in FIGUR~S 18(A~-18(B).
It will be noted that the variou~ blocks of the Image Display P~ocessor labelled Stack have yet to be described. A Memory Address Stack 400 is connected to the Memory Address Processor block 300;
a Object Node Packet Stack 410 is connected to the Object Node Packet Processor block 500; a Object Node Geometry Stack 420 is connected to the Object Node Geometry Processor block 700; an Image Window Packet Staclc 430 is connected to the Image Window ~ 2 3 1 7 9~
!

Packet Pr~ce~sor ~lock 900; a Image Window ~eometry Stack 440 is connected to the Image ~indow Geometry Processor 1000; a WBIT5 ~tack 450 is ~onnecte~ to the Window Overlay Select Logic block 110C; a BBOX
Results Stack 460 is cDnnected to the Window Select Lo~ic 1200; and a Cut Plane ~eometry Stack 470 is ~onnected to the Cut Plane Processor block 1300.
The Memory Address Stack 400~ Object Node Packet Stack 410, Object Node Geometry Stack 420 and the Cut Plane Geometry Stack 470 all have the same function of sto~ing information about the current node pa~ket being processed when thP Octree structure is traversed to thle next node level, and producing that inormation once the Oc~ree is traversed back to that level so that the Image Display Processor ~ay~continue processing that node packet where processing was left off. Likewise, the Image Window Packet Stack 430, Image Window Geometry Stack 440, WBITS Stack 450 and ~BOX Results St~ck 460 have the same function of storing information about the current windows being processed when the quadtree structure is traversed ts the next level - down ~i.e. the current windows are subdivided3, and producing the information about that window packet when the quadtree structure is traversed back up to that window level.

1 7 ~ 13 Each of these Stack bl~cks is a LIFO ~tack upon which the operations of PUSH and PQP may be performed. The ~emory Address Stack 400, Object Node Packet Stack 410, Object Node Geometry Stack 420 and the Cut Plane Geometry S~ack 470 all push information in response to a NPUSH (node push), and all pop information in response to NPOP (node pop) operation. Likewise~ the Image Window Packet Stack 430i Window Image Geometry Stack 440, WBITS Stack 450 and BBOX Results Stack 460 all push information in response to a WPUSH twindow push) command, and all pop information in response to a WPOP (window pop) command.
The stack blocks permit the Image Display Processor to execute the r~cursive sections of the algorithm shown in FIGURES 18(A)-18(B~, and thus permit both the octree and the quadtree structures to be traversed toge~her in "lockstep," or independently. While each of these stack blocks stores different information (i.e. the working values of the block to which it is attached), they are all implemented in precisely the same manner and all have similar functions. (Indeed, the "window"
stacks may suitably be implemented as a single tack of sufficient width, whlle the "node" stacks may 17~

suitably be implemented as a second sufficiently-wide stack.~
Each of the different blocks compri~ing the Image Display Processor 152 will now be discussed in ~urther detail according to function and implementa-tion of the presently preferred embsdiment of the present invention.

M~MORY ADDRESS PROCESSOR

Referring to FIGURES 15, 25 and 26lA~-26(B), shown is a schematic diagram of the Memory Address Processor 300 in accordance with the preferred embodiment of the present invention. The function of the Memory Address Processor 300 is to address the Octree Encoded Object Storage block 140 to obtain the next n~de pa~ket, and to calculate the absolute address of the node packets containing the children of the current node packet in the Octree Encoded Storaqe. Referring to FIGURE 17, it will be reralled that node packets are stored in ~elative Address Format in words of memory in the Octree Encoded Object Storage block 140. The lower sixteen bits of each word c~ntains the E, P or ,F property values ~or each of the eight children stored in the node packet, while the upper sixteen bits contain an 7 9 al address o~fset which is added to the absolu~e address of the node packet to ~btain the addre ~ of the block of node pa~kets containing the children of ~he nodes contained in the node packet.
Referring ~ore particularly to FIGURES
26(A)-26(B~, node packets are read into the Memory Address Processor block 300 through the DATA line (which i~ suitably 32 bits wide)~ The lower half of the node packet (which stores the E, P or F property values of each of the eight nodes) is s~ored in a Node Packet Register 302, while the upper sixteen bits (representing address offset informa~iorl) is stored in an Offset Register 304. An Address Register 306 stores the absolute address in the Octree Encoded Object Storage block 1~0 of the current node packet (this Address Register 306 must be initialized by the Initializing Controller block 160 at l:he beginning of an image generation to the absolute address of the node packet containing the children of the root node).
The output o~ the Address Register 306 and the output of the Offset Register 304 are added together by an ~dder 308 to generate the address of the block of node packets containing the children of the nodes of the current node packet (as discussed a~ove in describing FIGURE 17). This block address ~ ~31~

1~

value is connected to the input of an Address ~ultiplexer ~MUX) 310, the output of which i~
connected t~ a Block Pointer Register 312. ~he input of the Address ~UX 310 connected to ~dder 308 is selected during a NPUSH operation initia~ed by the 5equence Controller block 1600, and permits the nodes of the present node packet to be subdivided into their children.
The output of the Block Pointer Register 312 is connected to the input of the Memory Address Stack 400; the output of the Memory Address Stack is connected to a second input of the Address MUX 315, and is selected by the MUX 310 during an NPOP
operation. After a node packet has been subdivided into its children and the children and their descendents have been processed, a NPOP will be performed on the Memory Address Stack 400 to traverse back up the octree structure. At this time, the former contents of the Block Pointer Register 312 (which were pushed onto the Memory Address Stack 400 before ~he subdivision occurred) are output by the Memory Address Stack, multiplexed through the ~ddress MUX 310l and reloaded into the Block Pointer Register 312. Processing o~ the POPped block of node packets may continue where it -` 12317~

1~1 was left off before the subdivision of the octree was initiated.
As will be recalled, the presently preferred embodi~ent stores some of the node packets in the higher levels o the octree in "Long"
Relative Address Format rather than "Short" Relative Address Format (in order to increase the range of memory which can be used to store the octree).
Those node packets stored in the "long" format are stored in 64-bits of memory (i.e. two sequential words in the Octree Encoded Object Storage 140) rather than in a single word. In order to properly access these 64 bit node packets, a "double fetch"
cycle is employed.
The Sequence Controller block 1500 ~an determine whether a node pac~et being retrieved from the Oc~ree Encoded Ob~ect Çtora~e is stored in short or long ~ormat (the top packe~ is in long format and a bit in the otherwise unused short offset field indicates when the su~tree will only use short address format packets~. If the node packet being retrieved is stored in long format, the first word of the node packet is retrieved and stored in Registers 302 and 304 as discussed previously. If the Sequence Controller block 1500 determine~ (from the packet size of the parent and the value of a 791~1 1~2 flag bi~ in the sh~rt addres~ field if the paren~
was in long format) that a second fetch i5 requiredr it applies a logic one to an Adder 3U7 on the ~utput of Address Register 3~6 t~ increment the address by one, and stor~s the second 32-bit w~rd which appears on the Data line in a Register 305 ~thi~ information represents the 32-bit long offset). The output of Register 305 is ad~ed to the sum of the output of Of~set Register 304 and the output of Adder 307 to produce the offset in memory from the current node packet to the node packet next to be retrieved.
As noted above, one of the bits in the first word of each ~'long" node packet is used as a flag bit which indicates that its children are "long" rather than "short"; in this way, "long" node packets can occur at any level of the octree, and some of the node packets at a given level of the octree can be ~l~ng" while others are short. Qf courser all ancestors of a long packet must be lony.
Alternatively, one skilled in the art could easily devise ~odifications to the ~emory Address Processor block 300 to permit some node packets to be in Relative Address Format while other node packets contain the Absolute Address of the block of children node packets.

~ ~3 ~ ~91D

lB3 The current node packet stored in the Node Packet Register 302 is one o~ the outputs of the Memory Address Processor 300, and is connected to the Object Node Packet Processor block 500. In addition, the bits produced at the output of the Node Packet Register 302 are conventionally combined together by Logic ~rray 313 (suitably a bank of inverters followed by a bank of two-input AND gates not shown) to generate eight outputs, each of which is asserted if a corresponding node in the current node packet has a P propesty value (it will be recalled that in the preferred embodiment of the present invention P is encoded as 01). These eight values are connected through a MUX 314 to a Node Displacement Register 316.
The output of ~he Node Displacement Register 316 is connected through a Logic Array 317 (another conventional array of combinational logic) to generate seven values, PAR~0 (which is asserted when the right-most node as stored in the node packet is marked P)~ PART0 + PARTl (which is equal to the arithmetic sum of the number of P nodes in the two right-most positions of the node packet), PART0 + PARTl ~ PART2 (~hich is equal to the sum of the number o~ nodes marked P in the three right-most positions of the node packet), ..., and PART0 +

PARTl + P~RT2 ~ PART4 + PART5 + PART6 (the number of nodes mark2d P in the seven right-most positions of the node packet stored in Node Packet Register 302).
These seven lines ~each suitably 3 bits wide) together with a zero value are connected to the eight inputs of MUX 318, the select lines of which are connected to the CNUM0 signal (representing the child number of the node currently being processed in the current node packet produc2d by the Object Node Packet Processor block 150~
The output of MUX 318 is the offset within the node packets pointed to by the Block Pointer Register 312 of the node packet containing the children of the current node being processed. This offset is added to the address st~red in the 81Ock Pointer Register 312 by an Adder 320 to genera~e the absolute address of the child node packet li-e- the node packet containing the children of the current node packet), and is applied to the input of the Address Register 306. If the Sequence Controller block 1600 commands a NPUS~, this value will be clocked into Address Register 306, and the Memory Address Processor 300 will access the children of the current node, thus traversing one level down the octree.

~ ~31791~1 18~

The output of the Node Displacement Register 316 is als~ connected t~ th~ input of the Memory Address Stack 400, and the output of the Memory Address Stack is ~onnected to an input of the MUX 314~ ~hen ~ NPUSH is performed, the contents ~f the Node Displa~ement Register 316 will be stored in the Memory Address Stack 400; likewise, when an NPOP
is performed, the Node Displacement informati~n will ~e returned from the Memory Address Stack through the ~UX 3l4 and back into the Node Displacement Register 316. In this way, Node Displacement information is saved when the octree is traversed down one level, and processing may resume where left off when the octree is traversed back up to the present level.
The Memory Address psocess~r block 300 can be placed in an "unpacked" mode to handle unpack~d octreesO In this case, block 313 is forced to indicate that ~11 nodes are P n~des 1 no matt~r how many P nodes are actually contained in register 302).

- MEMORY ADDRESS STACK

Referring to FIGURE 27, shown is a schematic diagram of the Memory Address Stack 400.

`` 1~31~9~

1~6 As discu~sed previously, the Object Node Packet Stack 410, the Object ~ode Geometry 5tack 420, the Image Window Packet Stack 430, the Image ~ind~w Geometry Stack 440, the ~BITS Stack 450, the B~OX
Results Stack 460 and the Cut Plane Geometry Stack 470 are all implemented in precisely the same manner as the Memory Address Stack 400. Thus, FIGI~RE 27 actually shows a generalized stack 480. Stack 4~0 comprises a Random Access ~emory (RAM~ 482 and a DAT~ Register 484. RAM 482 is suita~ly a semicon-ductor static Random Access Memory as wide as needed for the particular stack application, the number of locations of which is determined by the number of levels that stack 480 must store. If stack 480 stores Node information, such as the Memory Address Stack 400, Object Node Packet Stack 410, ~bject Node Geometry Stack 420 or eut Plane Geometry Stack 470, then i~ suitably has sixteen locations for a l-par~-in-65,~36 resolution (in each dimension) octree.
Additional levels are used fsr higher resolution objects. If stack 480 stores window information (such as do the Image Window Packet Stack 430, Image Window Geometry Stack 440, WBITS Stack 450 or BBOX
Results Stack 460) then the stack suitably ha~ nine locations ~or a 512 pixel display soreen, to stDre the nine upper levels of the 10 level quadtree.

1 ~ 3 ~ 7 ~ ~`

Additiondl levels can be used for higher resolution images.
The Address Input of RAM 482 is ~onnected to either the node level signal N~EV ~for the ~node stacks") or the window level signal WLEV ~for the "window sta~ks"~ generated by the Sequence Controller block 1600. The Sequence Controller block 1600 performs a NPUSH by simply incrementing NLEV (and enabling the write c~ntrol on RAM 482) and performs a NPOP by decrementing NLEV (and clocking Data Register 484). The Sequence Controller block 1600 analogously performs a WPUSH operation by incrementing ~LEV ~and enabling the write control on RAM ~82~ and performs a WPOP by decrementing WLEV
~and clocking Register 4843.
The D~TA OVT ou~put of RAM 4B2 is connected to the input o~ Register 484. Register 486 always contains the last value stored in RAM 482 (thus implementing a LIFO Stack). The Data In input of RAM 482 iS the input o stack 480 r upon which i5 placed the value to be stored by the stack during the next P~SH operation. It will be understood by those skilled in the art that register 484 could be eliminated provided that the resulting complexity in assuring that proper signals were available from the stack at the proper time csuld be tolerated.

-- 123~7~

1~8 ~JECT NOD~ PACKET PROCESSO~
- AND NODE SELECT LOGIC

Referring to FI~URE 28, ~hown is a schematic diagram of the Object Node Packet Processor 500 and the Node Select Logic 600 shown in FIGURE 25.
The function of the Object Node Packet Processor 500 is to accept a node packet from the Memory Address Processor block 300, to reorder the nodes in that node packet according to the traversal sequence for a given viewing angle, and to keep track of the nodes in the node packet that have already ~een processed. The Object Node Packet Processor 5~0 generate~ a reordered node packet NPR~P (which comprises the E, P ~r F property values for the reordered node packet) and sends it to the Node Select Logic block 600. The Node Select ~ogic block 600 selects the next non-Empty node in the seven-to-zero traversal sequence in the node packet NPROP~ The Node Select LogiG block 600 generates the P or F property value for the current node ~E

nodes are skipped), and also generates a value CNUM.
which indicates which child num~er in the (reordered) node packet is the current node. The Node Select Logic block 600 also generateS a signal 3179~ 1 ~REM which is ~s erted when there is one or more non-Empty nodes left in the NPROP node pa~ket.
The Object Node Packet Processor block 500 accepts as an input the node packet generated by the Memory Address Processor 300. This node packet tsuitably 16 bits wide, i.e. 2 ~its per node) is applied as an input to a Traversal Sequence Encoder 504. The Traversal Sequence Encoder block 504 rearranges the position of all of the nodes in the node packet according to the traversal sequence for a given viewing angle. Referring to FIGURES 4(A) and 17, it will be recalled that the nodes in any given node packet are arbitrarily numbered and stored in the Octree Encoded Object Storage block 140 according to the seven-to zero traversal sequence for an arbitrary viewing an~le. Th~
viewing angle selec~ed by a user through the Interaction ~ith U~er block 150 will determine the sequence (one of eight) in which the n~des in a node packet must be accessed according to the viewing angle ~so that hidden ~urfaces are not displayed).
The traversal sequence for a given viewing angle is determined by which of the eight octants of the octree coordinate system shown in FIGURE 4~A) the octree universe is viewed from. Since there are eight octants in a three-dimensional coordinate 3179~

system, there will be eight different traversal sequences, one for each octant. The Interaction ~ith User block 150 o~ FIGURE 15 determines which octant the three-dimensional universe is being viewed from by monitoring the position of the Trackball, and generates a Case ~umber value (suitably 3 bits wide) which is stored in Case Number Register 503 ~t the beginning of each image generation.
The following table is a cuitable encoding for Case Number as a function of the octant in the three-dimensional universe fr~m which the ~bject to be displayed i5 viewed, showing also the traversal cequence ~f nodes as numbered in FIGURE 4(A):

Case Traversal Octant Number Sequence x y z 000 7 6 S 4 3 2 1 0 + ~ +
~01 6 2 4 0 7 3 S 1 ~ +
010 5 1 7 3 4 0 6 2 +
011 4 5 6 7 0 1 2 3 +
100 3 7 1 5 2 6 0 4 - ~ +
101 2 3 ~ 1 6 7 4 5 - ~ -110 1 0 3 2 S 4 7 6 - - +
111 0 4 2 6 1 5 3 ~
TABL~: I

Referring once again to FIGURE 2B, the Traversal Sequence ncoder block 504 is suitably a combinational logic array with dual func~ions:

lgl (1) to seorder the node packet sent by ~he Memory ~ddress ~rocessor block 300 so ~hat the nodes appear in the traversal sequence as a function of the Case Number value; and (2) to translate the CNUM (child number) value generated by the Node Select Logic block 600 from a format which indicates the child number of the current node aocording to the traversal sequence of the given viewing angle as specified by the Case Number to the corresponding node number ~s it is stored in the Ortree Encoded Object Storage block 140 (i.e. before it is reordered).
Thus, the ~raversal Sequence Encoder block 504 accepts three inputs, the node packet generated by the ~1emory Address Processor block 300 (suitably 16 bits wide), the CNUM value generated by ~he Node Select Logic block 60~ Isuitably 3 bits wide), and the case number from the Case Number Register 503.
~he Traversal Sequence Encoder b~ock 504 generates two outputs: CNUM0, the translated CNUM value (suitably 3 bits wide), and the reordered node packet NPROP (suitably 16 bits wide). One skilled in the art could readily design a conventional logic array to perform this one-to-one mapping ~f CNUM
into CNUM0 and the node packet into NPROP using conventional logic elements.

1 ~3 3 79~ ~

A multiple~er 502 is connected to the node packet input of the Traversal SQquence Encoder $04, and 5ele~t5 between the node packet produced by the Memory Address Processor block 300 and a set of hard~wired logic 1 inputs. The select line ~f MUX
502 is c~nnected tv the property value of the current node produced by the Node Select Logic block fi00. If the current node is P, MUX 502 selects the hard-wired logic 1 inputs to generate or "simulate"
the node packet containing the children of the F
node (it will be recalled that the o~tree structure is "trimmed" to remove all of the children of both E
and F nodes; however, an F node must be subdivided if it is intersected by a cut plane). Otherwise, the ~hild node packet accessed ~y the Memory Address Processor block 300 is selected by the MUX 502 to be input to the Traversal Sequence Encoder 504~
The translated CNUM0 value is ou~put from the Otiject Node Packet Processor block 500 to the Memory ~ddress Processor block 300, and is used to determine the address offset within a block of node packets. The reordered node packet NPROP produced by the Traversal Sequence Encoder 504 is connected to the input of a MUX 506~ the output of which is applied to a NPROP Register 508. The output of the NPROP Register 508 is applied to the input of the -~ ~ ~ 1 7 ~

Object Node Pa~ket Stack 410, the output of which is connected to the other input of the MUX 506. On an NPUSH, the value currently stored in the NPROP
Register 508 is pushed onto the Object Node Packet Stack 410. ~At this point, a new, subdivided node packet will be sent to the Object Node Packet Processor block 500 by the Memory Address Process3r block 300, will be reordered by the Traversal Sequence Encoder block 504, selected by the MUX ~06 and stored in the NPROP Register 508 as a new node packet.~ On an NPOP, MUX 506 selects the output of the Object Node Packet 5tack 410, and thus the last NPROP value stored on the stack 410 is clocked into the NPROP Register 508 so that processing o~ that node packet packet may resume where it was left off before it was pushed onto Stack 410.
The output of the NPROP Register 508 is also output from the Object Node Packet Processor block 500 to the Node Select Logic block 600. The Object ~ode Packet Processor block 500 receives from the Node Select Logic block 600 an input CNUM, which is the child number ~f the node of node packet NPROP
currently being processed. As mentioned be~ore, CNUM is applied as an input to the Traversal 5equence Encoder 504 so that it m~y be translated into CNUM0. In addition. CNUM i5 applied as an --` 12317~ i 19~

input to ~ three-to-eight Decoder 510 which is also gated by the Sequence Controller block l600. ~he 3-to-8 Decoder 510 has eight Reset lines as outputs~
each of which is applied to one of the eight sets of 2-bits of the NPROP Register 508 which stores the property value of a child node. ~henever CNUM is updated (indicating that the processing ~f the current node is completed and that the next non-Empty node must be processed), one of these eight Reset l.ines is asserted ~o clear (to Empty) that particular node in NPROP Register 508~ In this way, the Object Node Packet Processor block 500 keeps track of which nodes in the current node packet have already be n processed.
The Node Select Logic block 600 accepts as an input the current node packet NPROP from the Object Node Packet Processor block 500. It generates three outputs: CNUM (suitably a 3-bit value indicating the child num~er of the node in node pack2t NPROP currently being processed); the P
or F property value for child number CNVM; and NREM, which is asserted if there are any "active" (i.e.
non-~mpty) unprocessed nodes remaining in NPROP.
The node packet NPROP is connected to the input of a Priority Encoder 602 (suitably comprising 74~148 Priority Encoders). The output of the ~ 23 1 79~ 1 Priority Encoder 602 is a 3-~it value indicating the next non-Empty node (in the seven-to-zero tr~versal sequence) i~ NPROP. This 3-bit output is connected to the input of a CNUM Regi~ter 604, and is clocked into that Register whenever the Sequence Controller block 1600 determines that the processing of the current node is complete. The output of the CNUM
Register 604 is CNUM, the number of the current node NPROP being processed.
NPROP is divided into two sets o 8-bits each. One ~et of 8 bits comprises the lower property value bits of the ~ight nodes in NPROP, while the other set of 8 bits comprises the upper property value bits of the eight nodes in NPROP.
These are each sent to an 8-to-1 MVX ~MUX 606 and MUX 608, respectively). MUXes 606 and 608 are selected by the same 3-bit select line, the 3-bit (unregistered) output from Priority Encoder 602.
Thus, MUX 606 and MUX 6D8 together select the P or F
information f or the next non-Empty node in NPROP.
The output of ~UXes 606 and 608 are ~oth connected to the CNUM Register 504, and are clocked into the register together with the new value o~ CNUM. The CNUM Register 604 at any given time contains the P
or F property value for the CNUM child number of node packet NPROP as well as CNUM.

The Node Select Logic block 600 generates one more ~utput, NRE~, suitably a l-bit value which is asserted whenever there is a non-Empty unprocessed node remaining in NPROP. The P or F
property value for ~urrent node CNUM and the value NREM are both sent to the Sequence Controller block 16~0 so that the Sequence Controller can determine the property value o~ the current node being processed, as well as when the current node packet NPROP has been completely processed. As nodes in the current node packet are processed, their property values are cleared from the NPROP Register 508 of the Object Node Packet Processor block 500, so that the Object Node Packet Processor block together with the Node Select ~ogic block 600 keep ~rack o~ which nodes in the current node packet have been processed. The NREM signal is asserted by Priori~y Encoder block 602 ~hen any of the 16 bits NPROP ~re asserted (a signal conventionally provided by off-the-shelf gates~.

OBJECT NODE G~OMETRY PROCESSOR

Referring to FIGURE 25, the function of the Object Node Geometry Processor block 700 i5 to supply information concerning the geometry of the 317~0 1~7 current node to the Window Overlay Select ~ogic ~lock 1100 (to permit seleotion ~f a wind~w overl~y) and the Cycle Results block 1500 ~ts permit it to perform the BBOX, PI and E tests). The Object Node Geometry Processor 700 aocepts as an input the value CNUM Çrom the Node Select Logic block 600 ~representing the number of the node currently being processed in the current node packet). It generates five families of uutputs, the geometries o~ the current node being prooessed in each of the X', Y', D0, Dl and D2 dimensions (see FIGURES 20(A)-20~C) and 21(A) 21(F)~.
Referring to FIGURE 29, the Object Node Geometry Processor 700 is divided into two basic sections, the Node Bounding ~ox Geo~etry ~loc~ 702 and the Node Polygon Geometry block 750. While only two blo~ks are shown, actually the Node Bounding ~ox Geometry block 702 is duplicated twice (once ~or x' and once for y'), while the Node Polygon Geometry block 750 is duplicated three times (once for each of the D9, Dl and D2 dimensions)~
The Object Node Geometry Processor block 700 contains several shift registers which are initialized by the Initialization Controller block 160, and are shifted one place right for a node PUSH
and one place to the left for a node POP. They are 1 7 9 ~
I

thus shifted an appropriate number of bits to the left or to the right according to the node level NLEV (a value generated by the Sequenoe Contr~ller block 1600 indicating the level of the octree at which the node currently being processed is located). The b ~egister 704 is initialized by the Initializing Controller ~lock 160 to the value bx (or by for the duplic~tion of the Node Bounding Box Geometry block 702 in the y' dimensionJ calculated as shown in FIGURE 20~B). The a Table 706 is a bank of eight ~hift registers containiny the axO-ax7 offsets (or ayO-ay7 offsets for the duplication of the Node Bounding Box Geometry block 702 in the y' direction) shown c~lculated in FIGURE 20(C).
Likewise, the NDOFP Table 752 comprises four shift registers, each af which are initialized to an appropriate one of the three NDOOPF values or zero ~the N~lOFF values for the Dl duplication of the Node Polygon Geometrv block 750 and the ND20FF
values for the D2 duplication of the Node Polygon Geometry block 7~0) shown calculated in FIGURES
21(D)-21(F). Likewise, the FDIAG Register 754 is initialized to the FDIAGO value (the FDI~Gl value for the Dl duplication of the Node Polygon Geometry block 7$0, and the FDIAG2 value for the D2 duplication of the Node Polygon Geometry block) -\ 123~i90 lg9 shown calculated in FIG~RES 21(D)-21(F)~ 5imilarly, an NDIAG Register 756 is initialized to the NDIAG0 value (the NDIAGl and the NDIAG2 values for the Dl and D2 duplications of the Node Polygon Geometry block 750, respectively) shown calculated in FIGURES
Zl~D)-21~F)o Each of the geometric values is suitably 24 bits wide to provide a desired degree of precision.
The shift registers used to implement the b Register 704~ PDIAG Register 754, NDIAG Register 756, a Table 706 and NPOFF Table 752 are suitably substantially wider than 24 bits, but generate only 24 bit outputs. The remainder of the width of these shift register provide "underflow capability,"
meaning that the values shifted "out" of the 24 bits generating an output are not lost, but are stored elsewhere so that they may be shifted back into the shift registers. This "underflow capability" may suitabl~ be implemented either by long shift registers, or by an auxiliary storage element, such ~s a RAM.
All of these shift registers are shifted the same numher of bits dependent upon the signal NLEV. It will be recalled that because the dimensions of any given node are exactly one-half those of its parent t all of the values calculated as I ~3 1 7~

shown in FIGURES 20~ 20(C) and. 21~A)-21 (P) can be used at any node level by merely dividing them by an appropriate factor of 2. ~s will be under~to~d by those skilled in the art, division of a binary number by an appropriate factor c~f 2 may be accomplished by merely shifting the number an appropriate number of bits to the right. Thus, the b Register 704, ~DIAG Register 754, NDIAG Register 756, ancl the registers in each of the a Table 106 and NDO~P Table 752 are shifted one place to the right each time ~he octree structure is traversed downward to subdivided nodes ~NPUSH) in order to calculate the appropriate node geometry values for the current node level, and are shifted back to the left one place each time the octree structure is traversed one level back up toward the root node 5Npop).
~ he Node Bounding Box Geometry block 702 also comprise~ a ~ounding Box Origin Register 708, which is initialized by the Initializing Controller block 160 to contain the NPX (NPY for the Y ' duplication of the Node Bounding Box Geometry block 702~ value calculated as shown in FIGURE 20tB) (it will be recalled that (NPX, NPY) is the origin of the bouflding box for the octree universe)~ The output of Register 708 is connected to the input ~f 23 1 7~ ~

an Adder 710, the other input of which is connected to the output of the a Table 706~
~ s mentioned previously, the a Table 706 s~ores the values axO ax7 (ayO-ay7 for the y' dupli-cation of the Node Bounding Box Geometry block 702).
Each of these values rorresponds to the bounding box offset for one of the eight nodes in the current node pa~ket. A 3-to-8 Decoder 714 accepts CNUM as an input from the Node Select Logic block 600, and generates one ~f eight mutually exclusive ou~pu~s, each of which is used to select one of the eight shift registers in the a Table 7C6. Thus, the approp~iate ax (ay) value for the node currently being accessed in the current node packet will be applied to Adder 710.
The output of Adder 710 thus represents the origin of the bounding box for the child of the current node, NCX ~NCY). This output NCX îs connected to the input of a MUX 712, the output of which is connected to the input of th~ ~ounding Box Origin Register 708. The other input of the MUX 712 is connected to the output of the Object Node Geometry Stack 420. The input of the Object Node Geumetry Stack 420 is connected to the output of the Register 70B. During a NPUSH, the MUX 712 selects the NCX input, and NCX is clocked into the Register J~3J7~

70B; at the same time, ~he current value of NPX is pushed onto the Object Node Geom`etry Stack 420.
During a NPOP, the MUX 712 selects the output.of the Object Node Geometry Stack 420 (the NPX tNPY) value of the parent node), which is ~locked back into Register 708. In this way, the Object Node Geometry Processor 700 generates the appropriate values f~r the bounding box origin tNPX, NPY) when the octree is traversed up or down a level.
The ~utput of the 3-to-8 Decoder 7~4 is also applied to select the appropriate one of the f~ur NDOF~ values from the NDOFF Table 752. The output of the NDOFF Table 752 is connected to one input of an Adder 758, the other input of which is connected t~ the output of a NPD Register 760. The NPD Register is initialized by the Initiali2ing Controller block 160 to contain the value NPD0 (NP~
and NPD2 for the Dl and D2 duplications of the Node Polygon Geometry block 750, respectively) calculated as shown in FIGURE 20(A). The output of Adder 758 is thus the offset from the origin 104 of the Display Screen 212 (as shown in FIGURE 20(A)) to the D0 ~Dl or D2) edges of the projection of child node CNUM of the parent node ~tored in the NPD Register 760. This value is output to the Cycle Results block 1500, and is also applied to an input o~ a MUX

~ 3 1 ~ g i~
I

762, the output of which is connected to the input of the NPD Register 760. The output of the NPD
Register 760 is also connected to the input of the Object Node ~eometry Stack 420, the output of which is connect2d to the other input of MUX 762. During an NPUS~, the contents of the NPD Register 760 is pushed onto the Object Node Geometry Stack 420, and the output of the Adder 758 is selected by the MUX
762 and clocked into the NPD Register; in this way, the NPD0 (NPD1 and NPD2) displacement for a child node projection are derived from those of its parents. Likewise, during a NPOP, the output of the Object Node Geometry Stack 420 is selected by the MUX 762, and is clocked into the NPD Register 760 to return the NPD0 (NPDl and NPD~) displacement to the NPD Register when the octree is traversed back up a level upon ompletion of the processing of a subdivision.

IMAGE WINDOW MEMORY

Referring to FIGURE 3D(A), shown is ~
detailed block diagram of the Image Window Memory block 800 of FIG~RE 25. The function of the Image Window Memory B00 is to represent the windows of the view plane in a quadtree structure, to retrieve a ~ ~3~9~ 1 ~elected window packe~ on demand, and to update the quadtree by changing painted wind~ws to F and changing the ancestors of painted windows to P (or F, as appropriate~.
Unlike the Octree Encoded Object Storage block 140, which produces an entire node packet of eight children nodes whenever it is accessed, the Image Window Memory block 800 must produce a window packet comprising the four children of each of the four parent windows in the parent window overlay (resultinq in a total of 16 windows). The ~indow Overlay Sele~t Logic block 1100 then selects a new window overlay of four c~ntiguous windows from among those 16 windows. This added complexity exists because a window overlay is defined as four contiguous windows guaranteed to enclose a given node projection; these four contiguous windows are not ~u!aranteed to be the children of the same parent window. Also, all 16 windows may be needed simultaneously during a WPOP operation because they all may need to be examined in order to generate the four reduced parent values.
In order to permit the simultaneous access of the four children of any four contiguous windows in the current 4 x 4 window array, the presently preferred embodiJnent of the present invention 1~179~ 1 ~05 utilizes an interleaved memory comprising fDur different ~emori~s whi~h are pbysically separat~
(and separately addressed)~ each of which ~tores one-fourth of the quadtree structure. Referring to ~IGURE 30~B), all of the windows at any (every) level of the quadtree comprising the Display Screen 212 are organized into A, B, C and D windows, as ~hown. An "A" window is arbitrarily located so that its lower left-hand vertex corresponds to origin 104, and B, C and D windows are arranged ~o surround it as shown.
Referring to ~IGURES 30(A) and 30(B), ~he children of A windows are stored in the A array 802, the children of B windows are stored in the ~ array 804, the children of C windows are stored in C array 806, and the children of D windows are stored in D
array B08. ~ family of four ehildren windows are stored in the same word in their resp@ctive arrays.
If the same address is applied to all of the Arrays 802, dO4, 806 and 808, the sixteen grandchildren of some parent window will be produced (for example, windows 295A-295D).
As mentioned above, it cannot be predetermined which four windows of a 4 x 4 window array will be selected as a window overlay.

Re~erring ~o FIGUFIES 30(B)-30~F), it will be -206 ~ ~ 3~ 7~

understood that ~y wind~w overlay will ~o~prise an ~A" window, a "~-- window, a ~C" window and ~ UD~
window, and that only four different arrangem2nts of these windows are possible. These four possible arrangements are suitably encoded in two bi~s, MAPX
and ~APY, as shown.
Referring once again to FIGURE 30(A), the Quadtree Address Map 81D accepts as inputs the values WPX and WPY (describing the origin of a window overlay to be subdivided). In addition, the Quadtree Address Map 810 accepts the MAPX bit and the MAPY bit, which determines how the various wind~ws in ~he window overlay are t~ be mapped into Arrays 802, 804, 806 and 808 (i.e. which windvw is to be produced by which array). The Address ~WPX, WPY) actually specifies a window overlay in the interleaved memory arranged in the format shown in FIGURE 30(C). The MAPX and MAPY may be viewed as least significant bits to permit variations in this ~ormat.
The Quadtree ~ddress Map 810 per~orms a l-to-l mapping of the 16 bits (WPX and WPY are suitably 7 bits each, while MAPX and MAPY are suitably 1 bit each) applied to its input into addresses for ~he A, B, C and D Arrays ~802, 804, t 2 3 1 ~ 9 al 806, 308, respectively~. The addresses for each array ~re calculated as ~ollows:

. . .
A Array Address = ~PX!WPY
Array Address = (~PX+MAPX)!WPY
C Array ~ddress = WPX!~WPY+MAPY) - D Array Address - (WPX+MAPX)!(WPY~MAPY) ~where I is the operation of catenation and ~ is arithmetic addition).

It will be understood by those skilled in the art that the A, B, C and D addresses will all be the same when the MAPX and MAPY bits are both 0 (thus constituting the specific case where the window overlay being subdivided comprises four childrerl windows of the same parent window~. In the case where MAPX and M~PY ~re not both 0, the address actually ~pplied to Arrays ~02-808 will not be equal. i~or this reason, while the Quadtree Address Map 810 performs a unique l-to-l mapping ~meaning that any given lo~ation in any one of the Arrays 802, 804, 806 and ~08 can be arrived at only through one unique combination of WPXs WPY, MAPX and MAPY~, information is not stored sequentially in each of the arrays but rather in a seemingly random fashion 1 2 3 ~ 7 9ai (although the address of any given piece of information may ~e readily calculated).
For any given set of values of ~PX, ~PY, MAPX and MAPY, a window packet comprising 32 bits of data (the 2-bit property values of each of the four children windows of each of the four parents compri-sing the 2 x 2 window overlay being subdivided) will be generated by the A, B, C and D Arrays (802, 804, 806 and 808). This data must be reordered to remain consistent with the arbitrary traversal sequence of a window overlay shown in FIGVRE 6~F)~ The reordering is accomplished by the Data Read Map 812, which reorders the information according to the values of MAPX and MAPY.
The Image Window Memory 80Q must be written into as well as read from, since the quadtree struc-ture must be continually updated every time a window is painted by the Image Display block 154 to assure that hidden surfaces are not displayed in the image (compare the Octree Encoded Object Storage block 140, which is only read from and never written to;
this is because a given window may be accessed numerous times but only pained once, while a given node will only be accessed once). A Data Write Map 814 performs a task similar to that of the Data Read Map B12 by reordering WPROP (a window packet already ~;~3~
~9 updated by the I~age Wi~dow Packet Processor gOO to be discussed shortly) ~rom the traversal sequenoe shown in FIGURE 6~F) to a format suitable for storage into the A, B, C and D Arrays 802, 804, 806 and BO~. A bi directional Tri-State Bus 816 is used to connect the data input/output of the A, B, C and D Arrays (802, 80~, 806 and 808, respectively~ to either the output of the Data Write Map 814 or the input ~f the Data Read Map 812.
A Quadtree Block Enable Logic block ~18 is used to selectively enable any combination of the four Arrays 802, 804, 806 and BOB. In general, the Quadtree Block Enable Logic 818 will enable all of the arrays. ~owever, as will be explained shortly, it is possible that a given window overlay will not be entirely on the Display 5creen ~12~ As mentioned previou~ly, only the Display Screen section of the view plane is organized into the quadtree structure;
thus, only windows on ~he Display Screen will be stored in the Image ~indow Memory ~00. An F node located at the very edge of the Display Screen 212 may define a window ov~rlay vf four windows only som~ ~f which are part of the Display Screen. The Quadtree Block Enable Logic block 818 enables only those Arrays 802, B04, B06 and 808 corresponding to windows ~ctually on the Display Screen (determining 23~790 which windows are on the Display Screen from four ~alues, POUTRX, POVTRY, POUTLX ànd POUTLY, produced by the I~age Window Geometry PrQcessor block 1000).
Finally, every window at every level of the quadtree strurture ~ust be initialized to E (00) before an image is generated Isince the Display Screen is blank before each im3ge is generated).
The function of clearing the quadtree before each image is generated is performed by the Quadtree Clear Address Generator 820 together with address MUXes 822, 824, 826 and 828. The Quadtree Clear Address Generator receives a "start" signal from the Sequence Controller 1600 before an image is to be generated. In response to that start signal, the Quadtree Clear Address Generator 820 asserts a Clear Busy signal, which is connected to the Quadtree Block En~ble Logic block 818 and to the select input of the four MUXes B22, 824, 826 and 828.
MUXes ~2-828 are placed in the address lines between the Quadtree Address Map 81~ and the A, B, C
and D Arrays 802, B04, ~06 and 808, respectively.
MUXes 822, 824~ 826 and 828 select between the outputs of the Quadtree Address Map 810 and a single parallel address generated by the Quadtree Clear Address Generator 820 depending upon whether or not the Clear Busy line is asserted (selecting the 7~
.~ I

.

address qenerated by the Quadtree Clear Address Generator ~20 when the Clear ~usy line is a~erted). The address generated by ~he Quadtree Clear Address Generator 820 begins at location 0 and is ~tepped through every location in Arrays ~02, 804, 806 and 808. Meanwhile, ~rrays 802, 804, 806 and 808 are all ena~led by the Quadtree Block Enable Logic block 818, and all bit~ of ~he Tri-State ~us 816 are forced to logic level 0 so that 0 data appears at the data inputs of all of the Arrays. In this way, 0 values are stored in every location of each of the four Array~ B02, 804, 806 and 808, thus initializing the quadtree structure to all Empty windows.
~ eferring to FIGURE 3:L(A~, shown i5 a schematic diagram of the Quadtree Address Map 810.
As mentioned above, the Qu~dtree Address Map ~10 combine~ the (suitably 7-bit~ values WPX and WPY
with the (suitably l-bit) values MAPX and MAPY to produce four addresses, one for each of the Arrays 802, 804, 806 and 80B. WPX and MAPX are ~dded together by an Adder 822 to produce the value ~WPX~MAPX), while WPY and MAPY are added by an Adder 824 to pr~duce the value (~PY+MAPY). The various catenations shswn in the equations are accomplished by simply parallelling the appropriate lines. The ~ ~ ~3 1 7~

i four addre~s outputs are connected to the MUXes 822, B24, 826 and 828, respectively, and are used to address Arrays 802, 804, B06 and 808, resp~ctively.
Referring to FIGURE 31(B~, shown as a schematic diagram of one of the four Arrays 802, 804, 806 and 808 (the schematic diagram of each of the four Arrays is exactly the same~. Each Array 802-808 i~ comprised of nine sections. Eight of these sections are R~Ms ~or portions of RAMs), each of which stores windows at a different level of the quadtree structure. Thus, RAM 826 stores windows at level 2 of the guadtree, RAM 828 stores windows at level ~ of the quadtree, RAM 830 stores windows at level 8 9f the quadtree and RAM B32 stores windows at level 9 of the quadtree. As will be understood, the size of the ~AM ~ust increase as the quadtree level increases, since each change in level represents a four-fold increase in the number of windows. Thus, the RAM B26 llevel 2) has 1 location, the RAM 828 (level 7) has 32 x 32 locations, and the RAM 832 (level 9) has 128 x 128 locations. Each location in each RAM is an 8-bit word storing the property values of four children of one of the four windows in the window overlay being ~ubdivided (thus, A Array 802, for example, produces 1 2 ~ ~ 7 g~

the property values of the A, B, C and D children of an A window).
In the present design~ ~or a 512 by 512 pixel screen. at level 9, the four 2rrays t802-808 each contain a 128 by 128 looation ~AM ~832), each location representing four pixels. Thus, all 512 by ~12 pixels are repr~sented. The method is easily scaled up or down for other display screen sizes.
In practice~ the memory for multiple levels may be comb~ned into the same physical memory chips by placing them in separate regions of addressing space. Also, at level 9, only one bit per pixel (four bits per location) is needed because only ~
and F nodes need be represented ~there can be no P
nodes at the lowest level of the quadtree, level

9). This ~esults in a memory savings.
~ ach of these eight RAMs 826-832 have an Enable line connec~ed to them so that only one RAM
will be enabled ~t any given time (except during a clearing operation, when they ~re all enabled at once). Th~ eight RAMs are addressed by a common address line generated by the Quadtree Address Map 810, and all o~ their data lines are connected to a common Tri-State, bi-directional Data Bus 816A tPart of the same Tri-State Bus shown in FIGURE 30(~
The level g RAM 832 requires 14 bits of address --' 1 23~79~

information, the level 8 RAM 830 requires ~nly 12 bits, etc.; the ~ost significan~ bits in each o the WPX and ~PY expressions produced by the Quadtree Address Map block 810 lshown in FIGURE 3llA)) are suitably discarded for RAMs storing lower levels of the quadtree.
A combinational logic block B33 comprising a MUX B34, a Tri-State Bus Driver 836 and an ~R gate 838 performs several functions to handle v~rious "special cases." Block B33 places all zeros on Bus 816A during a quadtree clear operation; it places ~ll "l"s onto the Bus when a window outside of the Display Screen 2l2 is accessed; and finally, it emulates a level 1 RAM, as will be explained shortly.
The ~irst function of combinational logic block 833 i5 to place all zeros onto 3us 816A during a quadtree clear operation. When the Quadtree Clear Busy line ~produced by the Quadtree Clear Address Generator block 820 shown in ~I~URE 30(A)) is asserted, MUX B34 selects an input of all zeros ~nd applies it to ~us Driver 836. Meanwhile, the output of OR gate 838 is asserted, enabling the output of BU5 Driver 836 onto Bus 816A. In this way, all zeros appear at the inputs of all of RAMs B26-832.

~ ~ ~ 1 7~

~15 ~ his combinational logic also handles the case where the window being accessed is not on the Display Screen. The Quadtree Block Enable Logi~
block 81a (of ~IGVRE 30(A)) generates a signal OUT
~one for each of Arrays 802, 804, ~06 and 808) indicating that the address applied to that particular array is not for a window on the Display Screen, and thus is not a meaningful address in the Array. (~hile each of the Arrays 802, 808 c~uld be constructed large enough to contain all possible windows that could be addressed, the presently preferred embodiment of ~he present invention reduces the size of the memory needed to a minimum by simulating memory for those windows not on the screen~) If the OUT si~nal is asserted, the Tri-State Bus Driver 836 is ~n2bled, and the OUT signal itself is selected by the MUX 834 ~o as to place all infor~ation onto Data Bus ~16 (it will be recalled that an P window will never be painted; all windows not on the Display Screen will be discarded). The OUT signal will be used (as described below) to place all E information onto Data Bus 816.
Level 1 of the quadtree structure ~ay be regarded as a specific case of handling windows whi~h are not on the Display Screen. It will be recalled that windows at level 1 of the quadtree are the children of windows the siæe of ~he display screen (level 0 ~indows). Referring to FIGURES
20(A), 43(A) and 30(B), the selection of a window overlay comprising windows o~ the size of the Display Screen is constrained so that the window corresponding to the Display Screen will be both the lower left-hand window in the overlay and an "A"
window (thus, the overlay will have the arrangement shown in FIGURE 30(C) wherein th* A window is the Display Screen). Hence, the children of B, C and D
windows, by definition, will not be on the Display Screen, and must be forced to F, as discussed above. While the A window could conceivably also be F ~meaning that it is entirely enclosed by a face of a single node projection), the presently preferred embodiment subdivides the Display Screen anyway in this case. This is assured by producing all zeros on the Bus 316A for the A Array 802 (so that its four ~hildren are all Empty).
Referring ~nce again to FIGVRE 31(B~, when the Enable Block lA line is asserted, OR gate 838 produces an output which enables Bus Driver 836 onto Bus 81~A. Meanwhile, the OVT line is selected by MUX B34 and is applied to the data input of ~us Driver 836, so that the OUT value is placed onto Bus B16A. The Quadtree Block Enable Logic block 818 231~9~

(shown in FIG~RE 30(A)) assures that when Level 1 of the quadtree is being accessed, OUTA has the va}ue of ~ero while OU~B, OUTC and OUTD all have ~he values of all ones. In this way, the Display Screen (window A in the window overlay of windows the size of the Display Screen) will always be subdivided7 while th remaining windows will be discarded.
Referring to FIGURE 32, shown is a schematic diagram of the Quadtree Block Enable Logic block 818 shown in FIGURE 30(A). The function of the Quadtree ~lock Enable Logic block 818 is to enable the appropriate level RAM of each of Arrays 802, 804, 806 and 808, and to produce the OUTA-OUTD
signals indicating windows that are not part ~f the Display Screen. A signal WLEV (generated by the ~equence ContrDller block 1600) is applied to a 4-to-16 Decoder 836 which generates a plurality of mutually exclusive level lines, one for each of the levels of the quadtree ~note that ~LEV may suitably take on only 10 of 16 possible values, so that only

10 of the 16 output lines of Decoder 836 will ever be assertedl. ~ach one of ~hese 10 level lines output by Decoder 836 is connected to a duplication of Decoder Block ~37. Each of Decoder Blocks 837 comprises four 2-input AND gates 838, 840, 842 and ~44, the output of eaeh o which is connected to one of the inputs ~f an OR gate ~46, 848, B5D and 852.
The Image Window Geometry Processor 1000 ~shown in PIGVRE 25) generates four signals, POUTRX, POUT~Y, POUTLX and POUTLY, which indicates the windows in the current window overlay which are not on the Display Screen. ~hese signals must be translated to specify which of the A, B, C and D
windows are not on the Display Screen. Each of these signals is applied to one of the inputs of two of a bank of four 2-input ~R gates B54, 856, 858 and 860 to generate the following signals:

POUTA = POUTRX OR POUTRY
POUTB = POI~TRY OR POUTLX
POUTC = POU~RX OR POUTLY
POUTD = POUTLX OR POVTLY

- Each c~ne o~ these lines PO~TA, POt~TB, POUTC
and POUTD is inverted to form INA, INB, INC and IND, respectively, each of which is applied to one of AND
gates #38, 840, ~42 and 844 in each of Dec~der blo~ks ~37. The second input of each of OR gates ~46, ~4B, 850 and 852 are connected in com~uon to the Clear Busy line generated by the Quadtree Clear Address Generator B20. Likewise, each of the second 123l7~
!

~19 inputs of AND g~tes 838-B44 in each of Dec~der blocks 837 are connec~ed in c~mmon to one of the outputs of Decoder 836~
Each block enable ~utput ~the output of each OR gate B46, 848, 85a and 8523 of a given D~coder block 837 is asserted either when the Clear ~usy line is asserted (all of the level RAMs for all four of Arrays 802, 804, 806 and 808 are enabled during the period which the Quadtree Clear Address Generator 820 clears the Image Window Memory B00) or when the window addressed is in~ide the Display Screen ~as indicated by INA, INB, INC or IND) and that level R~M is selected by D~coder 836. If one or more of the windows are not on the Display Screen, the block enable output generated by the corresponding one of O~ gates B46, ~48, 850 or 852 is not asserted, but rather the corresponding one of PW TA, POUTB, POUTC or POUTD is asserted. POUTA-POUTD are each connected to one of gates 892, 894, 896 and 89~ to produce the following signals:

OUTA=POUTA AND LEYELl OUTB-POUTB OR LEVELl OUTC-POUTC OR LE~ELl OUTD=POUTD OR LEVELl 1~3~7~

22~

These fiignals are applied to combinational logic block 833 shown in FIGURE 31~B~ and discussed previously.
Re~erring to YIGURE 33, shown is a schematic diagram of the Quadtree Clear Address Generator block 820 shown in FI~URE 30(~). The Quadtree Clear Address Generator 820 accepts as an input a single bit from the Sequence Controller block 1600 shown in FIGURE 25 called the Start signal, which commands that the entire Quadtree ~;tructure stored in the Image ~indow Memory 800 be initialized to all ~ windows. The Start signal sets a Set-Reset Flip-~lop 862, the output of which is gated through an AND gate 864 with the output of a free running crystal oscillator ~65. The output of AND ~ate 864 is cvnnected to the clock input of a 14-bit binary counter 866, the output of which is applied to one of the inpu~s of each of the ~Uxes 822, ~.4, 826 and 828 shown in FIGURE 30~A).
Re~erring to FIGVRES 30(A) and 33, the output of ~he SR Flip-Flop B62 is also output to the Quadtree Block Enable Logic 818 and to the select _ inputs of MUXes 822-82~ as the Clear ~usy signalO
Hence, the MUXes are controlled to select the output of Counter 866 rather than the output of the Quadtree Address Map 810, and apply the counter ---` 12317~
~ ) 2~1 output as the address input ~o Arrays ~02, 804, 806 and 808. At the s~me time, the Clear Busy input to the Quadtree Block Enable L~gic 81B forces ~11 of the RAMs in all of Arrays 802, 804, B06 and 808 to be enabled, and places all zero data onto Data Bus 816. Counter 866 cycles from all zeros to 3F~FH, thus cycling through each address in each of Arrays 802, 804, 806 and 80B, clearing each locaticn as it cycles.
Referring to FIGURE 34(~, shown is a schematic diagram of the Data Read Map 812 shown in FIGURE 30~A)o The function of the Data Read Map 812 is to reorder the 4 x 4 window array produced by the Arrays 802, 804, 806 and 30B (shown in FIGURE 30(A)) into the traversal sequence shown in FIGURE 6(F) (i.e, the bottom left, bottom--right, top-left and top-right arbitrary traversal seguence in which any given w.i.ndow overlay is accessed). Referring to FIGURE 34(A), four eight-bit wide data inputs produced by Arrays 802, 804, 806 and 808 are applied to each of four 32-to-8 bit MUXes 868, 870, B72 and B74 (each of MUXe- ~68, 870. 872 and 874 may suitably ~e a bank of eight 4-to-1 bit MUXes). Each o~ MUXes B68-874 selects the outputs from a different one of the Arrays A-D at any given time.

317~

While the ~ata inputs to each of ~UXes 868, 870, 872 and 874 are identical, the s.ignals ~pplied to their select input~ are not. The select inputs of MUX ~68 are MAPX and MAPY; the select inputs of MUX 870 are MAPX and MAPY; the select inputs to MUX
872 are MAPX and ~APY; and the select inputs of MUX
874 are MAPX and MAPY. Thus, the 8-bit wide ~utput of each of MUXes 868, 870, 872 and 874 are different; depending upon the values of MAPX and MAPYy the output of each of Arrays 802, 804, 806 and 808 shown in ~IGURE 30(A) will be routed to the output of one of MUXes 868, 870, 872 or B74. In this way, the Data Read Map 12 performs a one-to-one mapping of the outputs of the Arrays 802-8D8 into the Window Pac~et.
Referring to ~IGURE 34~B), shown is a ~chematic diagram of the Data Write Map 814 shown in FIGURE 30(A). The function of the Data ~rite Map 814 is the converse of that of the Data Read Map 812; the Data Write Map must reorder four families of four children from the ~uadtree traversal sequence order shown in ~IGURE 6(~) to the appropriate one o~ the four arrangements shown in FIGURES 30(C)-30~F) so that the proper looations in the proper Arrays 802, 804, 806 and eo8 (shown in ~IGURE 30(A)) will be updated. The Data ~rite Map ~ ~31~9~ ~

814 ~ay suitably ~e implemented in precisely the same way as the Da~a ~ead Map ~1~ using ~our 32-~o-B
bit ~UXes 876, 878/ 8ao and 882. The select inputs for MUXes ~76, 87~, ~80 and 8B2 are exactly the same as those of MUXes 868, 870, 872 and 874, respective-ly. MUXes 876, 878, 880 and 882 are also suitably pr~vided with Tri State Enable inputs (suitably enabled during a window POP) to enable the outputs of the MUXes onto the Tri-5tate Bus 816 ~hown in FIGURE 30~A). The write enables of Arrays 802-808 are also enabled at this time.

IMAGE WINDOW PACKET PROCES!;OR

Referring to F~GURES 25 and 35, shown is a schematic diagram of the Image Window Packet Processor 900. The function of the Image Window Packet Processor 900 is to demand window packets from the Image Window Memory 800, to modify those window packets as new windows are painted by the Window Writer 1400 ~o ~hat the quadtree structure ctored in the Image Window Memory 800 is accurate, and to modify window packets as they are a~cessed (but before they have been stored back in the Image ~indow Memory 800) so that the section of the quadtree being pxocessed is always accurate (even `- ~2~17~ ~

though the quadtree structure stored in the Image Window ~emory may not have yet been modified)~ The Image Window Packet Processor 900 comprises a Child Modify Logic block 902, a Grandparent Modify Logic block 904, a MUX 906, a WPROP Register 908 and a Window Decoder 910.
As previously discussed, a window packet comprising a 4 x 4 array of windows made up of the four children of each of four contiguous (but not necessarily sibling1 parent windows is obtained from the Image Window ~lemory ~00. This window packet is input to the Child Modify Logic blt~ck 902. Al~o applied as inputs to the Child Modify Logic block 902 are the E, P or P property values of the ~our parent windows (obtained from the Window Overlay Select Iogic block llûO).
The function of the Child Modify Logic block 9~2 is to ~nodify the children of any ~ window in the ourrent window overlay to also be Fo This is necessary because a window may be painted at a high level and ~herefore marked F, but the processor does not bother to mark all descendant nodes as ~ (they will all remain E). The Child Modify Logic bl~ck 902 automatically marks all such nodes below an F

node F as they are accessed. The modified window packet is connected to an input of a MUX 906, the 1 ~3 ~ 7~ i output of which is connec~ed ~o the input of the ~PROP Register 90B. The output o~ the WPROP
Register 908 is connected to the input of the Image ~indow Packet Stack 430, the output of which is connected to the input of the Grandparent Modi f y L~gic block 904. The Grandparent Modify Logic block 904 also requires the output of the WPROP Regi~ter 908 directly and the ~BITS produced by the Window Overlay Select Logic block 1100 (W3x3X, W3x3Y, W2x2X
and W2x~Y, whieh specify the window overlay in the current 4 x 4 window packet WPROP whi~h i5 being proce~s2d ) .
The ~unction cf the Grandparent Modify Logic block 904 is to modify the parents of the current window overlay before a WPoP ~i.e. a traversal of the ~uadtree from a lower to a higher level) to mark F the parent of four children windows marked F, and to mark P any parent window having one or more children marked P or some but not all ch.ildren marked ~. The output of the Grandparent Modify Logic block 904 is connected to the other input ~f the MUX 906, and is selected by the MUX and clocked into the ~PROP Register 908 when a WPOP is performed ( i .e. when the quadtree is tras~er~ed back up f rom children ~o parent windows) so that the contents of the WPROP Register are always correc~.

7 ~ ~
I

2~6 Like~ise, the ~utput from ~he Child Modify Lo~ic block 902 is selected by the MUX 906 and clo~ked into the WPROP Register 9D8 when a W~U5H is performed (i.e. when the quadtree structure is traversed downward to subdivide a current window overlay into a 4 x 4 array)~ The output of the WPROP Register 908 i5 connected to the input of the Image ~indow Memory 800 (among other places), and i5 used to update the quadtree structure stored in the Image Window Memory whenever a WPOP is performed.
When a window i~ painted by the Wind~w Writer 1400, that window must be marked ~ in the quadtree structure so that it ~and non2 of its descend~nts) will ever be painted again. The Window Decoder 910 performs this function by setting the bits in the WPROP ~egister 90~ corresponding to windows that are written by the Window Writer 1400 to F. The Window Decoder 910 accepts as inputs the WBITS ~W3x~X, W3x3Y, W2x2X and W2x2Y~ and WNUM.
These sign~ls are encoded as shown in FIGU~ES 6(D)-6(F). In addition, the PAINT ~ignal from the Cycle Results block 1500 (which is asserted when the current window is to be painted) is applied to the Window Decoder 910. The output of the Window Decoder 910 is one of 16 mutually exclusive set lines, one for each of the 16 windows in the 4 x 4 1 23 ~ ~9~ i 2~7 window packet WPROP. When one of these ~6 lines is asserted, the appropriate 2-bits in the WPROP
Register 908 are set to ~
~ he Window Decoder block ~10 is sui~ably implemented by combinational logic. The Truth Table describing the outputs of the Window Decoder 910 as related to its inputs i~rom whirh one skilled in the art could easily construct the combinational lo~ic array required) is as follows:

~BITS ~rNuM
W~x3XW2x2X W3x3Y ~2x2Y 0001 10 11 0 0 ~ 0 0 1 2 3 0 1 1 ~12 11 14 0 1 6 î 12 13 TABLE I I

- In ~he abc~ve Table, all 9f the four possible combinations o the WBITS IW3x3X~ 1~3x3Y, W2x2X and W2x2Y~ and WNUM are listed horizc>ntally.
Thus, for every combination of these 6-bits~ one of 1 23 ~ 7~

2za the 16 output lines from the Window Decoder 910 is specified as being asserted. The encoding ~hown in Table II directly corresponds to that shown graphically in FIGVRES 6(D)-6(F). It should be noted that this one output line is enabled only if the PRINT signal f~om the Cycle Results block 1500 is asserted.
Referring to FIGURE 36(~3, shown is a s~hematic diagram of the Child Modify Logic block 902 of ~I~URE 35~ The Child Modi~y Logic block gO2 accepts the 4 x 4 window packet from the Image Window Memory block 300 of FIGURE 25 (suitably 32-bits wide) as an input. The property values of each of the families of four children windows in the 4 x 4 array are ORed by one of o~ gates 912 ~ 914, 916 or 918 (each of which is suitably a bank of eight 2-input OR gates ) with one of ~our "Full "
signals generated by the ~indow Overlay Select Logic block 1100, which are asserted if the parent of the four children windows has been ma~ked F. Thus, the output of each of the four OR gates 912, 914, 916 and 918 are t~e E, P or F property values of one family of four children windows, those prc>perty values having been "overwritten" by all F values if the parent of those four children windo~s has been 1 7 ~ ~

marked F (i.e. painted). ~ence, the subdivision of a F window will always result in F children.
Referring to FIGURE 36(U), shown is a s~hematic diagram of the Grandparent Modify Logic block 904 shown in FIGURE 35. The Punction of the Grandparent Modify Logic block 904, as discussed above, i5 to "overwrite" a window property value obtained ~rom the Image Window Packet Stack 430 on a ~POP to reflect the painting of any one or more of its descendent windows. The ~randparent Modify Logic block 904 performs this function every time a ~POP is performed to traverse back up one level in the quadtree structure.
Each output from the :Lmage Window Packet Stack 430 is connected to one input of a 5-input OR
~ates 920-930 (for a total of 32 OR gates, one for each bit output from the stack)O Each bit in each pair of :L6 bi~s output from the Image Window Packet Stack 430 indicates either P (least significant bit) or F ~mo~t significant bit) information about one of the 16 windows in ~he window packet containing the window overlay which was subdivided to obtain the current window packet. Each one of these bits will be overwritten if anyone of the other four inputs of its respective OR gate is asserted.

'7~
~30 The output of the WP~OP Register 908 ~the current window packet) i5 applie~ to the input of the Parent Reduction Logic block 932, which groups the four families of four children in WPROP
together, examines the E, P or F prQperty values of each family of our ~hildren, and determines if the parent of that family should be marked E, P or F (as mentioned above, the parent of four children ~arked F must be marked F, and the parent of four children some ~ut not all of which are marked P or having one or more children marked P must be marked P3. The Parent Reduction Logic block 932 generates eight outputs, POP, POF, PlP, Pl~, P2P, P2F, P3P and P3F, indicating whether the four parents (0-3) of the current 4 by 4 window packet containiny the window overlay should be marked P or F, respectively.
Referring to ~IGURE 37, shown is a schematic diagram of one four~h of the Parent Reduction Logic bl~ck 932 (i.e. the four~h which generates the outputs 20P and POF). FIGURE 37 shows an 8-input OR gate 934 which generates the POP
~utput, and a 4-input AND gate 9 6 which generates the POF information. It will be recalled that window property values are encoded 00 for E, 01 for P and 11 for F. Thus, if the most significant bit of a property value of a given window is logic 1, '79(~

then that window is ~. The most significant ~its of the property values of each of the four ohildren windows are input to AND gate 936. If all four bits are lo~ic 1 (indicating that all four children are F), the AND gate generates a logic 1 output for POF
(indicating that the parent of those four windows is marked F~. This is used to overwrite the most significant bit of the property value of the parent window of these childsen with a logic 1.
Likewise, if any bit o~ any of the property values of any of the four ~hildren is logic 1, then the least significant bit of the property value of the parent of the four windows should be marked logic 1 ~as all of the children are not E, the parent mus~ be either P or F, both of which are encoded to have a logic 1 in the least significant bit of ~he property value)~ Thus, OR gate 934 and AND gate 936 together generate the property value of a parent window ~rom the four property values of the ohildren of the windo~. Each of the 8 bits of the current WPROP window packet (representing four sets of four children ~ach) are pro~essed similarly to generate the property values of each of four parents.
Referring once again to FIGURE 36~B), each of the eight outputs of the Parent Reduction Logic 1 7 ~ ~

~32 block 932 are connected to an input of one o eight Grandp~rent ~indow Decoder blocks 938-952. Output POP s connected to the input o~ Grandparent Window Decoder block 938, POP is connected to the input of the Grandparent Window Decoder block 940, PlP is ccnnected to the input of Grandparent ~indow Decoder block 942,..., and P3F is connected to the input of Grandparent Window Decoder block 952 (for a total of eight Grandparent Window Decoder blocks 938-g52, one for each output of the Parent Reduction block 932).
The WBITS ~W3x3X, W2x2X, ~x3Y and W2x2Y) produced ~y the Window Overlay Select ~ogic block llOO (shown in FIGURE 25 ~ are connected to another input of each of Grandparent Window Decoder blocks 938-952. The Grandparent Window Decoder blocks 938-g52 serve to map th~ POP-P3F signals into the appropria~e OR
gates 921D-930. In other words, the Grandparent Window Decoder blocks 938-952 determine which of signals POP-P3F (~pecifying the property value of a four window overlay the children of which constitute the current window packet) correspond to which four of the 16 windows in the 4 x 4 window packet the eurrent window overlay was subdivided from.
Grandparent ~indow Decoder blocks 938-952 are implemented by combinational logic arrays. In the presently pre~erred embodiment of the present ~23~9~

invention, identical arrays are used ~o imple~ent each of ~randparent Window Decoder blocks 938 952.
ach of blo~ks 93B-952 function according to the following Truth Table:
.

WBITS H~rd-"iret ~lindow As s i gnmerl t 3x3X 1~2x2~3x3Y~12x2Y3001 10 11 O ~ O O 1 2 3 0 O Q 1 ~ 3 8 0 0 1 ~ 2 3 ~ 9 0 O O 1 4 3 6 IN 4 x 4 O 1 O 3 6 9 lZ OVER' AY

0 1 6 ~ 12 13 O ~ ~ 12 13 1~13 14 15 TABLE I I I

The 4-bit combinations along the horizontal edge of Table III are the various combinations of the WBITS ~W3x3X, W2x2X, ~3x3Y and W2x2Y). Also, along the top of Table III are the four possible combinations of 2-bits, labelled "Hard-Wired Window Assigment." These 2-bits are hard-wired inputs for each of the Grandparent Window Decoder blocks 938-952, and serve to assign a pair of Grandparent Window Decoder bl~cks to each of window numbers 0-3 1 2~ 1 7~1 (thus~ only the first cQlumn of outputs under the ~ard-Wired ~in~ow Assignment 00 is v~lid ~or the pair of Grandparent Window Decoder blocks 93~ and 940: like~ise, only the output columns un~er the ~ard-Wired Window Assignment values 01, 10 and 11 are valid for the pairs of Grandparent Window Decoder blocks 942 and 944, 946 and 948, and 950 and 952, respectively). The output of each Grandparent Window decoder blocks 338-952 is enabled by the input which it receives ~rom the Parent Reduction Logic ~lock 932.
One of the 16 outputs of each of the "P"
Grandparent Window Decoder blocks 938, 942, 946 and 950 are connected to every oth~er one of the OR ga~es (the "P" gates 920, ..., 924 nd 92B) corresponding to the least significant bit of the property values for the 4 x 4 window packet ~utput from the Image Window Packet Stack 430. Likewise, ~ne o~ the 16 outputs of each of the "F~' Grandparent Window Decoder ~locks ~40, 944, 948 and 952 are connected t~ the other set of every other OR gate (the "F"
gates 922, ...~ 926, and 930) corresponding to the most significant bit of each property valu of the 4 x 4 ~indow packe~ QUtpUt by the Image ~indow Packet Stack 430.

31~
.

~35 In this way, the P and F property value deter~inati~ns for four vindows produ~ed by the Parent Reduction Logic block 932 are mapped into the 4 x ~ window packet produced by the I~age Window Packet Stack ~30 by the Bard-Wired Window Assi~nment (of Tabl~ III) together with the WBITS ~W3x3X, W3x3Y, W2x2X and ~2x2Y~. The outputs of each P and F pair of OR gates 920-930 represents the "overwritten" property value for one of the 16 windows in the 4 x 4.

IMAGE WINDOW GEOMETRY PROCESSOR

Referring to FIGURE 3B, shown is a schematic diagram o~ the Image Window Geometry Processor block 1000 of FIGURE 25. The f~nction of the Ima~e Window Geometry Processor 1000 is to determine the position of a given window overlay on the view plane, and to determine whether the window is on the Display Screen.
The Image Window Geometry Processor 1000 is divided into two general parts, the ~indow Bounding Box Geometry block 1002 (which determines the families o~ window geometric values in the X and Y
dimensions), and the Window Polygon Geometry block 1050 lwhioh determines the families of window . ~ 1 23 ~

23fi geometric v~lues in the D0, Dl and D2 directions).
The Window Bounding Bo~ Geometry block lD02 shown in ~IGURE 3B is duplicated twice, onee for X' and once for Y'; likewise, the Window Polygon Geometry block 1050 is duplicated three times, one duplication for each for D0, Dl and D2.
The Image Window Geometry Processor 1000 accepts as inputs the WBITS lW3x3X, W2x2X, W3x3Y and W2x2Y) generated by the Window Overlay Select Logic block 11~0 shown in ~IGVRE 25, and the signal WLEV
(~pecifying the level of the quadtree at which the current windows are f~und) generated by the Sequence ControlleF block 1600. The WLEV signal is connected to the input of a 4-to-16 Decoder 1004, which asserts one of 16 mutually exclusive outputs, which ~ogether specify e, ~he size of the windows at the current level (the value of E as shown in FIGURE
23(A) d1vided by an appropriate multiple ~f 2).
The W3x3X signal ~W3x3Y for the Y' duplica~ion of the Window Bounding Box Geometry block 1002) is applied to the input of an Adder 1006, the output of which is connected to an input - of a MUX 10D8. The output of MUX 1003 is connected t~ the input of a WP Register 1010. The WP Register 1010 as initialized at the beginning of the generation of an image to the oFigin 104 of view 12317~ 1 ~37 plane 66 WPX IWPY or the Y duplication of the ~indow Bounding ~ox Geometry bl~ck 1002~ ~hown in FIGURE 23(A). The output of the WP Registe~ 1010 is connected to the input of the Image ~indow Geometry Stack 440, the output of which is connected to the other input of the MUX 1008.
On a WPUS~, the output of Adder 1006 is selected ~y MUX 1008 and is clocked into the WP
Register 1010 while the old contents of the WP
Register 1010 is pushed onto the Image ~indow Geometry Stack 440, thus placing the origin of a parent window overlay onto the Window Geometry Stack and placing the origin of the child window overlay into the ~P Register 1010. On a WPOP, MUX 1008 ~elects the output of the Ima~e ~indow Geometry Stack 440, which is clocked into the WP Register to restore the origin of the parent window overlay into the register (when the quadtree is traversed back up after a subdivision h~s been processed).
The output of the WP Register 1010 is connected to the input of an Adder 1012 after being hard-wire shifted one bit to the left by block 1014 (note that block 1014 merely represents the connection of 3 logic 0 to the LSB of Adder 1012, and the connlec~ion of the output of the WP Register 1010 to the remaining bits of the Adder, so that the -- 123~79~

output oP the register i~ actually multiplied by 2 before being applied to the Adder). The othe~ input of Adder 1012 is connected to W2x2X (~2x2Y for the Y
duplication of the Window ~ounding Box Geometry block 1002). The output of Adder 1012 is connected to the other input of the Adder 1006. Thus, the output of Adder 100~ WCX = (WPX*2)~W2x2X+W3x3X) [(WPY*2~+(~2~2Y~W3x3Y~ for the Y' duplication of the Window Bounding Box Seometry block 1002]. This value i5 the origin of the window overlay selected within ~he current 4 x 4 array, the selection of which was discussed previously in the discussion of FIGURES 6(D)-6(F).
The ~3x3X and W2x2X bits (W3x3Y and W2x2Y
bits for ~he Y' duplica~ion of the Window Bounding Box Geometry ~lock 1002) are also both connected to ~-input XOR gate 1016, the QUtpUt ~f whi~h is the CMAPX ~.it (CMAPY bit for the Y' duplication of the Window Bounding Box Geometry block 1002) for the next subdivision of windows, as previously discussed in conjunction with FIGUR S 301C)-30(F). The output of the X~R gate 1016 is applied to the input of a ~UX 1018; the output of the MUX is connected to the M~P Register 1020. The output of the XO~ gate 1016 is also connected to one input each of two 2-input AND gates 10~2 and lD24. The output o~ the AND

7 9 ~

gates 1022 and 1024 ~re i!ll50 applied to the I~UX
1018, and thus tc~ ~he input of the MAP Regi~ter l02n, The ~ap Register :1.020 contains three values, the ~IAPX (I~APY~ bit; and ~he POUTLX and POUTRX bits (POUTLY and PO~TRY bits for the Y' duplication of the Window Bounding ~ox Geometry block 1002), which indicate which (if any) windows in the current window overlay are not on the Display Screen (this register must be initialized before e~ch image is generated~. The POUTLX (POUTLY) output of the MAP Register 1020 is connected to the other input of AND gate 1022, while the POUTRX
lPOUTRY) output of the MAP Register 1020 is connected to the other input of the AND gate 1024.
In this way, whi~h of the windows in the child window o~erlay are not on the Display Screen is determined from which of the parent windows in the current window ~verlay ~re off of the screen and the lvcation of the child window overlay within the 4 x 4 array (specified by the WBITS~.
The outputs of the MAP Register lD20 is also connected to the input of the Image Window Geometry Stack 440, the output of which is connected to inputs of the MUX 1018. On a WPUSH, the ou~put of the MAP Register 1020 i5 pushed onto the Image ~2317~

2~0 Window Geometry Stack 440, and the MAPX, POUT~X and POUTRX lMAPY, POUTLY and POUTRY) values f~r the ~ubdivided overlay are clocked into the MAP Register so that the appropriate child values are present in the register when the quadtree is traversed down one level. Likewise, on a WPOP, the output of the Image ~indow Ge~metry ~tack 440 is selected by the MUX
1018 and clocked into the MAP Register lD20 so that the former values are reloaded into Register 1020 when the quadtree is traversed back up a level.
~ he Window Polygon Geometry block 1050 of the Image Window ~eometry Processor 1000 is dupli-cated three times, once each ~or D0, Dl and D2. The Window Polygon Geometry block 1050 accepts as an input the wsITs (W3x3X, w2x2x, W3x3Y and W2x2Y) together with WNUM (specifying which window of the four windows in the current window overlay is being process~d), generated by the Window Overlay Select Logic block 1100 and the Window Select Logic block 1200, respectively. W3x3X, ~2x2X and one of the 2 bits of WNUM are connected to the inputs of a 3-to-1 ~UX 1052, while W3x3Y, W2x2Y and the other bit of WNUM are connected to the inputs of a 3-to-1 MUX
10~4.
Both MUXes 1052 and 1054 select these three inputs according to select inputs from the Sequence 317~ ~

2~1 Controller block 1600. W3x3X and W3x3Y are ~elected by ~UXes 1052 and 1054, respectively, during a WPUSH; W2x2X and W2x2Y are selected during a ~BOX
test; ~nd WNUM is selected during a PI test ~nd an E
test. ~he outputs of MUXes 1052 and 1054 are connected to a 2-to 4 Decoder 1056, which generates one of Eour mutually exclusive outputs. These outputs of the Decoder 1056 are used to select one of four Shift Registers in a WDOFF Table 1058. The WDOFF Table 1058 is initialized with zero and three appropriate window offsets, as mentioned previously in the discussion of FIGURES 23(B)-23(D).
Th~ output of the WDOFF Table 1058 is connected to a Latch 1060, the output of which is connected to one input of an Adder 1062. The output of Adder 1062 is connected to an input of a MUX
1064, the output of which is connected to the input of a WPD Register 1066 (which is initialized at the beginning of each image generation to WPD0, WPD1 or WPD2 as shown in FIGURE 23tA), one for e~ch duplica-tion of Window Polygon Geometry block 1050 for D0, D1 and D2). ~he output of the WPD Register 1066 is connected to the other input of Adder 1062. The output of the WPD Register 1066 is also connected to the input of the Image ~indow Geometry Stack 440, the output of which is connected to the other input 1 2 3 ~ 7~

24~

of MUX 1064. MUX 1064 selects the output of the Image Window Geometry 5ta~k 440 during a WPOP, which is clooked into the WPD Registez 1066. On a ~PUSH, the MUX 1064 selects the output of Adder 1062, which is clocked into the ~PD ~egister 1066~
It will be recalled from the discussion of ~IGVRES 23~A)-23tDl that the preferred embodiment calculates the critical vertices of a given window in the current window overlay from the critical vertices of the current 4 x 4 window array in three stages~ first, a 3 x 3 window array is selected from the 4 x 4 window array, and the critical vertices of the 3 x 3 array are determined; then, a window overlay (a 2 x 2 window array) is selectcd from the selected 3 x 3 array, and the critical vertices for the overlay are determined; finally, a single window is selected ~rom the window overlay, and its critical vertices are determined.
Immediately after a ~PUSH, the WPD Register 10S6 contains the ~PD0 (WPDl, WPD2) Qffsets for the 4 x 4 window array (as shown in FIGURE 23(A)). At this time, ~UXes 1052 and 1054 select the ~3x3X and W3x3Y bits, respectively, to select from the ~DO~F
Table 1058 the appropriate offcet to calculate the critical vertices of the 3 x 3 array selected from the 4 x 4 array. This offset value is latched into 3 1 79~

~3 Latch 1060 and is applied to ~dder 1062 so that the offset from the ori~in of the view plane to the ~ritical vertex of the 3 x 3 array i5 applied to the input of MUX 1064.
Once Latch 106D has latched, the output of the WDOF~ ~able 1058 is free to change withou~
affecting the calculated result of Adder 1062.
After the WPUSH, a BBOX cycle is begun. The W2x2X
and ~2x2Y inputs of MUXes 1052 and 1054 are selected, which select from the WDOFF Table 1058 the apprspriate window offset for computing the critical vertices of the selected window overlay. The value discussed above for the 3 x 3 array is clocked into the WPD Reqister 1066, and the window offset for the window overlay is latched in Batch 106~. As before, a new value is produced by Adder 1062; this timel it is WCD0, the offset from the view plane origin to the cri.tical vertex of the selected window overlay.
~CD0 is output from the Image Window Geometry Processor block 1000.
Once Latch 1060 has latched a second time (for a BBOX cycle) if a PIT (or ET) cycle is entered, MUXes 1052 and 1054 select the WNUM value, which is used to select from the WDOFF Table 1058 the appropriate of fset for calculating the critical vertex of individual windows in the window -- 5 23 1 7~

overlay. Recall that all four windows in the overlay are tested simulta~eously during a B~O~ test and, in ~act, the di~gonal (D0, Dl, D2) inormation is not needed (it's simply updated from the 3 by 3 to the 2 by 2 in preparation for a BBOX or E test.
For a PI or E test, however, the diagonal informa-tion for a single window is needed, and therefore, generated from the 2 by 2 values. As WNUM changes ~as the PI and E tests are performed on different ones of the windows in the window overlay) t the output WOFF changes. A new value of ~CD0 will not however be produced until the next WPUSH (or WPOP~.
Also contained in the Window Polygon Geometry block 1050 is a WDIAG Shift Register 1068, which is initialized by the Initializing Gontroller block 160 at the start of each image generation to contain the value WDIAG0 (WDIAGl and WDIAG2 for the Dl and D2 dupl;cations of the Window Polygon Geo-metry ~I.lock 1050) calculated as ~hown in FIGURE
23(E). As with all of the Shift Registers previously discussed, the WDIAG register shifts one bit to the right for ev~ry WPUSH, and one bit ~o the left on every WPOP, to keep the value which it contains correct for the level of the quadtree being accessed.

31~9~

2~5 Referri~g to FIGURES 39~A) and 391~ hown is a schematic diagram of the Window Overlay Select L4gic blo~k 1100 of FIGURE 25. The function of the ~indow Overlay Select Logic block 1100 is to select the appropriate window overlay from the 4 x 4 window array comprising the current window packet. ~he Window Overlay Select Logic block 1100 comprises two blocks~ th~ WBITS Processor 1102 (which is duplicated twioe, once for X' and once for Y'); and the WPROP Reduction Logic block 1198. The WBITS
Proce~sor block 1102 calculates the WBITS as previously discussed and shown in FIGURES 6(D) 6~E).
Although the WBITS Processor block 1102 is duplicated for each of x' and y', only the x' duplication will ~e discussed; the y' duplication is directly analogous.
The WPX signal generated by the Image Window Geometry ProcessDr 1000 is input to a ~arrel Shif$er 1104, which shifts WPX a predetermined number of places to the left depending upon the value of WLEV generated by the Sequence Controller block 1600. The Barrel Shifter 1104 suitably shifts the ~PX value between 0 to a pl~ces to the left; at the bottom level of the quadtree (level g, the -``` 12317~

2~6 ~mallest window size)~ the Barrel Shifter will shift 0 places to the left, while at quadtree level 1 (the largest size windows in the quadtree structure). the Bar~el Shifter will shift eight places to the left. The output of Barrel Shifter 1104 is the signal ~PX~2e which is the origin of the 4 x 4 window array in units of ~ixels (this conversion is required because the location of nodes are specified in units o~ pixels)O The WPX value is a parent value and is thus multiplied by 2e rather than e to obtain ~he 4 x 4 origin.
The output of Barrel Shifter 1104 is connected to one input of an Adder 1106, the other input of which is connected to the value e (the si7e of windows in pixels at the current level of the quadtree). The output of Adder 1106 is thus equal to (WPX*2e)~e ~the location of line a in FI~URE
6(D))-Each of the bits of e are gated with thevalue ~3x3X by AND gate 1108 (suitably a bank of 16 2-input AND gates)~ the output of which is connected to an input of an Adder 1110. Thus, the output of Adder 1110 is equal to [WPX*2e)~e~(e ~3x3X) lthe location of line c shown in FIGURE 6~E)).

NPX and NPY are also input to the Window Overlay Select Logic block 1100. It will be 7 ~ ~

2~7 recalled that (NPX, NPY~ is the origin 76 of bounding box 74 of node projection 68 shown in FIGURE 6~). NPX is connected to the input of an Adder 1112, the other input of which is cvnnected to the value ax~CNUM) generated by the O~ject ~ode Geometry Processor block 700. The output of Adder 1112 is thus NPX~ax(CNUM), the origin of the boundin~ ~ox of the child node projection.
The output of Adder 1106 and ~he signal NPX
are connected to the inputs of a Magnitude Comparator 1114; the output of Magnitude Comparator 1114 is asserted when NPX > (WPX~2e)+e. Likewise, the outputs of Adders 1110 and 1112 are connected to the two inputs of a Magnitude Comparator 1116. The output of Comparator 1116 is asserted when NPX+ax ~CNUM) ~ ~WPX*2e)+e~e~W3x3X). Finally, the output of Adder 1112 is also suitably connected to an input of a ~agnitude Gomparator 1118, the other input of which as conneeted to logic 0. The output of Comparat3r 1118 is asserted when NPX~ax (CNUM) > 0.
The outputs of Comparators 1114, 1116 and 1118, together with WNUM (the output from the Window Select Logic block 120~ of FIGURE 25 which indicates which one of the four windows in the current window overlay is being processed~ are input to various inputs of one of two MVXes 1120 and 1122. MUXes 1120 and 1122 select between these inputs to calculate the WBITS, depending upon various relationships between node level and window level~
~UXes 112~ and 1122 have their select inputs ~onnected in parallel to a signal generated by the Sequence Controller block 1600 (not shown)~
The input selected when MUXes 1120 and 1122 have a 00 placed on their select lines are ~oth "don't cares", ~can be set to either 0 or 1) these inputs are selected when the projection of the object node i~ larger than the size of the Display Screen (i.e. the node level is above the screen level). Since a window overlay cannot be found , within ~,:he quadtree structure which will enclose the i bounding box of a node projection which is larger than the Display Screen, this is a special case which the Image Display Processor block 152 proces.ri~les without requiring ~BITS information.
Those ~killed in the art will recognize that this ~pecial case could have been avoided if the Image Window Memory block 1800 stored a quadtree structure larger than the Display Screen (large enough to enclose the projection of the universe whe~ scaled up by the maximum scale factor)O ~owever, in the presently preferred embodiment of the present invention, only the Display Screen is subdivided by 7~

2~9 the guadtree ~tructure ~nd stored in ~he Image Window Memory bl~ck 800 in order to save in hardware costs ~information that will never be displayed is not stored, so that a much smaller memory may be u~ed) and to decrease processing time (little time is spent discarding windows not on the Display Screen).
When the select lines to MUXes 1120 and 1122 are set to 01; MUX 1120 sele~ts a logic 1 input, while M~X 1122 selects the output from Comparator 1118. This occurs when the quadtree level 0 is a~eessed ~i.e. each of the 16 wi.ndows in the current window packet is the size of the Display Screen). In this case, W3x3X and W3x3Y are both set to logic 1, thus selecting the upper right-hand 3 x 3 within the 4 x 4 window packet, as shown in FIGURE 6(D). Referring to FIGURES 6(D1 and 43(A), the Display Screen 212 is defined to be the center window of this 3 x 3 (i.e. wind~w 12 in FIGURE
6(D~), so that the Display Screen will ~e included in any of the 4-window arrays selected from the 3 x 3. The values of W2x2X and W2x2Y select the window overlay within the 3 x 3 dependin9 upon whether the bounding box of the node pro jection is above the x' axis and whether it is to the right of the y' axis ~f the view plane.

250 ~3~79~1 When the value 10 is ~pplied to the select inputs of MUXes 1120 and 1122, MVX 1120 selects the output of Comparator 1114, while MUX 1122 selects the output ~f Comparator 1116. This is the general case, where the node and window levels are equal and four contiguous windows in the current window packet can be found to form a window overlay which encloses the bounding box of the node projection. In this general case, the WBI~S must be determined arthimetically.
As ~hown in FIGURE 6 (D), the position of the left edge of the bounding box of the node projection is compared with the position of line a to determine th~ value of W3x3x, and similarly, within the selected 3 x 3, the position of the left ed~e of the bounding box defined by the node projec-tion is compared with the position of line c in the 3 x 3 shown in FIGURE 6(E) to determine W2x2X.
These ~omparisons are implemented by comparat~rs 1114 and 1116. Analogous comparisons are made with respect to lines b and d shown in FIGURES 6(D)-6(E) to determine ~3x3Y and W2x2Y~
When the value 11 is applied to the select input of MUXes 1120 and 1122, the MUXex both select the least significant bit of ~NUM (the most significant bit of WNUM is selected by the Y

251 ~23~9~

duplication o~ the ~BITS Prt~cessDr block 1102). As shown in FIGURE 6(~ r this provid~s selection uf c)ne window from the window overlay selected by the WBITS .
- The output of MVX 1120 is connected to an input of a MUX 1124, while the output of MUX 1122 is connected to an input of MUX 1126. ~he outputs of MUXes 1124 and 1126 are connected to the input of the ~13x3 Register 1128 and the WZx2 Register 1130, respectively. The output of P~egisters 1128 and 1130 (the WBITS for the current window overlay) ~re connected to the input of the WBITS Stack 450, the output of which is connected to the other inputs of MUX 1124 and MUX 1126. MUXes 1124 and 1126 select - the output of ~UXes 1120 and 1122, respectively~
during a ~PUSEI and ~3BOX test, which are then clocked into Registers 1128 and 1130, respectively~ On a WPOP, PlUXes 1124 and 1126 select the output of the WBITS Stack 450, which is clocked into Registers 1128 and 1130 to relocate a parent window overlay after some of its children have been subdivided.
The ~utputs of Rcgisters 1128 and 1130 are, it will be recalled, connected to a number of the blocks in the Image Display Processor block 152 ~for instance, the WBITS are used by the Image Window Packet Processor 900, the Image Window Geometry `

252 ~3~.79113 Processor 1000, the Window Writer block 1400, and the CycIe Results block 1500). These outputs are also further processed within the Window Overlay Select Lsgic block 1100 by the WPROP Reduction Logic block 1198. The function of this block is to take the WBITS toqether with WPROP (the current 4 x 4 window packet ~enerated by the Image Window Packet Processor block 900) to ~enerate the E, P or F
property values of the our windows in the current window overlay. The WPROP Reduction Logic block 1198 is implemented in the presently preferred embodiment by a combinational lQgic array implementing the following Truth Table:

i l ~

~;~3~7~1~

~IBIl`S OVRLAY ItINDO~
NU!IBER
~le~3X ~2~2X1~3x3Ytl2x2YO 1 2 3 .

O O l 2 3 O O 1 O 2 3 a 9 O O l l 8 9lO ll WINDOW
O 1 O O 1 4 3 b PROPERTY
O 1 O l 3 6 9 12 VALUES
O 1 l O 3 6 9 12 OUTPUT
O l 1 1 9 1211 14 O O O l 4 3 6 O O l ~ 6 9 1~
O l O 3 6 9 12 O l l 9 121 l 14 O l 6 712 13 TABLE I V

WINDOW SELECT LOGIC

Referring to FIGURE 40, shown is the Window Select Logic block 1200 of FIGURE 25. Thc function ~3~Y9~) of the Window Select Logic ~lock 1200 is t~ ~upply f rom the current window ov rlay those non-Full windows whi~h have passed the B~OX ~est. The Window Select Logic block 1200 accepts as an input the results of the ~BOX test (suitably four l-bit signals BPASS0, BPASSl, BPASS2 and BPASS3 supplied by the Cycle ~esults block 1500, which are asserted if their respective windows (encoded as shown in FIGURE 6~F)) pas ed the BBOX test and are non-Full), together with the E, P or F property values o~ the current window overlay (generated by the Window Overlay Select Logic block 1100).
The BBOX Results signals are connected to an input of a MUX 1202, the output of which is connected to the input of the BBOX Results Register 1204. The output of ~egister 1204 is connected to the input of the B~OX Result Stack 46Q, the output of which is connected to the other input of MUX
1202. On a WPUSH, the MUX 1202 selects the BBOX
Results inputs l~PASS0, BPASSl, BPASS2 and BPASS3) generated by the Cycle Results block 1500, and clocks these values into the BBOX Results Register 1204. On a WPOP, MUX 1202 selects the output of the ~BOX Results Staclc 460, which is clocked into Register 1204. Thus, the BBOX ~esults values are saved in the ~BOX Re~ults Stack 460 on a WP~SH, and 317~ ~

2~5 are ret~ieved after a subdivision of the ~urrent window overlay has been processed and a WPOP is executed.
~ he output of the BBOX Results Register 1204 is connected to the input of a Priority Encoder 1206. Priority Encoder 1206 generates a l-bit output WREM, which is asserted if any bit at the output of Register 1204 is asserted; thus, WREM i5 asserted if at least one of the windows in the current window overlay is non-~ull and passed the BBOX test (i.e~ needs to be further processed).
WREM is applied as an input to the Sequence Controller block 1600.
Priority Encoder block 1206 also generates an output ~NUM, suitably a 2-bit value which indicates the window number in the window overlay next to be processed according to the quadtree traver~;al sequence shown in FIGURE 6~F). This output is connected to the input of a WNUM Register 1208. The (unresistered) output also is connected to the select inputs of a MUX 1210, the inputs of which are the E, P and F property values of the f~ur windows in the current window overlay. Thus, the property value of the one window in the window overlay selected by WNUM is generated at the output of ~UX 1210; this output is also connected to the - -` 123179~

2~6 input sf the ~NUM Register 120~. The output of the WNUM ~egister 12U8 comprises both a signal indicating which one of the four windows in the current window overlay is next to be processed, and the E, P or ~ property value of that window.
~ he WNUM output of the WNUM Register 1208 is also connected to the input of a 2-to-4 Decoder 1212, which also receives a gating input from the Sequence Con~roller block 1600. The output of Decoder 1212 is four mutually excluslve l-bit lines which are connected to the Reset inputs of the BBOX
Register 1204. When the value WNU~ of the next window in the current window overlay to be processed is clocked into ~he WNUM Register 1208, the Dec~der 1212 clears the BBOX Results value corresponding to that window in the BBOX Results Register 1204 so that Priority Encoder 1206 is informed that the window has already been processed, and therefore will not select that window again.

CUT PLANE PROCESSOR

Referring to FIGURE 41, shown is a detailed block diagram o~ the Cut Plane Processor bl~ck 1300 of ~IGURE 25. The function of the Cut Plane Processor ~lock 1300 is to determine whether the --- 1 2~
I

current node lies at least partially within the region to be di~played defined by ~he cut planes~
and if so, whether it is intersected by a cut plane. The Cut Plane Processor block 1300 produces two outputs: a signal Cut Plane OK is asserted if at least a portion of the current node lies within the region to be displayed; and Cut Plane INT i5 asserted if the current node i5 intersected by a cut plane. If ~ut Plane OK is asserted and Cut Plane INT is not, then the node must lie entirely within the r~qion to be displayed.
The Cut Plane Processor block 1300 comprises a Cut Plane Geometry block 1301 and a Cut Plane Arithmetic block 1350. There is one set of these blocks for each pair of cu~ planes used to de~ine the re~ion to be displayed. The Cut Plane ~eometry block 1301 accepts as an input the signal CNUM (produced by the Node Select Logic block 600), which speciies which of the eight nodes in the current node packet is being processed. CNUM is connected to the input of a 3-to-8 decoder 1302 which produces eight mutually exclusive output lines, one for each node in the node packet. The output lines of the 3-to-8 decoder 1302 are used to select one of eight shi~t registers in the ak Table 1304. The ak Table 1304 together with Adder 1306, 3 1 7 ~9 MUX 1308 and ~n ~PK Regis~er 1310 produce ~he various geometric l~cations of the left-most and right-most vertices of the projection of the ~urrent node onto the cut plane test plane shown and discussed in conjunction with ~IGURE 14tB). The operation of these components is very much similar to equivalent structures in the Node Bounding Box Geometry block 702 of the Object Node Processor block 700 shown in FIGURE 29. Cut Plane Geometry Stack 470 permits storage and recovery of computed offset values when the octree structure is traversed downward and upward, respectively.
The Cut ~lane Geometry block 1301 contains two additional registers, the KDIAG Register 1312 and ~he LDIAG Register 1314. It will be under~tood that the ak Table 1304, the KDIAG Re~ister 1312, the LDIAG Register 1314 and the NPK Register 1310 are all initialized to the values shown computed in FIGURES 14tB), 22(A) and 22(B). The ak Table 1304 and the XDIAG Register 1312 are both shift registers which shift according to the level of the octree currently being accessed. The NPK Register 1310 and the LDIAG Register 1314 are both fixed registers.
Cut Plane Geometry block 1301 produces three values: NCK (the location of the left-most vertex of the projection of the current node cnto I ~ 3 1 7 9 ~ . . . .

2~9 the cut plane test plane), KD~AG ~the offset E~om the le~t-most vertex of that node projection to the right~most vertex) and LDIAG (the distance between the two cut planes). These three signals are sent to the Cut Plane Arithmetic block 1350, which performs the cut plane test discussed previously in conjunction with ~IGURE 14(8). In IN/OUT Register 1370 is a single-bit register which is initialized by the Initializing Controller block 160 to either logic 1 or logic U, depending upon whether the region to be displayed is that region defined between the cut planes or that region outside of the region between the two cut planes. The output of the IN/OUT Regi~ter 1370 is used to select ~ MUX
1368, which selects an IN and an OUT input, as appropriate. The IN and OUT signals are produced by Adder 1352, M~gnitude Comparators 1354~ 1356, 1358 and 1360, AND gate 1362 and OR gate 1364, which per~orm the arithmetic comparisons for the cut plane test previously described in the discussion of FIGURE 14(B). AND gate 1366 produces the Cut Plane I~T signal ~which is sent to the Sequence Controller block 1600 of ~IGURE 25), while an OR gate 1372 produces the Cu~ Plane OK signal (which is sent to the Cycle Results block 1500 of FIGVRE 25).

-` 123179Q
J

It will be understood by those skilled in the art that by duplicating the pair of Cu~ Plane Geometry block 1301 and the Cut Plane Arithmetic block 1350, the region to be displayed may be further restricted to that defined by two pairs of cut planes. The Cut Plane INT signal of both the duplications of the Cut Plane Arithmetic block 135D
are ORed together, while the Cut Plane OK signal are ANDed together. Additional cut planes and more sophi~ticated visibility determination criteria are easily added.

Ref~rring to FIGU~E 4~, shown is a de~ailed block diagram of the Cycle Results block 150D of FIGURE ~5. The Cycle Results block 1500 c~mprises four blocks, the ~creen Intersection Logic blDck 1502~ the BBOX Arithmetic block 1520 r the PI Test Arithmetic block 1540 and the E Test Arithmetic block 1560.
The BBOX Arithmetic block 1520 performs the Bounding ~ox test on the four windows in the current window overlay simultaneously. and generates four sin~le-bit outputs, each of which indicate whether one of the four windows in the overlay passed the 1~23~L79~
~1 BBOX test. These outputs are each ANDed with t~e ~ost significant ~it of the E, P or F property value of the corre ponding window (indicating Full or not Full) by four 2-input AND gates 15~2, 1584, 1586 and 15880 The outputs of ~ND gates 1582, 1584, 1586 and 1588 are the signals BP,9SS0-BPASS3 previously discussed in the description of FIGURE 40.
The four outputs BPASS0-BPASS3 are also ORed together by OR gate 1590 the output of which i5 ANDed with the Cut Plane OK signal (produced by the Cut Plane Processor block 1300 ) to generate a single output BPASS which indicates whether any one of the four windows in the current window overlay have passed the BBOX test, are at least partially within the region defined by the cut planes to be displayed, and are non-~ull. The ~PASS signal is ~ent to the input of the Sequence Controller block 1600 to enable it to de~ermine whether furth@r testing of the window overlay by the PI and E tests i~ necessary.
The Screen Intersection Logic block 1502 performs the BBOX test in a special case, when the ~ize of the windows in the current window overlay is equal to or greater than the ~ize of the Display Screen. It will be recalled that the only section of the view plane which ic ~rganized into the 3l79~ ) 26~

quadtree ~tructure is the Display Screen, since only those nodes which project onto the Display ~creen will be visible to a viewer. When the current window size is e~ual to or grea~er than the size of the Di~play Screen, the preferred embodim2nt of the present invention simplifies the B80X Test into a simpler Screen Intersection te tv which merely determines whether the Display Screen ~the only window of interest in an array of windows of size equal to or greater than the size of the display screen) intersects any portion of the bounding box defined by the projection of the current node. The Screen Intersection Logic ~lock 1502 generates a single output, SPASS, which is asserted when ~he bounding box intersects the Display 5creen.
~ he PI Test Arithmetic ~lock 1540 performs the Polygon Intersection Test on individual windows in the c~urrent window ~verlay to determine if those windows intersect the projection of the current node. The PI Test Arithmetic block 1540 generates a ~ingle output, PPASS, which indicates th~t the window under tes~ has passed the Polygon Intersection Test.
The E Test ~rithmetic block 1560 perorms the Enclosure Test on individual windows in the current window overlay to determine if those windows ~ ~3~7~0 are enclosed by one of the three faces of the current node projection. A given window suitably is tested simultaneously for the Enclosure Test with respect to all of the three Eaces of the node projection. The E Test Arithmetic block 1560 generates the PAINT signal, which is asserted when the window under test passes the E Test with respect to any one of the three faces of the node projection. It will be understood that a given window may be enclosed by, at most, one of the three faces; due to finite precision arithmetic operations, however, sometimes the E test w~ll indicate that a given window is enclosed by more than one face at the same time. In such an instance, one o~ such faces is arbitrarily chosen.
~he E test arithmetic block 1560 also yenerates the FACE NUMBER signal, suitably a 2-bit value indicating which of the three faces of the node projection encloses the window un~er test ~if it is in fact enclosed by any of them).
It will be seen from FIGVRE 42 that each of the BBOX Arithmetic block 1520, PI Test ArithmetiC
~lock 1540 and E Test ~rithmetic block 1S60 input~ ¦
~he geometry of current windows (the family oE
values describiny the location of the current window overlay and the single window under test in the X, ~ 23 1 790 Y, D0, Dl and D2 dimensionsJ and the geometry of the current node (the family of values indicati~g the position of the current node projection in the X, Y, D0, ~1 and D2 dimensions), generated by the Image Window Geometry Processor block 1000 and the Object Node Geometry Processor block 7D0, respectively.
Because the location of the Display Screen is fixed, the Screen Intersection Logic block 1502 requires only the information containing the geometry of the current node.
Referr1ng to FIGURE 43(A),-shown is a yraphical illustration of the special case in which the Screen Intersection Logic block 1502 is used to perform a sim~lified BBOX test ;n order to determine if the Display Screen intersects the current node projéction. As mentioned above, the Screen Intersection Logic block 1502 is used instead of the Bsox Arithmetic block 1520 to perform the BBOX test wh~never t~e size of th~ windows in the current window packet is equal to or greatèr than the size o th~ Display Screen. It will be recalled from the discussion of FIGURE 20(A) that the lower left-hand corner of the Display Screen 212 is located at point ~WPX, WPY)-~0, 0) (the origin 104 oE view plane 66), and that the dimensions of Display Screen 212 ~re 512 x 512 pixels. It will be readily understood to . .

~L23~9~

those skilled in the art that if any of the four following eguations are true, then the bounding box 76 of the current node projection 68 (re~erring to ~ICURE 7~ does not intersect with the Display ~creen:

NPX ~ axtCNUM) 2 512 NPX ~ ~x(CNUM~ + bx s 0 NPY ~ ay(CNUM) 2 512 NPY + ay(CNUM) ~ by c 0O

~ The above equations determine respectively whether the left edge of the bounding box of the current nQde projec~ion i5 to ~he right of the right ed~e of the screen, wheth~r the right edge of the bounding box is to the left of the left edge of ~he screen, r~hether the bottom edge ~f the bounding box is above the top edge of the Display Screen, and whether the top edge of the bounding box vf the node projection is below the bottom of the Display Screen~. These equatiDns are conventionally implemented by ADDERc 1504, 1506, 1508 and 1510 and Magnitude Comparators 1512, 1514, 1515 and 1;16.
The output of Comparators 1512, 1514, 1515 and ~516, ~each representing the resul~s of the comparison of one of the equations above) are connected to tAe 1 23 1 7~1 2~6 input of a 4-input NOR ga~e 1518,.the output of which will be asserted only i~ none of the four equations ~re satisfied. The outpu~ of NOR gate 1518 is the signal 5PASS, which indicates that the ~ounding ~ox of the current node projecti~n intersects the Display Screen.
The presently preferred embodiment does not permit windows of the view plane to be larger than the display screen, but instead, subdivides nodes until their projections define a window overlay comprising windows of level 0 (the size of the display screen). The screen intersection test may be applied to any node projection, no matter how large.
Referring to FIGURE 44~B), shown is a schematic diagram of a portion of the BB~X
~rithmetic block 1520 ~hown in FIGVRE 42. Referring to FIGURES 7 and 44(B~, the operation of the BBOX
Arithmetic block 1520 may ~e bet~er understood in conjunction with the geometry of the BBOX Test. The BBOX Arithmetic block 1520 performs the BBOX test simultaneously for the four windows in the current window overlay, generating four ~utput sign~ls PASS0-8PASS3, indicating respectively if ~indows 0-3 tl~beled ~s shown in FIGURE 6(F)) of the current window overlay pass the BBOX test~

~ 2 3 ~

Referring tc FI~U~E 44(~ he loqic array block 1529 required to determine if one of the windows in the current window overlay inter~ects the bounding box of the current node projection is chown (four logic array blocks 1529 are required, one for each window in the window overlay). Adders 1522, 1524, 1526 and 1528 together with Magnitude Comparators 1530, 1532, 1534 and 1536 implement the following equations:

tW~ + e) > NPX ~ ax (CNUM) WX c NPX + ax (CN~M) ~ bx IWY + e) > NPY t ay (CN~M) WY < NPY ~ ay (CNUM) + by.

IThese eguations are satisfied if the right edge of the wi,ndow under test is to the right of the left edge of the bounding box of the current node projection, the left edge of the window under test is to the left 4f the r ght edge of the bounding box, the top edge of the window is above the bottom edge of the bounding box, and the bottom edge of the window is below the top edge of the bounding box, respectively). The output of Comparators 1530, 1532, 1534 and 1536 are connected to a 4-input AND
gate 1538, the output of which is asserted only if -"` 1 23~7~

~68 all our equati~ns are sa~i~f~ed ~i.e. when the window under test intersects ~he bounding box of the current node projection).
Referring to FIGURE 44IA), shown is a block diagram of the Window Location Logic block 1521 contained in the B~OX Arithmet;c Logic block 1520.
The Window Location Logic block 1521 generates eight outputs, the X' and ~' coordinate values (in pixels) of each of the four windows in the current window overlay. The Window Location Lo~ic block 1521 requires as inputs WLEY (the window level of the current overlay), e (the size of the current windows), WPX and WPY tthe or.igin of the current 4 x 4 array) and the WBITS ~W3x3X, W3x3Y, W2x2X and W2x2Y, specifying the current window overlay within the 4 x 4 window array). The Window Location Logic ~lock 1~21 generates the outputs WX0, WY~ ~Xl, WY1, WX2, WY2, WX3 and ~Y3, each pair respectively specifying the location of the lower left-hand vertex (i.e. ~he window origin) of each of the four windows in the current window overlay. The values WX0 and WY0 are connected to the ~X and ~Y inputs of the duplication of the logic block 1529 shown in FIGURE 44(B) for the 0 window in the current wîndow overlay WXl and WYl are connected to the WX and WY

~ 23~7~

inputs for the duplication of logic array block 1529 - for window 1, etc.
The Window Location ~ogic block 1521 is suitably a combinational logic array implementing the following equations:

wXo = ~X2 = (WPX 2e) ~ (2 AND W3x3X)~(e AND W2x2X) X3 = WXO ~ e - WYO = WYl = (WPY-'-2e) 4 (e AND S13x3Y)~(e AND W2x2Y~
WY2 = WY3 = ~YO ~ e (Those skilled in the art will recognize that these equations may be implemented with binary Adders, 3arrel Shifters, and logic ~unction gates, keeping in mind that the value e is a power of 2).
Referring to FIGURE 45, shown is the schematic diagram of the PI Test Arithmetic block 1540 shown in FIGURE 42. Referring to FIGURES 10 and 44, the PI Tes~ Arithmetic block 1540 performs the polygon intersection test on one of the four windows in ~hP current window overlay by selecting a critical vertex of the window for each of the six edges of the node projection, and then comparing the position of each one of the six edges with its corresponding critical vertex to determine if the window intersects ~he node projection. ~s shown in 1~317~

~IGURE 9, the selection of one of the f~ur vertices of the window as the critical vertex for a given edge of the node projection is dependent upon the 510pe of the edge and the orientation of the edge with respect t~ the interior ~f the node projection (note that the critical vertex selection is the same for the projection of any node in the octree struc-ture with respect to any window in the quadtree structure for a given viewing angle), Referring to FIGURE 45, the PI Arithmetic block 1540 comprises six Magnitude Comparators 1541-1~46. The output of each Comparator 1541-154S is connected to an input of one of six 2-inpu~ XOR
qates 1547-1552. The outputs of each of the six XOR
~ates 1547-1552 are all ANDed ~ogether by a 6-input AN3 gate 1553, the output of which is the PPASS
signal (which indicates that the window under test.
has passed the Polygon Intersection ~est). The function of XOR gates 1547-1552 is to reverse the inequality sign o the comparison implemented by Comparators 1541 154~, depending upon the orientation of the interior direction of the node projection with respe~t to the corresponding edge being compared (as discussed previously). The other input of each of the XOR gates is connected to one o~ three outpu~s ID0-ID2 of a Interior Direction Register 1554 (~hown in ~IGURE 42) which is loaded by the Initiali~ing C~ntrvller block 160 of F1~RE
15 at the start of each new image generation with three single-bit values, each of which respectively indicate the interi~r direction of the node projection for each o~ edges D0, D1 and D2.
The PI Test Arithmetic block 1540 also comprises Binary Adders 1555 and 1556 to generate the following values:

NDl ~ NCDO ~IDl - ~lCDû ~ WDOOFF~WNUM) ND2 = NCD2 ~ID2 - ~CD2 4 WD20FF(WNUM) ND3 = NCDl WD3 = WCDl ~ WDlOFF(WNUM) ~ID4 ~ NCDO ~ NDIAGO WD4 = WD~ JDIAGO
ND5 = NCD2 ~ NDIAG2 WD5 = W1)2 ~ WDIAG2 UD6 = ~CDl ~ NDIAG1 WD6 = WD3 + ~IDIAC1 In the preferred embodiment of the present invention, XOR gate 1547 (connected to the output of the Comparator 1541 comparing ~Dl with NDl~ and XOR
gate 155D (not shown, connected to the QUtpUt of the comparator 1544 (also not shown) comparing ND4 with WD4) have an input connected to the output ID0 of the Interior Direction Register 1554 (which is asserted when the half-plane defined by edge D0 of the current node projection lying below the edge 2~7g~

contains the int~rior of the node projection), XOR
gates 154~ and 1552 ~not shown, connected to comparators 1543 and 1546 comparing ND3 with WD3 and ND6 with ~D6, rQspectively) each have an input connected to the output IDl of the Interior Direction ~egister 1554 (which is asserted when the half-plane defined by the line passing through the edge Dl to the left of line Dl contains the interior of the node projection) and XOR gates 1548 and 1551 (not shown, connected to comparators 1542 and 1545 comparing ND2 with WD2 and ND5 with WD5) are connected to an output ID2 of the Interior Direction Register 1554 (which is asserted when the half-plane defined by a line extending through edge D2 of the node projection and lying below edge D2 contains the in~erior of the node projection).
Referring to FIGURE 46, shown is a schema~.ic diagram of one of blocks 15~5 of the E
Test Arithmetic block 1560 shown in FI~URE 42 ~i.e.

the block which performs the enclosure test for face #3 of the node projection shown in PIG~RE 12). The E Test Arithmetic block 156Q performs the enclosure test simultaneously for each of the three faces of the node pr~jection with respect to a given window under test. Magni~ude Comparators 1566, 1567, 1568 and 1569 assert an output if WDll > ~Dll, WD7 > ND7, 3 1 7~1~

WD8 < ND8 and WD16 c ND16, respectively. The output of each of Comparat~rs 1566-156g a~e connected to an input of 2-input XOR gates 1570-1573, the other input of which is connected to one of three outputs ~f Interior Direction Register 1554 (shown in FIGURE
42~, The purpose of XOR gates 1570-1573 is to permit the direction of the inequality sign of each of the comparisons performed by Comparators 1566-1569 depending upon the ~rientation of the various edges with respect to the interior o~ the ~ace of the node projection.
Arithmetic Blocks 1575 and 1576 (suitably comprlsed of binary Adders, not shown) calculate the following values for the duplication of the Arithmetic Block 1565 for Pace #3 of the node projection:

Ndll = NCDO ~Jdll ~ WCDO - ~lOOFF(WNUM) ~ WDIAGO
Nt8 8 NCD0+FDIAGO SID8 = ~CDO ~ WOOFF(WNUM) Nd7 = NeDl~FDIAGl ~lD7 = WCDl ~ WlOFF(~NUM) - l~JDIAGl Ndl6 = NCDl~NDIAGl WD16 = WCDl ~ WlOFF~llNUM) ~ rom the geometric diagram shown in ~IGURES
12, 21(A)-21(F), and FIGVRES 23~A)-23~E~, those skilled in the art will be able to calculate the equati~ns to be implemented by the duplications of Arithmetic Blocks 1575 and 1576 for the other two faces of the node pr~jection.

WINDOW WRITER

Referring tc ~IGURES 47(A)-(B), shown is a schematic diagram of the Window Writer block 1400 shown in PIGVRE 25. The function of the Window Writer is to paint all of the pixels on the Im~ge Display block 1~4 of FIGURE 15 corre~ponding to a window in the quadtree for which the Cycle Results block 1500 has issued a PAINT signal. The Imaye Display block 154 is addressed on the pixel level.
Thus, the Window Writer block 1400 must convert the values describing ~he ori~in ~f the window to be painted (WPX, WPY, the WBITS and WNUM) together with ~LEV (which determines the si~e of the window to ~e painted) into addresses of adjacent pixels of the Image Display block 154 corresponding the area occupied by the window to be painted.
Adders 1402, 1404 and 1406 are cascaded to generate the X' coordinate value of the origin of the window to be painted as (W3x3X + WPX) ~ W2x2X
WNUM tLSB), as is shown in FI~URES 6~D)-(F).
Likewise, Adder~ 1408, 1410 and 1412 compute the Y' coordinate value of the origin of the window to be I

~75 painted as lW3x3Y ~ ~PY) ~ ~2x2Y I WNUM (MSB).
These values are shifted by Barre~ Shifters 141~ and 1416, respectively. The shif~ select inputs of both of Barrel ShiEters 1414 and 1416 (i.e. the inputs which control the number of places shifted) are connected to ~LEV, which indicates the level in the ~uadtree at whieh the current window is located.
The function of Barrel Shifters 1414 and 1416 are.
thus to conver~ ~he address of the origin of the window to be painted to an appropriate pixel location on the Image Display block 154 (Barrel Shifters 1414 and 141~ shift the address of the window at the bottom level of the quadtree zero places, a window at the next to bottom level of the quadtree one place, etc.).
The output of ~arrel Shifter 1414 i~
connected to the input of a programma~le counter 1418, ~hile the output of Barrel Shifter 1416 is connec~ed to the input of a programmable counter 1420~ A Register 1422 and a Register 1424 are each loaded with the value e, the si~e of the window to be painted.
Counter 1418 is sequentially incremented by one through all values from its starting value to its starting value ~ e, thus addressing every pixel in the Image Display block 154 on the bottom row of ~ - ~ ~
- - -I

~3~7~1 the area of the Image Display to be painted. At that point, the Counter Control block 1426 increments counter 1420 by one, and loads ~ounter 1418 to its starting value again. Counter 141B once again is incremented from ;ts starting value to its starting value ~ e, ~hus addressing every pixel in the second row from the bottom of the area of the Image Display block 154 corresponding to the window to be painted. This process continues, where counter 1420 is held at a constant value while counter 1418 is incremented through every address in a row of an area to be painted, following which counter 1420 is incremented by one, counter 1418 is loaded to its initial value and is once again incremented to another row, until counters 1418 and 1420 both contain their initial values ~ e (indicating ~hat the entire area of the Image Display block 154 to be painted has been addressed).
Once tl.~is occurs, the window has been completely painted on the Image Display block 154, and a signal lnot shown) is sent to the Sequence Controller block 16Q0 ~of FIGURE 25) indicating the painting process is complete.
The output of a MUX 1428 is sent to the Image Display block 154 ~along with the outputs of counters 1418 and 1420), which provides information ~77 . ~3~7~

concerning color of the pixels to be painted. ~UX
142~ selects between the outputs of three registers, the PACEl Register ~430, the FACE2 Register 1432 and the FACE3 Register 1434, which are loaded by the Initializing Controller block 160 before the start o~ each image generation to contain a different color and intensity value ~suitably 24 bits wide comprising 8 bits each for red, green and blue) for each of the three faces of a given node projection~
The select input of MUX 1428 is connected to the FACE NUMBER output qenerated by the Cycle Results box 1500 to select the color of the pixels to be painted depending upon which face of the current node projection the w.indow to be painted is enclosed by. As menti~ned previously, providing diff2rent colors and intensities for the projections of the different faces of the node projection adds three-~imensional realism to the final image.
It will be understood by those skilled in the art that the color of pixels to be painted could be affected by factors other than ~ust the FACE
NUMBER (such as property value information other than the P or ~ property value of the current node) to permit object nodes corresponding to sections of the object having different densities to be painted different colors.

!

27~

The presently pre~erred embodim~nt provides an optional enhancement to ~he generated image by "anti-aliasing" pixels when painting windows at level 9 (the bottom) of the quadtree. Rather than having windows at level 9 of the quadtree correspond one-to-one with pixels of the Image Display ~lock 154, the presently preferred embodiment in fact optionally addresses the Image Display as a 256 x 256 array of pixels (each representing four "subpixel" cells, corresponding to ~our of the lowest level windows in the quadtree). To paint a level 9 quadtree window, one-~ourth of the window-intensity value is summed ~instead of written) into the associated Image Display pixel. Of course, ~he Image Display must be cleared before the image generation process begins. Additional "levels" of anti aliasing can be performed (one pixel can be summed lnto by 4 level 8 quadtree windows or 16 level 9 windows, for example).
The purpose of anti-aliasing is to average sets of pixels into single pixels (4 to 1 in this case) so as to reduce the 2-D spatial frequency components of the ima~e. Edges of objects t~en appear as lines or curves rather than as staircases.

Surfaces also appear smoother. The result is an image which is more pleasing to the human eye. When ~3~7~3~

implemented as described above, anti-aliasing i~
carried on only ~hen writing windows of level 9 in the quadtreeO

SEi;2UENCE CONTROLLER
-Referring to FIGURE 48, shown is a state diagram of the Sequence Controller block 1600 of ~I~URE 25. The unction of Sequence Controller block 1600 is to provide signals to control the sequence o events occurxing in the Image Display Processor block 152, and thus to directly to contrQl the operation of each of the blocks in the Image Display Processor.
It will be underst~od by those skilled in the art that a considerable num~er of timing problems involving the sequence of operation of all of the various components of a digital logic device of this complexity result during implementation which must be solved in order to ensure that proper values are calculated and reach their destination before they are required. It will likewise be understood that the speed of operation of the various components used to implement the digital logic device determine the speed at which it may operate. Sillce many of these design choices are 2~0 entirely arbitrary and well wit~in the capabilities o~ those skilled in the art, t~ey are not discusse~
an this appli~ation.
The Image Display Processor block 152 in the preferred embodiment of the present invention is implemented as a finite~state synchronous sequential circuit having eight states: NPUSH, ~PUSH, 8BOX, PIT, ET, NPOP and WPOP. Peferring to ~IGURE 48, only six states are shown, because the PVSH state is actually divided into a ~PUSH and a NPUSH position, while the POP state is actually divided into a NPOP
and WPOP position. IE the Imase Display Processor block 170 is either in the WPUSH or the NPVSH or ~oth, the processor is said to be in the POP state;
likewise, if the Image Display Process~r block 170 is either in the NPOP or the WPOP state or ~oth, it is said to be in the POP state.
The Initializing Controller block 160 (of FIGURE 15) starts the operation of the Image Display Processor ~lock 152 by sending a start signal whieh forces the machine into the INI~ state. The INIT
state continues to loop upon itself through path 1 50 long as the signal GO (which is asserted when the Initializing Controller block 160 has completed generating the values of all of the appropria~e node and window geometry values and initializes the Image 28~

Display Processor block 160 with th~se value~ is unasserted. When the G~ signal is asserted, the machine changes state along path 2 and enters the ~30X state.
~ here are five state transition paths from the BBOX state; the machine will traverse one of these f ive paths depending upon the results of the BBOX test. ~henever the size of the current windows is smaller than the size of the Display Screen and one of the four ~indows in the current window overlay pas~es the ~OX test, the PI test i5 to be performed on the first window in the quadtree traversal sequence which passed. Path 3 is traversed to the PIT state.
a h 4: state transition path 4 i~
traversed to perform a NPOP and/or a ~POP. If all o~ the windows in the current window overlay fail the BBOX test, the machine is in lockstep (meaning that t~le node and window levels are the same, as discussed previDusly) and there are no non-E nodes remaining in the eurrent node packet, a NPOP is perform~d. Likewise, if the size of the current windows is equal to or greater than the size ~f the Display Scre~n and the projection of the current node does not intersect the Display Screen ~i.e. the screen intersection test has failed) and no nodes 2~2 remain in the current node packet, a NPOP is likewise performed. When the ~urrent window size is less than the size of the Display Screen~ and all o the windows in the current window overlay fail the ~BOX test and there are no nodes remaining in the current node packet, a ~POP is performed. Finally, when the size of the current window is less than the size of the Display Screen and all of the current windows in the window overlay fail the BBOX test and the machine is not in lockstep (meaning that the node level is not the same as the window level, i.e.
that a full node has been encountered and the window~ that intersect it have been further subdivided to locate which windows are fully enclosed by that full node) a WPOP must be performed.
Path 5: Path 5 is traversed from the BBOX
state to the PUSH state, and must also be separated into a WPUSH and a NPUSH. Path 5 is traversed from the BBOX state t~ the PUSH state to perform a NPUSH
whenever the size of the current windows is equal to or greater than the size of the Display Screen and the Di~play Screen intersects the current node pro-jection (i.e. the screen intersection test is passed~. A WPUS~ is also performed in the case where the size of the current windows is equal to 2~3 the size of the Display 5creen (i.e. when the windows are st level 0 sf the quadtree structure).
Path 6: Path 6 causes the transition of th~ BBOX state back to the BBOX state. Path 6 is traversed when the size of the current windows is less than the si~e ~f the Display Screen, none of the current windows of the window overlay passes the BBOX test, and there are non-Empty nodes left in the current node packet. In this case, the next node ~according t~ the ~-to-O tra~ersal sequence of the octree) in the current node packet is selec~ed and the BBOX test is performed on it. This path is also traversed when the size of the current windows is equal to or greater than the size of the Displ3y 5creen, the screen intersection test fails and there are nodes remaining in the current n~de packet.
Once the machine is in the PIT state, it performs the polygon ;ntersection test for one of the windows in the current window overlay as discussed previously. It ~ay exit the PIT state thr~ugh paths 7, B, 9, 10 or 11.
Path 7. Path 7 causes a change ~f state from the PIT state to the ET state; this ~ccurs in one of two cases. Path 7 is traversed whenever the PI test is passed, the current node is F, the current window is E~ and the machine i5 not in I 2 ~ l 7 9 ;

2~4 lock~ep (i.e. ~he node level do~s not equal the ~indow level be~ause wi~dows have been subdivided to find those windows which intersect the Full node).
The other oase is when the PI test is passed and the ~urrent window is at the very bottom level of the quadtree (so that it cannot be further subdivided).
Note that the ET state (which performs the enclosure test~ is only performed on ~ nodes because P nodes must be further subdivided before they can be so processed (recall that those wind~ws enclosed by a ~ull node only are paintedl~ Likewise, the ET state i5 only entered if the current window is E because P
windows must be further subdivided while F windows are discarded (since only E windows are ever pain~ed)o Path 8. Path 8 is traversed to change the machine ~rom sta~e PIT to the PV5~ state. Path 8 is traversed to cause a NPUS~ whenever the PI test is passed ~nd either: the current node is P; or the ~urrent node is F, the windows in the window overlay for the current node projection are not at the bottom level of the quadtree and the current node is intersected by a cut plane; in this case, the current node must be subdivided. Path 8 is traversed to cause a WPUSH when the PI test is passed and the current window is P (to subdivide the window). Likewise; path B is tra~ersed to ~ause a ~PUS~ if the PI test is passed and the machine is in lockstep (i.e. node level equals window level) and the window level is not at the bottom level of the quadtree; the ET state is never entered when the machine is in lockstep because in this condition the current wind~w is by definition larger than the current node projection ~even though the current window m~y intersect the current node projeetion, it cannot enclose the node).
Path ~. When path 9 is traversed, the machine changes from the PIT state back to the PIT
state. This occurs whenever a PI test fails but there are still windows remaining in the eurrent window overlay; in this case, the next window in the window overlay (according to the quadtree traversal sequence~ is obtained and the PI test is peformed on it.
Path 10. Path 10 changes the state from the PIT state to the POP state. A NPOP is performed whenever the PI t2st fails, there are no windows remaining in the current window overlay, there are no non-E nodes remaining in the current node packet and the machine is in lockstep (in this case a WPOP

is also performed). A WPOP (without a NPOP) is performed when the current window fails the PI test, .

7 ~ ~

there are no windows remaining in the current ~indow overlay and the machine is not i~ lockstep (~eaning that the windows have been subdivided below the node level t~ locate those windows enclosed by a Full no~e).
Path 11. Path 11 is traversed from the PIT
state to the BBOX state when the PI test fails, there are no windows remaining in the current window overlay, there are non-E nodes remaining in the current node packet and the machine is in lockstep.
Once the machine is in the ET state~ it performs the enclosure test for one of the windows in the cur rent window overlay, as discussed previously. It may exit the ET state through paths 12, 13, 14 and 15.
Path 12: Path 12 causes the machine to go from th~ ET state to the ~BOX state. The machine traverç,es path 12 whenever the current window passes the E test (and is painted), the current node pro jection is at the bottom level of the quadtree, and there are n~n-E nodes remaining in the current node packet; since, at ~ost, only ~ne window in the current window overlay can be enclosed ~y the current node projection ~guaranteed to be true when the node is at the bottom level of the octree), processing of that node is complete, and the 7 ~ ~ .. ..

2~7 remaining n~des in the current node packet must be processed. Path 12 i5 also traversed if th~ E test is failed, the current node projection is at the ~ottom level of the quadtree (which also means that the current win~ow level is at the bottom of the quadtree~, there are no windo~s remainin~ in the current window overlay to be processed, and there are nodes remaining in the current node packet to be processed; in this case, likewise/ the next node is to be obtained.
Path 13. Path 13 is traversed from the ET
state to the POP state to perform a NPOP whenever the E test is passed, the current node projection level is at the bottom level of the quadtree, and no nodes remain in the current node packet: processing of that subdivision of the octree is complete ~again remember.ing that at most, one window can be enclosed by a node at the bottom lev~l o~ the octree), and the next level up of the octree must be traversed.
P~th 13 is traversed to cause a NPOP also wheneYer the E test fails, the current node is at the bottom level o~ the octree, there are no windows remaining to be processed in the current window overlay~ and there are no nodes in the current node packe~ leEt to be processed. In these two cases, a ~POP is also performed (that is, Path 13 is traversed to cause a 7~3~

WPOP and a ~POP whenever th~ E ~est passes, the current node is ~t the bottom level of the octree, and no nodes remain in the current node packet~.
Path 13 is also traversed to cause both a NPOP and a WPOP whenever the E test fails, the current node is at the bottom level of the octree, and there are neither any windows to be processed in ~he current window overlay nor any nodes left to be processed in the current node packet. Path 13 is traversed to cause a WPOP whenever the E test is passed and there are no windows remaining to be processed in the current window oYerlay. Likewise, path 13 is traversed to cause a WPOP whenever the E test fails, the current window level is at the bottom of the quadtree, no windows remain to be processed in the curren~ window overlay, and the current node is at the bottom level of the octree.
Path 14. Path 14 is traversed to cause the machine ~o change from the ET state to the PIT state in one oF two cases. ~i rst, whenever the E test passes, the current node i5 not at the bottom level of the octree, and there are windows remaining to be processed in the ~urrent window overlay (re~all ~hat while the BBOX test is performed on all four windows in t~e window overlay simultaneously, the PI and E

tests are per~ormed sequentially on individual ~Z3~79~

windows in the overlay). Path 14 is also traYessed when the E t~st fail~, the current level is at the bottom of ~he quadtree, and windows remain iQ the current window overlay to be pr~cessed (the current window cannot be further subdivided because it is at the bottom level, so no action is taken and the next window to be processed is o~tained).
Path 15. Path 15 is traversed to cause the machine t~ change from the ET ~ta~e to the WPUSH
state whenever the E test has failed and the window level i~ not at the bottom level of the quadtree.
This condition occurs when the machine subdivides windows but not n~des ~i.e. goes below lockstep).
The POP st~te may be exited via pa~hs 16, 17 and 1~.
Path 16. Path 16 is traversed ~o change the state from a NPOP to a BBOX state whenever there is a node remaining in the current node packet.
Path 16 is also traversed when a WPOP but not a NPOP
was performed, there are no windows remaining in the current window overlay, there are nodes remaining in the current node packet and the machine is in lo~kstep.
Path _. Path 17 is traversed to remain in the POP state in four cases. First, path 17 is traversed whenever a NPOP is performed and the new 3 3 7 ~

current nGde packet has no non-Empty n~des re~aining in it: in this case, a second NPOP is immediately per~ormed. Path 17 is also traversed when a NPOP
was just performed, the new current node packe~ has no non-Empty nodes remaining in it and the window level is below the screen level; in this case, a second NPOP and WPOP are performed. Path 17 is traversed when a WPOP w~s just performed, there are no non-Full windows in the new window overlay, there are no non-Empty nodes in the new current node packet, and the processor is in lockstep; in this case, both a NPOP and WPOP are performed. Finally, path 17 is traversed when a WPOP was just performed, the machine is not in lockstep and there are no non-Full windows remaining in the new window overlay; in this case, a second WPOP i5 perf~rmed to look for windows yet to be processed.
Path lB. Path 1~ is traversed to change the tate of the machine from a POP state to the PIT
state. This occurs when a WPOP was performed without a NPOP and there are windows remaining in the current window overlay; before the window packet just POPed was PUSHed~ the ~BOX test had been performed on all four windows in the window ~verlay, so that the only windows remaining are those which had passed the BBOX test. To continue processing - I 23 1 7~

29~

this overlay where pr~cessing was left o~f requires the PI test next be perfor~ed on the next window remaining in the overlay ~according to the quadtree traversal sequence).
Path 19: Path 19 is traversed to change the state of the machine from a PUSH ~tate to the BBOX state. This path is always traversed (without condition) at the end of a PUSH cycle.
The state ~ransitions described above for the State Transition Diagram shown in FIGURE 48 may be summarized in the following State Transition Table:

1. INIT ~ INIT: GO
2. IU~ ~ BBOX: GO
3. BBOX ~ PIT: (BELOW.BPASS) 4~. PBOX - NPOP: (8ELOW~BFAIL~LOC~STEP~NRE~
4 (LELOW)oSFAIL~NREM) 4b. ~EOX ~ ~POP tBELOW.BFAIL.LOCKSTEP.NREM) ~ (BELOW.BFAIL.LOCKSTEP) 5~. BBOX - NPUSH: ~BLOW.SPASS) 5b. BBOX ~ ~PUSH: (SCREEN.SPASS) 6. BBOX - BBOX: ( BELOW~ BFAIL.LOCKSTEP. NPEM~
BELOW.SFAIL.NREM) 7. PIT ~ ET: (PPASS.NFULL.~E~PTY.LOCKSTEP~
~PPASS.WSUBPX) 8a. PIT ~ NPUSH: (PPASS.NPART) ~ ~PPASS.IN~.NSUBPX) 8b. PIT - ~PUSH ~PPASS.WPART) ~ (PPASS.LOCKSTEP.~SUBPX) 9. PIT PIT: (PFAIL.NREM) 10a. PIT ~ NPOP: (PEAIL.WREM.NREM.LOCKSTEP) 5 ~ 3 1 790 lOb. PIT , WPOP: (PFAIL.WREM.NREM.LOC~STEP) (P~AIL.~REM,LOCKSTEP~

11. PIT ~ BBOX: (PFAIL.WREM.NREM.LOCKSTEP)

12. ET ~ BBOX: (EPASS.NSUBPX.NREM) ~ (EFAIL.NSUBPX
.WREM.~REM) 13a. ET ~ NPOP: (~PASS.NSUBPX.NREM) ~ (EFAIL.~SUBPX
.WREM.NREM
13b. ET - WPOP: ~EPASS.NSUBPX~NREM) ~ (EEAIL.NSUBPX
~REMoNREM) ~ (EPASS.WREM.NSUBPX) (EFAIL.~SUBPX.WREM.NSUBPX) 14. ET ~ PIT: ~EPASS.NSUBPX.~REM) ~ (EFAIL.~SUBPX
.WREM) 15a. ET UPUSH: not allowed 15b. ET ~ ~PUSH: (EFAIL.WSU8PX) 16a. NPOP - BBOX: NREM
16b. WPOP ~ BBOX: ~NPOP.~REM.NREM.LOC~STEP) 17a. NPOP ~ ~POP: NREM
17b. NPOP ~ WPOP: ~NREM.BELOW) 17c. WPOP ~ NPOP: (upop.w~EM.LorRsTEp.NREM) 17d. WPOP ~ ~POP: (WREM.LOCKSTEP) ~ (NPOP.WREM.
.LOCKSTEP.NREM) lBa. NPOP ~ PIT: not allowed lRb. ~POP ~ PIT: ~NPOP.NREM) l9a. NPUSH B80X Always l9b. WPUSH ~ BBOX Always TABLE V

The following definitions apply to the logic variables used in the 5tate ~ransition Table:

~ELOW : True if the node level (NL~V~ i~ below the screen level ~quadtree level 0) ~nd above or ~qual to the bottom lev~l of the quadtree (level 9).
~FAIL : True if none of the windows in the window overlay passed the ~BOX test.
BPASS : True if Any of the windows in the wind~w overlay passed the BBOX test E~AIL True if an Enclosure Test fails.
EPA5S : True if an Enclosure Test passes.
GO : True when the Initilization Controller block 160 has completed initializing the Image Display Processor.
INT : True if one of the cut planes intersects the curr~nt node.
LOCKSTEP : True if the window level (WL~V) is equal to the Node Level (NLEV).
NFULL ~ True if the current node is Full.
NPART : True if the current node is Partial.
NREM : True if there are either Partial or ~ull nodes left to be processed in the current node packet.
NSU~PX ; True if the window overlay for the current node projection compri~es windows at the bottom level of the quadtree.

I ~ 3 1 7 91~ 1 PFAIL : True if a Polygon fntersection ~est failed.
PPASS : True if a Polygon Intersection Test passed .
SCREEN : True if the window overlay for the current node projection is composed of windows each of which are of the size equal to the Display Screen.
SFAIL : True if a Screen Intersection Test failed.
SPASS ~ True if a Screen Intersection Test passed.
WEMPTY : True if the current window is Empty.
WPM T : True if the current window is Partial.
WREM : True if windows remain to be prvcessed in the current window oYerlay.
WSUBPX . True if the current window level is at the bottom level of the quadtree.

Referring to ~IGURE 49, shown is a schematic diagram of the Sequence Controller block 1600 o~ the presently preferred embodiment of the present invention. ~he Sequence Controller comprises a Next State Logic block 1602 (suitabiy comprising a combinational logic array)~ a State Register 1604 and a System Clock Oscillator 1606 1 7 ~ ~ 1 2g5 ~suitably 2 crystal-controlled oscillator). the contents of the 5tate Register 1604 is the current state ~f the Image Display Processor block 152, suitably encoded into an 8-bit binary value so that one output line is asserted for each of the eight states. The State Register 1604 is continuously clocked by the output from the System Clock 1606 (which also is connected to the rest of the Image Display Processor block). The output of the State ~e~ister 1604 is connected to the various blocks of the Image Display Processor blvck 152, and controls the sequence of events in the Image Display Processor.
The output of the State Regicter bloek 1604 is also connected to the input of the Next State Logic block 1602 lsince the next state to be stored in the State Register is determined in part by the present state). Also applied as inputs to the Next State Logic block 1602 are all of the signals used in the 5tate Transition table. While some of these signals have not been previously discussed individually, those skilled in the art could readily derive them from the signals that have been discussed using simple logic operations.

It will be understood by those skilled in the ar~ that given the State Transition Diagram of 12317~d ~IGURE 48 and the State Transiti~n Table ~able V~, the outputs o~ the Next ~tate ~ogic block 1602 as a function o~ the inputs of that block are ~ompletely described (except for the arbitrary assignment of binary values to encode the various states).
Moreover, while the Next State Logic block 1602 is implemented as a combinational logic array in the preferred embodiment of the present invention to increase speed of operation, other implementations, such as a ROM (where the inputs address the ~OM in the information s~ored in each location in the ROM
is the nex~ state), a microprocessor, or any other group of hardware which implements the State Transit.i.on Diagram of FIGUR 4~ and the State Transition Table V ~ay be employed.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiments but on the contrary, it is intended to cover various modi~ications and equivalent arrangements included within the scope and spirit of the appended claims which ~cope is to be accorded the broadest inter-pretation so as to encompass all such modifications ~nd equivalent structures.

Claims (98)

WHAT IS CLAIMED IS:

1. A method for generating a two-dimensional image of a three-dimensional scene comprising at least one object, said method comprising:
(a) providing input data volumetrically defining said object within a three-dimensional universe;
(b) progressively subdividing the volume of said three-dimensional universe into subdivisions;
(c) projecting said subdivisions of step (b) which are contained by said object onto a view plane;
(d) progressively subdividing the area of said view plane into subdivisions;
(e) determining which of the subdivisions of said view plane are enclosed by said projections of said subdivisions of said three-dimensional universe;
and (f) painting areas of a display screen corresponding to said areas of said view plane determined by said deter-mining step (e) to be enclosed by said projections.

2. A method for generating a two-dimensional image of a three-dimensional object, comprising:
(a) providing input data volumetrically defining said object within a three-dimensional universe;
(b) progressively subdividing the volume of said three-dimensional universe into subdivisions;
(c) projecting said subdivisions of step (b) which are contained by said object onto a view plane in a predetermined order wherein subdivisions visually obstructing, from a predetermined view point, other subdivisions containing said object are projected before said other subdivisions;
(d) progressively subdividing the area of said view plane into subdivisions;
(e) determining, for each of said projections, which of the subdivisions of said view plane are enclosed by said projection; and (f) painting areas of a display screen corresponding to said subdivisions of said view plane determined by said determining step (e) to be enclosed by at least one of said projections, each of said painted areas being painted only for the first projection in said sequence determined by said determining step (e) to enclose said subdivision of said view plane to which said area of said display screen corresponds.

3. A method as in claim 2 further including the step of selecting said predetermined view point according to parameters specified by a user.

4. A method as in claim 2 wherein said progressively subdividing step (b), said progressively subdividing step (d), and said determining step (e) are performed by hard-wired digital logic elements.

5. A method as in claim 2 wherein said progressively subdividing step (b) and said projecting step (c) are performed recursively for smaller and smaller subdivisions of said three-dimensional universe until a predetermined resolution limit is reached, and said progressively subdividing step (d), said determining step (e) and said painting step (f) are performed recursively for smaller and smaller subdivisions of said view plane until a predetermined resolution limit is reached.

6. A method for generating a two-dimensional image of a three-dimensional object, comprising:
(a) providing input data volumetrically defining said object within a three-dimensional universe;
(b) progressively subdividing the volume of said three-dimensional universe into subdivisions;
(c) defining a subset of the volume of said three-dimensional universe to be displayed;
(d) projecting said subdivisions of step (b) which are contained by said object and which lie within said subset onto a view plane;

(e) progressively subdividing the area of said view plane into subdivisions;

(f) determining which of the subdivisions of said view plane are enclosed by said projections of said subdivisions of said three-dimensional universe;
and (g) painting areas of a display screen corresponding to said subdivisions of said view plane determined by said determining step (f) to be enclosed by said projections.

7. A method for generating a two-dimensional image of a three-dimensional object, comprising:
(a) providing input data volumetrically defining said object within a three-dimensional universe;
(b) subdividing said three-dimensional universe into a hierarchy of a predetermined number of levels, each level comprising a plurality of discrete volumes of uniform predetermined size, each volume being characterized by the degree to which it is occupied by said object, each volume in each of said levels being a subdivision of a volume in the level above it in said hierarchy;
(c) selecting a point of view for viewing said object;
(d) establishing a two-dimensional view plane;
(e) visiting the volumes in said hierarchy in a sequence determined by said point of view until a volume occupied by said object to a predetermined degree which is not visually obstructed from said selected point of view by any other volume in said hierarchy occupied by said object to said predetermined degree is encountered;
(f) projecting said unobstructed volume onto said view plane at a location and orientation determined by said selected point of view and the location of said volume in said three-dimensional universe;
(g) subdividing said view plane into a plurality of discrete areas of uniform size;
(h) determining which of said areas of said view plane are enclosed by said projection and which of said areas intersect said projection but are not enclosed by said projection;
(i) painting said areas of said view plane determined to be enclosed by said projection;
(j) further subdividing said areas of said view plane determined to intersect but not to be enclosed by said projection and repeating said determining and said painting steps for said subdivided areas, until a predetermined degree of resolution is reached;
(k) repeating said visiting step to obtain the next volume in said sequence occupied by said object to said predetermined degree which is not visually obstructed from said selected point of view by any volume in said hierarchy occupied by said object to said predetermined degree and not projected onto said view plane earlier in said sequence, repeating said projecting and subdividing steps for said next volume, and performing said determining, painting and further subdividing steps on the projection of said next volume for previously unpainted ones of said areas of said view plane, until all of the volumes in said hierarchy occupied by said object to said predetermined degree have been visited; and (1) displaying the painted areas of said view plane.

8. A method as in claim 7 wherein said visiting step (e), projecting step (f), subdividing step (g), determining step (h), painting step (i), further subdividing step (j) and repeating step (k) are performed by processing electrical signals with hard-wired digital logic elements.

9. A method as in claim 7 wherein said subdividing step (b) subdivides each of said volumes occupied but not to a predetermined degree into 8 volumes of identical size, shape and orientation.

10. A method as in claim 9 wherein:
said three-dimensional universe is defined by a parallelepiped; and said subdividing step (b) subdivides said universe into parallelepiped-shaped volumes.

11. A method as in claim 7 wherein:
said three-dimensional universe is defined by a parallelepiped; and said subdividing step (b) subdivides said universe into parallelepipeds.

12. A method as in claim 11 wherein:
said determining step (h) includes the step of determining which of said areas are enclosed by the projection of one of three faces, said three faces corresponding to the three visible faces of said volume being projected when said volume is viewed from said selected point of view;
said painting step (i) paints each of said areas of said view plane determined to be enclosed by one of said faces of said projection one of three shades depending upon which face encloses said area;
and said further subdividing step (j) is performed on areas which intersect said projection but which are not enclosed by one of said faces of said projection.

13. A method as in claim 7 wherein:
said subdividing step (b) includes the step of creating a representation of said hierarchically-subdivided three-dimensional universe, said representation having a plurality of entries, each of said entries representing one of said volumes, each of said entries comprising at least one field storing said characterization of the volume which it represents; and said visiting step (e) includes the step of visiting said entries in said representation of said three-dimensional universe.

14. A method as in claim 13 wherein said creating step of said subdividing step (b) includes the step of arranging said representation in a tree structure.

15. A method as in claim 14 wherein said entry-visiting step of said visiting step (e) encounters said unobstructed volume by a depth-first traversal of said tree.

16. A method as in claim 15 wherein:
said establishing step (d) includes the step of clearing every entry in an hierarchical representation of said view plane, said representation of said view plane comprising a predetermined number of levels, each of said levels representing a plurality of discrete areas of a different uniform size in said subdivided view plane, each of said levels comprising a plurality of said entries, each of said entries representing one of said areas;
said painting step (i) includes the step of marking the entries in said representation representing said areas which are painted; and said repeating step (k) includes the step of determining if the entry representing an area in said hierarchical representation of said view plane has been marked in order to determine whether said area has been previously painted.

17. A method as in claim 14 wherein said subdividing step (b) subdivides each of said volumes occupied but not to a predetermined degree into 8 volumes of identical size, shape and orientation.

18. A method as in claim 14 wherein neither entries of subdivisions of volumes not occupied by said object nor entries of subdivisions of volumes occupied by said object to said predetermined degree are included in said tree structure.

19. A method as in claim 18 wherein said visiting step (e) includes the step of adding an offset stored in each of said entries in said tree structure to the storage address where said entry is stored in a storage device to obtain the storage addresses in said storage device of entries representing subdivisions of the volume which said entry represents.

20. A method as in claim 7 wherein:
said establishing step (d) includes the step of clearing every entry in an hierarchical representation of said view plane, said representing of said view plane comprising a predetermined number of levels, each of said levels representing a plurality of discrete areas of a different uniform size in said subdivided view plane, each of said levels comprising a plurality of said entries, each of said entries representing one of said areas;
said painting step (i) includes the step of marking the entries in said representation representing said areas which are painted; and said repeating step (k) includes the step of determining if the entry representing said area in said hierarchical representation of said view plane has been marked in order to determine whether an area has been previously painted.

21. A method as in claim 20 wherein said representation of said view plane is arranged in a tree structure.

22. A method as in claim 21 wherein:
said view plane is rectangular;
said subdividing step (g) subdivides said view plane into at least four rectangular areas of equal size and orientation; and said further subdividing step (j) subdivides each of said areas into four rectangles of equal size and orientation.

23. A method as in claim 21 wherein said previously-painted determining step of said repeating step (k) includes the step of accessing the entries in said representation of said view plane representing said areas by addressing an interleaved memory.

24. A method as in claim 7 wherein said painting step (i) includes the step of uniformly painting each of said areas one of a plurality of different shades.

25. A method as in claim 7 wherein said painting step (i) includes the step of painting each of said areas of said view plane a shade which is dependent upon the orientation, with respect to said view point, of the surface of said volume the projection of which encloses said area.

26. A method as in claim 7 wherein said displaying step (1) is performed by modifying the intensity of pixels on an electronic display, each of said pixels corresponding to said subdivided area of said view plane at said predetermined degree of resolution.

27. A method as in claim 7 wherein said painting step (i) includes the step of painting said areas of said view plane at said predetermined degree of resolution which are significantly enclosed by said projection.

28. A method as in claim 7 wherein:
said subdividing step (g) includes the step of selecting an overlay comprising a predetermined number of contiguous ones of said areas which together enclose said projection;
said determining step (h) is performed only on said areas comprising said overlay; and said further subdividing step (j) further subdivides only said areas comprising said overlay.

29. A method as in claim 28 wherein the size of each of said areas of said view plane in said subdividing step (g) is larger than the size of said projection.

30. A method as in claim 28 wherein four of said contiguous areas are selected by said subdividing step (g).

31. A method as in claim 30 wherein the size of each of said areas of said view plane in said subdividing step (g) is larger than the size of said projection.

32. A method as in claim 7 wherein the size of each of said areas of said view plane in said subdividing step (g) is larger than the size of said projection.

33. A method as in claim 7 wherein said determining step (h) includes the preliminary step of testing said areas for intersection with a bounding box comprising a polygon of predetermined shape and orientation which is just large enough to enclose said projection, in order to eliminate areas which do not intersect said projection.

34. A method as in claim 33 wherein said bounding box is rectangular.

35. A method as in claim 34 wherein:
said view plane is rectangular;
said subdividing step (g) subdivides said view plane into at least four rectangular areas of equal size and orientation; and said further subdividing step (j) subdivides each of said areas into four rectangles of equal size and orientation.

36. A method as in claim 35 wherein said bounding box has the same orientation as said areas.

37. A method as in claim 7 wherein said projecting step (f) includes the step of processing retained data defining the size and orientation of projections of larger-sized volumes in said three-dimensional universe by hard-wired digital logic elements to obtain the size and orientation of projections of smaller-sized volumes in said three-dimensional universe.

38. A method as in claim 7 further including the step of defining a region of said three-dimensional universe and wherein said visiting step (e) only visits volumes contained within said region.

39. A method as in claim 38 wherein said region of said region-defining step is defined by at least one surface having a location and orientation which is selected by a user.

40. A method as in claim 39 wherein said region of said region-defining step is defined by at least one pair of parallel planes.

41. A method for generating a two-dimensional image of a three-dimensional object comprising:
(a) providing input data volumetrically defining said object within a three-dimensional universe;
(b) subdividing said three-dimensional universe into a hierarchy of a predetermined number of levels, each level comprising a plurality of discrete volumes of uniform predetermined size, each volume being characterized by the degree to which it is occupied by said object, each volume in each of said levels being a subdivision of a volume in the level above it in said hierarchy;
(c) selecting a point of view for viewing said object;
(d) selecting a region of said three-dimensional universe to be displayed;
(e) establishing a two-dimensional view plane;
(f) visiting the volumes in said hierarchy which are contained within said region in a sequence determined by said point of view until a volume occupied by said object to a predetermined degree which is not visually obstructed from said selected point of view by any other volume in said hierarchy which is contained within said region and is occupied by said object to said predetermined degree is encountered;
(g) projecting said unobstructed volume onto said view plane at a location and orientation determined by said selected point of view and the location of said volume in said three-dimensional universe;
(h) subdividing said view plane into a plurality of discrete areas of uniform size;
(i) determining which of said areas of said view plane are enclosed by said projection and which of said areas intersect but are not enclosed by said projection:
(j) painting said areas of said view plane determined to be enclosed by said projection;

(k) further subdividing said areas of said view plane determined to intersect but not to be enclosed by said projection and repeating said determining and said painting steps for said subdivided areas, until a predetermined degree of resolution is reached;
(l) repeating said visiting step to obtain the next volume in said sequence contained within said region occupied by said object to said predetermined degree which is not visually obstructed from said selected point of view by any volume in said hierarchy which is contained within said region, occupied by said object to said predetermined degree and not projected onto said view plane earlier in said sequence, repeating said projecting and subdividing steps for said next volume, and performing said determining, painting and further subdividing steps on the projection of said next volume for previously unpainted ones of said areas of said view plane until all of the volumes in said hierarchy contained within said region and occupied by said object to said predetermined degree have been visited; and ( m) displaying the painted areas of said view plane.

42. A method as in claim 41 wherein said region selecting step (d) includes the step of defining at least one surface having a location and orientation which is selected by a user, said surface being used to at least partially define said region.

43. A method as in claim 42 wherein said surface defining step of aid region selecting step (d) includes the step of defining at least one pair of parallel planes.

44. A system for generating a two-dimensional image of a three-dimensional object, comprising:
data acquisition means for acquiring input data volumetrically defining an object to be displayed;

data conversion means for defining said object within a three-dimensional universe the volume of which has been subdivided into a plurality of subdivisions: and image processing means for:
(1) projecting said subdivisions of said three-dimensional universe which are contained by said object onto a view plane:
(2) progressively subdividing the area of said view plane into subdivisions;
(3) determining which of the subdivisions of said view plane are enclosed by said projections of said subdivisions of said three-dimensional universe:
and (4) painting areas of a display screen corresponding to said areas determined to be so enclosed by said projections.

45. A system as in claim 44 wherein said image processing means includes a plurality of hard-wired digital logic elements.

46. A system as in claim 44 wherein said image processing means comprises a hard-wired finite-state sequential digital logic circuit.

47. A system for generating a two-dimensional image of a three-dimensional object, comprising:
data acquisition means for acquiring input data volumetrically defining an object to be displayed;
data conversion means for defining said object within a three-dimensional universe the volume of which is subdivided into a plurality of subdivisions; and image processing means for:
(1) projecting said subdivisions of said three-dimensional universe which are contained by said object onto a view plane in a predetermined order wherein subdivisions not visually obstructed from a predetermined view point by other subdivisions containing said object are projected before said other volumes;
(2) progressively subdividing the area of a view plane into subdivisions;

(3) determining, for each of said projec-tions, which of the areas of said view plane are enclosed by said projection;
and (4) painting areas of a display screen corresponding to said areas of said view plane determined to be so enclosed and not already painted because of enclosure by the projection of a volume visited earlier in said sequence.

48. A system as in claim 47 wherein said image processing means comprises a plurality of hard-wired digital logic elements.

49. A system as in claim 47 wherein said image processing means comprises a hard-wired finite-state sequential digital logic circuit.

50. A system for generating a two-dimensional image of a three-dimensional object, comprising:
data acquisition means for acquiring input data volumetrically defining an object to be displayed;

data conversion means for defining said object within a three-dimensional universe the volume of which is subdivided into a plurality of subdivisions;
interactive means for permitting a user to define a subset of the volume of said three-dimensional universe to be displayed; and image processing means for:
(1) projecting said subdivisions of said three-dimensional universe which are contained by said object and which lie within said subset onto a view plane, (2) progressively subdividing the area of said view plane into subdivisions, (3) determining which of the subdivisions of said view plane are enclosed by said projections of said subdivisions of said three-dimensional universe;
and (4) painting areas of a display screen corresponding to said areas determined to be so enclosed by said projections.

51. A system for generating a two-dimensional image of a three-dimensional object, comprising:

data acquisition means for acquiring input data volumetrically defining an object to be displayed;
data conversion means for defining said object within a three-dimensional universe subdivided into a hierarchy of a predetermined number of levels, each of said levels comprising a plurality of discrete volumes of uniform predeter-mined size, each of said volumes being characterized by the degree to which it is occupied by said object, each volume in each of said levels being a subdivision of a volume in the level above it in said hierarchy;
interactive means for permitting a user to select a point of view for viewing said object;
image processing means for processing said image, including:
(1) view plane establishing means for establishing a two-dimensional view plane;
(2) visiting means for visiting the volumes of said three-dimensional universe in said hierarchy in a sequence determined by said point of view until a volume occupied by said object to a predetermined degree which is not visually obstructed from said selected point of view by any other volume in said hierarchy occupied said object to said predetermined degree is encountered, and for so visiting, one by one, each of the volumes in said sequence occupied by said object to said predetermined degree and not visually obstructed from said selected point of view by any volume in said hierarchy occupied by said object to said predetermined degree and not projected onto said view plane earlier in said sequence until all of the volumes in said hierarchy occupied by said object to said predetermined degree have been visited;
(3) projecting means for projecting each of said volumes so unobstructed, one by one, onto said view plane at a location and orientation determined by said selected point of view and the location of said volume in said three-dimensional universe;
(4) view plane subdividing means for subdividing said view plane, for each of said projections, into a plurality of discrete areas of uniform size, said view plane subdividing means including recursive means for further subdividing said areas of said view plane determined by said determining means to inter sect but not to be enclosed by said projection, until a predetermined degree of resolution is reached;
(5) determining means for determining, for each of said projections, which of said areas of said view plane are enclosed by said projection and which of said areas intersect but are not enclosed by said projection; and (6) painting means for painting said areas of said view plane determined to be both enclosed by said projection and not already painted because of enclosure by the projection of a volume visited earlier in said sequence; and display means for displaying the painted areas of said view plane.

52. A system as in claim 51 wherein said data acquisition means comprises a computer tomography scanner.

53. A system as in claim 51 wherein:
said data conversion means includes object storage means for storing a representation of said hierarchically-subdivided three-dimensional universe, said object storage means including a plurality of storage locations each of which represent one of said volumes, each of said storage locations having at least one field containing said characterization of the volume which said location represents; and said visiting means includes means for accessing the storage location in said object storage means representing said visited volumes.

54. A system as in claim 53 wherein said object storage means stores said representation in a tree structure.

55. A system as in claim 53 wherein:
said data conversion means subdivides each of said volumes in each of said levels into 8 volumes of identical size, shape and orientation;
and said object storage means stores said representation in an octree structure.

56. A system as in claim 55 wherein said object storage means stores the subdivisions only of volumes occupied by said object but not to said predetermined degree.

57. A system as in claim 55 wherein said object storage means stores said tree structure at least partially in linked list format.

58. A method as in claim 57 wherein:
said object storage means includes means for storing an offset in each of said storage locations which locates the address of the storage locations representing the subdivisions of the volume represented by the storage location in which the offset is stored relative to the address of said storage location; and said accessing means of said visiting means includes addressing means for addressing storage locations storing the subdivisions of a volume represented by a given storage location by adding said offset stored in said given storage location to the address of said given storage location.

59. A system as in claim 51 wherein said interactive means includes a trackball.

60. A system as in claim 51 wherein said image processing means includes a plurality of hard-wired digital logic elements.

61. A system as in claim 51 wherein said image processing means comprises a hard-wired finite-state sequential digitial logic circuit.

62. A system as in claim 51 wherein:
said image processing means further includes:
window storage means for storing a hierarchical representation of said view plane, said representation of said view plane comprising a predetermined number of levels, each of said levels representing a plurality of areas of a uniform size in said subdivided view plane, each of said levels comprising a plurality of storage locations, each of said storage locations representing one of said areas; and window storage access means for marking the storage locations of said window storage means representing said areas which are painted; and said determining means determines whether an area has been previously painted by testing whether the storage location of said window storage means representing said area has been marked.

63. A system as in claim 62 wherein said window storage means stores said representation of said view plane in a tree structure.

64. A system as in claim 62 wherein said window storage means comprises an interleaved memory.

65. A system as in claim 51 wherein:
said three-dimensional universe is parallelepiped in shape, each of said volumes subdividing said three-dimensional universe is parallelepiped in shape;

said determining means includes means for determining which of said areas are enclosed by one of three faces of said projection, each of said three faces corresponding to one of the visible faces of said volume being projected when said volume is viewed from selected point of view;
said painting means paints each of said areas of said view plane determined to be enclosed by one of said faces of said projection one of three shades depending upon which face encloses said area;
and said recursive means of said view plane subdividing means further subdivides only those areas which intersect said projection but which are not enclosed by one of said faces of said projection.

66. A system as in claim 51 wherein:
said view plane is rectangular; and said view plane subdividing means subdivides said view plane into a plurality of rectangles of equal size and orientation.

67. A system as in claim 51 wherein said painting means includes means for uniformly painting each of said areas one of a plurality of different shades.

68. A system as in claim 51 wherein said painting means includes means for painting each of said areas of said view plane a shade which is dependent upon the orientation, with respect to said view point, of the surface of said volume the projection of which encloses said area.

69. A system as in claim 51 wherein said recursive means of said view plane subdividing means paints said subdivided areas at said predetermined degree of resolution which are significantly enclosed by said projection.

70. A system as in claim 51 wherein:
said view plane subdividing means includes means for selecting an overlay comprising a predetermined number of contiguous ones of said areas which together enclose said projection; and said determining means performs said determination only on said areas comprising said overlay.

71. A system as in claim 70 wherein four of said contiguous areas are selected by said overlay-selecting means.

72. A system as in claim 71 wherein said view plane subdividing means subdivides said view plane into areas each of which is larger than the size of said projection.

73. A system as in claim 70 wherein said view plane subdividing means subdivides said view plane into areas each of which is larger than the size of said projection.

74. A system as in claim 51 wherein each of said plurality of discrete areas into which said view plane subdividing means subdivides said view plane is larger than the size of said projection.

75. A system as in claim 51 wherein said determining means includes means for testing said areas for intersection with a bounding box comprising a polygon of predetermined shape and orientation which is just large enough to enclose said projection, in order to eliminate areas which do not intersect said projection.

76. A system as in claim 75 wherein said bounding box is rectangular.

77. A system as in claim 76 wherein:
said view plane is rectangular;
said view plane subdividing means subdivides said view plane into a plurality of rectangles of equal size and orientation; and said recursive means further subdivides each of said areas into four rectangles of equal size and orientation.

78. A system as in claim 77 wherein said bounding box has the same orientation as said areas of said view plane.

79. A system as in claim 78 wherein:
said view plane subdividing means includes means for selecting an overlay comprising a predetermined number of contiguous ones of said areas which together enclose said projection; and said determining means performs said test and said determination only on said areas comprising said overlay.

80. A system as in claim 79 wherein four of said contiguous areas are selected by said overlay-selecting means.

81. A system as in claim 80 wherein said view plane subdividing means subdivides said view plane into areas each of which is larger than the size of said projection.

82. A method as in claim 51 wherein said projecting means includes:
means or retaining data defining the size and orientation of said projection of larger-sized volumes in said three-dimensional universe; and means for processing said retained data to obtain the size and orientation of the projection of smaller sized volumes in said three-dimensional universe.

83. A system as in claim 82 wherein said means for processing said retained data comprises:
shift registers;
arithmetic address; and digital logic gates.

84. A system as in claim 82 wherein said means for retaining data comprises a stack.

85. A system as in claim 51 further including means for defining a region of said three-dimensional universe and wherein said visiting means only visits volumes contained within said region.

86. A system as in claim 85 wherein said region-defining means includes means for defining at least one surface having a location and orientation which is selected by a user.

87. A system as in claim 85 wherein said said region-defining means includes means for defining at least one pair of parallel planes.

88. A system is in claim 51 wherein said display means include :
an electronic display; and means for modifying the intensity of pixels on said electronic display, each of said pixels corresponding to said subdivided area of said view plane at said predetermined degree of resolution.

89. A system as in claim 88 wherein said intensity-modifying means includes frame buffer means for storing said modified intensity of each of said pixels.

90. A system as in claim 47 wherein said data acquisition means includes user interactive means for analytically defining said object to be displayed.

91. A system for generating on a display screen a two-dimensional image of a three-dimensional object volumetrically defined within a three-dimensional universe the volume of which has been subdivided into a plurality of subdivisions, said system comprising image processing means for:
(1) projecting said subdivisions of said three-dimensional universe which are contained by said object onto a view plane;
(2) progressively subdividing the area of said view plane into subdivisions;
(3) determining which of the subdivisions of said view plane are enclosed by said projections of said subdivisions of said three-dimensional universe;
and (4) painting areas of said display screen corresponding to said areas determined to be so enclosed by said projections.

92. A system as in claim 91 wherein said image processing means comprises a plurality of hard-wired digital logic elements. 93. A system as in claim 91 wherein said

93. A system as in claim 91 wherein said image processing means comprises a hard-wired finite-state sequential digital logic circuit.

94. A system for generating on a display screen a two-dimensional image of a three-dimensional object volumetrically defined within a three-dimensional universe the volume of which is subdivided into a plurality of subdivisions, said system comprising image processing means for:
(1) projecting said subdivisions of said three-dimensional universe which are contained by said object onto a view plane in a predetermined order wherein subdivisions not visually obstructed from a predetermined view point by other subdivisions containing said object are projected before said other volumes;
(2) progressively subdividing the area of a view plane into subdivisions;
(3) determining, for each of said projec-tions, which of the areas of said view plane are enclosed by said projection;
and (4) painting areas of said display screen corresponding to said areas of said view plane determined to be so enclosed and not already painted because of enclosure by the projection of a volume visited earlier in said sequence.

95. A system as in claim 94 wherein said image processing means comprises a plurality of hard-wired digital logic elements.

96. A system as in claim 94 wherein said image processing means comprises a hard-wired finite-state sequential digital logic circuit.

97. A system for generating on a display screen a two-dimensional image of a three-dimensional object volumetrically defined within a three-dimensional universe the volume of which is subdivided into a plurality of subdivisions, said system comprising:
interactive means for permitting a user to define a subset of the volume of said three-dimensional universe to be displayed; and image processing means for:
(1) projecting said subdivisions of said three-dimensional universe which are contained by said object and which lie within said subset onto a view plane, (2) progressively subdividing the area of said view plane into subdivisions, (3) determining which of the subdivisions of said view plane are enclosed by said projections of said subdivisions of said three-dimensional universe;
and (4) painting areas of said display screen corresponding to said areas determined to be so enclosed by said projections.

98. A system for generating on a display screen a two-dimensional image of a three-dimensional object volumetrically defined within a three-dimensional universe subdivided into a hierarchy of a predetermined number of levels, each of said levels comprising a plurality of discrete volumes of uniform predetermined size, each of said volumes being characterized by the degree to which it is occupied by said object, each volume in each of said levels being a subdivision of a volume in the level above it in said hierarchy, said system including:
interactive means for permitting a user to select a point of view for viewing said object; and image processing means for processing said image, including:
(1) view plane establishing means for establishing a two-dimensional view plane;
(2) visiting means for visiting the volumes of said three-dimensional universe in said hierarchy in a sequence determined by said point of view until a volume occupied by said object to a predetermined degree which is not visually obstructed from said selected point of view by any other volume in said hierarchy occupied said object to said predetermined degree is encountered, and for so visiting, one by one, each of the volumes in said sequence occupied by said object to said predetermined degree and not visually obstructed from said selected point of view by any volume in said hierarchy occupied by said object to said predetermined degree and not projected onto said view plane earlier in said sequence until all of the volumes in said hierarchy occupied by said object to said predetermined degree have been visited;
(3) projecting means for projecting each of said volumes so unobstructed, one by one, onto said view plane at a location and orientation determined by said selected point of view and the location of said volume in said three-dimensional universe;
(4) view plane subdividing means for subdividing said view plane, for each of said projections, into a plurality of discrete areas of uniform size, said view plane subdividing means including recursive means for further subdividing said areas of said view plane determined by said determining means to intersect but not to be enclosed by said projection, until a predetermined degree of resolution is reached;
(5) determining means for determining, for each of said projections, which of said areas of said view plane are enclosed by said projection and which of said areas intersect but are not enclosed by said projection; and (6) painting means for painting said areas of said view plane determined to be both enclosed by said projection and not already painted because of enclosure by the projection of a volume visited earlier in said sequence; and output means for outputting indicia of said painted areas of said view plane to said display screen.