CA1200933A - Multiple access system and method - Google Patents

Multiple access system and method

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Publication number
CA1200933A
CA1200933A CA000430342A CA430342A CA1200933A CA 1200933 A CA1200933 A CA 1200933A CA 000430342 A CA000430342 A CA 000430342A CA 430342 A CA430342 A CA 430342A CA 1200933 A CA1200933 A CA 1200933A
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CA
Canada
Prior art keywords
packet
parameter data
data
receiving
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000430342A
Other languages
French (fr)
Inventor
Kazutomo Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57101913A external-priority patent/JPS58219838A/en
Priority claimed from JP58029741A external-priority patent/JPS59154844A/en
Priority claimed from JP58040057A external-priority patent/JPS59167150A/en
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of CA1200933A publication Critical patent/CA1200933A/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/14Relay systems
    • H04B7/15Active relay systems
    • H04B7/204Multiple access
    • H04B7/212Time-division multiple access [TDMA]
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/14Relay systems
    • H04B7/15Active relay systems
    • H04B7/185Space-based or airborne stations; Stations for satellite systems
    • H04B7/1853Satellite systems for providing telephony service to a mobile station, i.e. mobile satellite service
    • H04B7/18539Arrangements for managing radio, resources, i.e. for establishing or releasing a connection
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/12Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18Automatic repetition systems, e.g. Van Duuren systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W74/00Wireless channel access, e.g. scheduled or random access
    • H04W74/08Non-scheduled or contention based access, e.g. random access, ALOHA, CSMA [Carrier Sense Multiple Access]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S370/00Multiplex communications
    • Y10S370/912Packet communications
    • Y10S370/913Wireless or radio

Abstract

Abstract of the Disclosure In a multiple access system for performing packet communication involving sharing of a single communication medium by a plurality of users, the single communication medium is divided into a plurality of channels. Each user monitors the condition of each channel, and probability of packet transmission to each channel is controlled in accordance with a monitored result.

Description

The preserlt inverltiorl relates to mul~iple access system and method of packet communication involving the sharing of a single communication medium such as a single satellite by a plurality of users.
Both the prior art and the present invention will be described in conjunction with the accompanying drawings in which:
Fig. 1 shows the principle of satellite communication;
Fig. 2 shows a slotted ALOHA scheme;
Fig. 3 shows a frame consisting of L time slots and useful in explaining the principle of this invention;
Fig. 4 shows a transmission model for j-th user in accordance with this invention;
Fig. 5 is a block diagram showing the basic arrangement of a multiple access system incorporating the present invention;
Fig. 6 is a block diagram of a modem section ~54) of the system shown in Fig. 5;
Fig. 7 is a block diagram showing a first embodiment of a network control section (53) of the system shown in Fi~. 5;
Fig. 8 is a block diagram of one embodiment of a control circuit shown in Fig. 7;
Fi~. 9 is a block diagram of an arithmetic operatlon circuit 81 shown in Fig. 8;
Yig. 10 is a block dia~ram of anothe-- embodiment of the control circuit shown in Fig. 7;

~,~
' ~1, ' ~
h / j ~ ~

3~
Fig. ll is a ~lock diac3ram of an arithMetic operation circuit (100~) shown in Fig. 10;
Fig. 12 is a block diagram showing a secon~
embodiment oE the network control section of the system show~ in Fig. 5; and Fig. 13 is a block diagram of a control circuit in Fig. 12.

Description of the Prior Art TDMA (-time division multiple access) and ALOHA
are well-known as multiple access systems using a shared communicatio~ medium such as a satel]ite shown in Fig. l~
The TDIIA scheme divides a channel into time slots at intervals comprising one-packet transmission time. When the number of users is N (positive integer), N slo-ts are given as one frame. Each slot of the frame is permanently assigned to each user. The TDMA scheme is very effective when the number of users is small and a heavy traffic load occurs. However, when the number of users is lar~e and only a light traffic load occurs, the utilization efficiency of the channel is degraded, and an avera~e delay time is increased, resulting in inconvenience. Furthermore, the TDMA scheme is not suitable when changes in the traffic load are great. The ALOHA system includes a basic ALOHA
scheme and a slotted ALOHA scheme. The l; ~1 / ( .~ `,.' slotted ALOHA scheme is an improvement upon the basic one and will be described hereinafter. In the slotted ALOHA
scheme as shown in FigO 2, a channel is divided into time slots in the same manner as in the TDMA schemeO If a user S wants to transmit a packet, he immediately transmits a packet in synchronism with the given time slotO If packets from the plurality of users collide with each other, retransmissions are performed at randomO The slotted ALOHA scheme is very effectively utilized when the number of users is great and a traff ic load is light (i.e. J a low load is imposed~ Howev~r~ a maximum throughput of this scheme is as low as ~.36~ with respect to a channel capacity defined as 1. When a number of packets ~hich exceeds the maximum throughput is transmitted, collisions Erequently occur~ resultlng in a deadlocked condition.
When the number o~ ~sers is great and the traffic load varies in a wide rangeJ the conventional schemes (i~e., the TDMA and slotted ALOHA schemes~ cannot be applied. In order to compensate for the drawbacks cf the conventional schemesr an optimal adaptive scheme for multiple access broadcast communication is proposed to automatically select one of the ALOHA and TDMA modes as needed, as described by Lo Kleinrock and YO Yemini, "An Optimal Adaptive Scheme for Multiple Access Broadcast Communicatlon", ICC Conf, Proc., Chicagol ILo ~ June 1977.
The ALOHA mode is adopted in the case of a light traffic \

--X--~0~)~33 load, while ~he TDMA mode is adopted in the case of a heavy traEfic load. In order to perform the above operation, however, a total number of users requesting packet transmission mus~ be signalled to each userO
Therefore, information indicating the total number of users requesting packet transmission must be transmitted to each user through a subchannel~ resulting in incon~enience. According to a scheme described by Glenn Ricard and Ashok Ko Agrawala, "Dynamic Management of Packet Radio Slots", presented at the Third Berkely Workshop on Distributed Data Management and Computer Networks, Aug. 1978, each user first uses the ALOHA mode while monitoring the ch~nnel. When the traffic load on - the channel becomes heavy, the mode is switched to the TDMA mode. Furthermore, when an empty slot occurs in the TMA mode~ this time slot is set in the ALOHA mode again~
A subchannel is not required in the above-mentioned scheme~ ~owever, where a few users ~requently transmit packets to render the channel busy, even i~f the ALOHA mode is switched to the TDMA mode t the remaining users~ cannot transmit packets. In order to eliminate this inconvenience, predetermined time slots must be allotted to those users who most frequently transmit packetsO In other wordsr in this schemel an additional allocation operation is requred. Therefore, this conventlonal scheme is difficult to update in accordance with a change in the number of users. In fact~ practical implementations for i/

3~3 this scheme have not yet been proposed.
Summary of the Invention It is a major object of the present invention to provide multiple access system and method which allow effecti~e utilization of a channel under distributed control even if a traffi.c load of each user varies in a wide range.
Another object of the present invention is to provide a multiple access system capable of pexform.ing an ALOHA mode during a light traffic and assigning ~ime slo~s to each user in accordance wi~h a TDMA mode during a heavy t.raffi~.
- Still another object of the present invention i5 to provide a multiple access system capable of preventing shutout of the userO
Still another object of the present invention is to provide a multiple access system capable of properly assigning time slots to each user even in the casP of an irregular, hi~h traffic~
According to one aspect of the inDention, there is pro~ided a method for performing. packet communication .in a multiple access system comprisingo sharing a single communication medium by a plurality o~ user stations through a plurality of channels;
~5 monitoring by each user station a state of each channel; and controlling probability of packet transmission in accordance with a monitored result.
According to another aspect of the invention~
there is provided a multiple access system for performing packet communication involving sharing of a single S communication medium by plurality of users through a plurality of channels such that each user monitors a state of each channel and pro~abili~y of packet transmission is controlled in accordance with a monitored result, comprising:
an interface section for linking data together~as a packet, a modem section for modulating/demodulating a packet, said modem section including a carrier detector for detecting whether or not the channe-l is being used and for generating one of emp~y and busy 5i gnals;
a network control section for performing access control, said network control sectio~ including a collision detector for detecting a transmitting packet and a delayed receiving pacekt so as to detect a collision of the transmitting packet with another transmitting packet r said collision detector generating a success signal when the transmitting packet and the delayed receiving pacekt coincide with each other and a ~5 collision signal when the transmitting packet and the delayed receiving packet do not coincide~
a retra~nsmitter ~or retransmitting a packet identical with the transmittin~3 packet when the transmitting packet collides with said delayed receiving packet, and a control circuit for receivin~3 a slot sync pulse, one of the busy and empty signals, one of the success and collision signals, and a packet arrival pulse, and for generating a control signal to control pac'~et transmission;
and an RF section for converting an IF signal to a high frequency transmission signal and vice versa.

Detailed Description of the Preferred Embodiment Preferred embodiments of the present invention will be described with reference to the accompanying drawing.
The principle of a multip]e access system accordin~ to the present invention will first be described.
As shown in Fig. 3, in slotted ALOHA, time is divided into slots of duration equal to a single packet transmission time~ Consecutive L slots form a frame as in TDMA. A retransmission algorithm iden-tical to that of slotted ALOH~ is employed. On the above framework a new parameter set~ Pij's, is introduced.
As is shown in Fig. ~, when j-th user has Pij's (i=l - L), a conditional probability is assigned to its i-th slot, with which it transmits a packet when it has any. The role of the parameter set is well illustrated by kh/~

~2~

the following two extreme cases.
If all Pij's are fixed to unity, the notion of the frame disappears and slotted ALOHA is obtained.
Throughout the specification this situation is called the S ALOHA mode.
If the siæe of the frame is set equal to the number of the use_s i~ and Pij's are selected as P~ for i=j =o otherwise thenr the system works as TDM~. We refer to this patte~n of Pij's as the TDMA mode O
It can be easily imagined now that if it is possible to adjust the parameters depending on the channel traffic~ efficient access schemes will emerge. In fact, as will be shown later many adaptive strategies proposed previously can be regarded as to have the parameter set implicitly and they are characterized by the way in which the virtual parameter are adjustedO
According to this invention, a scheme is proposed in which the parameters are adaptively adjusted so as to maximiæe the channel throughput. The slotted ALOHA
throughput is given by the well-known formula where Gj is t~e probab ity that j-th user wants to ~5 transmit a packet in some slot (see Nc Abramson, "The throughput of packet broadcasting channels", IEEE Trans.
Commun., vol. C~M-25, pp. 117-128, Jan. 1977)~ Applying (1) to each slot of all users/ the system throughput taking Pij's into accou,nt is obtained as l 2 >~ p~ r (~ - p~ C~ K ) ~O,OO (2~
To maximize t~is cost f unction a simple gradient search algorithm is employedO The conditional probability P Q n associated with the ~-th slot of ~he n-th user, is updated at m-th time frame by 7~ti _ p~ t ~ ~p 0...O (3) where ~ is a positive,adaptation constant~ By taking a partial derivative of (2) with respect to P~ the gradient i given ~s ~ ~

~P~n ~ J) 2 pRJ~
~ quation (4) implies that the gradient can be expressed in terms of the prohability of two vents, Let A ~n be the event "the ~-th slot is open for the n-th user" and let B be the event i'only one user othe~ than the n-th transmits a packet ~t the Q-th slot"~ Then, the first term in the brace of (4) i9 Prob ~A ~n~ and the second is Prob rB ~n~. It is to be noted here that those two events are not common to all users but they are defined on each user~ Also noteworthy is that the frame need not be synchronized among users, in other words, the Q-th slot of the n-th user need not be the Q-th slot of the m-th user.
~s ~ssuming that the collision between other users' packets can be detected, each user can observe or monitor whether the events defined to its own occur or not. The pro~ability of these everlts and consequently the gradient can be estimated from repea~ed observations or more practically by the stochastic gradient method. A natural deEini~ion of the stochastic gradient ~ is as follows:
AR.~ n ~ c~ ~ C~t ~ O = .
-- O
where C ~n denotes the event "more than two users, except for the n~th, transmit at the Q-th slot" 7 i~eO r A ~n ~ B Qn.
However, an obvious drawback will arise if the above deinition is applied to the adaptation. Since,-if all Pij's and Gi's happen to be unity~ the values of Pijls will never be changed any more and system deadlock -results. This is because the original cost function is not well conditioned over the parameter space to justify the gradient algori~hm and ~he above situation can be regarded as a trap. In the trap state the event C ~n; 5 or the collisions are always observed. Therefore, an intuitive remedy to avoid getting into this is to evaluate the stochastic gradient negative so that Pij's are decreased when the event C ~ is encountered~ T~e reason for decreasing the Pijls is not only because there is no way to increase, but because it is justified by the follcwing considerationO The outcome of the event C Rn decreases both Rrob CA ~ n~ and Prob CB ~ n] But as Gi's tend to increase due to the collisionsl decrease in the former is greater than that in the latter. Thus, if the system model includes feedback effects~ a natural directlon to move Pij's upon collisions i.s negative~

Then, an extremely simple algorithm P Q~ YZ .... O (6) with ~ Qn positive for ~ ~, negative for ~ ~n is reached. This means that as shown in the following Table, each user increases its parameters if no one else is there and decreases them if someone else is there in the slotO
Since Pij's are the probabilities, additional operations limiting them between 0 and 1 are needed besides (6)o Table The adaptation algo~ithm \ OTHERS
\ IDLE TRANS
SELF

IDLE (EMPTY ) (NON--EMPTY ) INCR~A.~ DECREASE

TRANS (SUCCESS) (COLI)ISION) I N CREASE DECREASE

For some simple traffi~ models~ the behavior of the algorithm can be predicted without resorting to a computer simulationO When every user has low traffic rate, channel empty is more frequently encounterd than the other events. Thus, all the Pij'S keep on increasing :~Z~ 333 until they reach unity malcing the system converge to the ALOHA mode.
If the traffic of all users increases, collisions begin to dominate and all Pij's decrease toward zero, but S due to statistical fluctuations a particular user's i-th ~lot probability, say Pin~ remain~ greater than that of the other usersO Since it is quite natural in this Situation to assume that each user has a number of packe~s to transmit in the bufer, a user with larger conditional probability will have greater probability of success.
Therefore, once the above situation is reachedf the nrth user will increase its Pin forcing the otherstPik's (~r) t~
zeroO In like manner, other slots will be occupied by other usees. If the traffic rate is equally high among users, each user will have one slot to its own and the TDMA mode resultsO
As the adaptation algorithm given in the previous Table has a high degree o freedom, a situation that some users occupy the whole channel and some are shut ou~ of the system may occurn This seems somewhat awkward from a practical point o view~ Th2refore, maximizing the throughput under the constraints `2 P~ J j~ o. (7) is preferred in practical applications~ This is done by introducing Lagrange multipliers ~ n~s. The adaptation algorithm t6) is modified as n ~ ~ ( f ~ ) O . . . O t 8 ) where ~ is an adaptation constant, and ~ n is the minimum number of slots which j-th user requires.
The constraints~ however, should not always be rigid~ Because, if the algorithm tries to keep sa~isfying the constraints even when there exists heavy traffic beyond the channel capacity, throughput decreases and the channel capacity cannot be attained. Avoiding this is done by limiting ~ n's not to exceed unityO
Re~erring now to Fig. 5~ an overall construction of a multiple access system on time multiplexed basis incorporating the present lnvention will be describedO An input/output terminal 51 is connected to a data terminal device~ An interface section 52 processes data transmitted from the data terminal device to the terminal 51 so as to link data together as a packetO The packet is then supplied to a network control section 530 The interface sec~-or 52 also decomposes the pocket from ~he network control section 53 and sends it to the data terminal device through the terminal 510 The network control section 53 mainly performs access control. A modem section 54 performs modulation and demodulationO An RF section 55 increases a frequency o an IF signal to a transmission frequencyO The signal having the transmission frequency propagates through a transmitting antenna. The RF section 55 also decreases the frequency of a signal received at a receving antenna to produce an IF signalO The IF signal is then supplied i3~

to the modem 5~. The basic configuration of the apparatus is the same as that of the slotted ALOHA scheme~ but the internal arrangements o~ the ne~work control section 53 and the modem 5~ greatly differ from those of the slotted S ALOHA scheme~
FigO ~ is a block diagram of the modem section 54 shown in Fig. 5. An input t~rminal 61 and output terminals 62, 63 and 64 of the modem section 54 are connected to the network control section 53. Input and output terminals 66 and 65 of the modem section 54 are connected to the RF section 550 A modulator 67 receives and modulates the packet transmitted through the input terminal 61 and produces the modulated data ~om the output terminal 650 A demod~u~ator 68 receives and demodulates the modulated signal from the input terminal 66 and produces a demodulated signal to the output terminal 64~
A carrier detector 69 detects whether or not the channel is busy. More particularly, the carrier detector 69 detects ~ level of the modulated signal to be.supplied to the demodulator S8. If the signal level exceeds a prPdetermined threshold, the carrier detector 69 determines that the channel is busy and then generates a busy signal. Otherwise, the carrier detector 69 2S determines that the channel is empty and then generates an empty signal. The busy or empty signal is supplied to the network control section 53 through the output terminal 3~

62. A slot sync signal. detector 600 extracts a slot sync signal which continuously propagates along ~he channel and supplies a sync pulse to the network control section 53 through the terminal 63O
The modulator 67 9 the demodulator 68 and the 510t sync signal detector 600 are arranged in an ayparatus for performing the slotted ALOHA scheme, The modem section 54 also has the carrier detector 69, as described abovea Fiy. 7 is a block diagram of a first embodiment of the network control section 53~
Input an~ output terminals 71 and 72 of the network control section 53 are conn~cted to the interface section 520 ~n output terminal 73 and input terminals 74 to 76 of the network con~rol section 53 are connected to the modem section 54. The packet supplied to the input terminal 71 is temporarily stored in a buffer 77. When a gate circuit 78 is turned on~ the packet is supplied to the modem section 54 through the output terminal 73O The gate circuit 78 is turned ON/OFF in accordance with a gate control signal from a control circuit 79.
The packet is also supplied f.rom the gate circuit 78 to a clelay circuit 700. The delay circuit 700 delays the packet from the gate circuit 78 by a propagation delay time. The delay signal is then supplied to a collision detector 701. The collision detector 701 serves to detect whether or not the received packet collides with a packet from any other user stationO It is here noted that each l'Z{~ 33 channel is assumed ~o be a broadcast channel, so that a packet transmitted from a given user station can be received by ~he same~ The collision detector 701 compare~
the packet received at the terminal 76 with the packet from the delay circuit 700. If the collision detector 701 detects a coincidence between these packe~s, it generates a success signal. Otherwise, the collision detector 701 geneates a collision signalO A retransmitter 702 generates a collision signal~ A retransmi~ter 702 temporarily receives the packet from the delay circuit , 700~ r~hen the collision sign~l from the collision detector is supplied to the retransmitter 702, the retransmitter 702 delays the packet from the delay circuit , 700 in accordance with a given distribution, The delayed packet is returned to the buf~er 77~ However, when the success signai is supplied to the retransmitter 702, the retransmitter 702 remov~s the packet~ ~ln address filter 703 only extracts a packet (among the packets supplied to the terminal 76) whicb is addressed thereto. The selected packet is then supplied from the address filter 703 to the inker~ace section 52~ The control circuit 79 receives the busy or empty signal from ~he terminal 74, the slot sync pulse rom the terminal 75, an arrival pulse from the buffer 77, and the success or collision signal ~rom the collision detector 701. The control circuit 79 then controls the gate circuit 78 in accordance with the above-mentioned input signalsO Thus, it will be ~(3(~33~

appreciated that terminals 61~ 62, 63 and 64 of the modem section 54 are connected to termials 73, 74, 7S and 76 of the network control section 53 ~ respectively. The control circuit 79 will he described in detail hereinafterO
Fig. 8 is a block diagram of one embodiment of the control circuit 79O The control circuit 79 receives the slo~ sync pulse, the busy or empty signal0 the success or collision signal~ and ~he packet arrival pulse at input terminals 704, 705~ 706 and 707, respectively~ and generates a control signal rom its output terminal 708 so as to control the ON/OFE' operation o~ the gate circuit 78~ A counter 709 counts slot sync pulses in units of L
~one frame3. Present count d~ta I (corresponding to a given slot number ~) of the counter 709 is decreased by the number o~ slots corresponding to the transmission delay time in units of L ~o as to obtain data I' (corresponding to a slot number ~)~ The counter 709 supplies only the data I' to an arithmetic and logic circuit 81 through a selector 8000 This is because two slot numbers are required when a packet is transmitted during a given slot and is received during a different lot under the conditions of a lengthy transmission delay.
The selector 800 reads out a parameter P~
corresponding to the slot number ,~ and a parameter P~/
corresponding to the slot number 11i. The parameter P~ is supplied to a pattern generator 83, and the parameter PR' is supplied to ~he arithmetic and logic unit 8lo The .

3~

arithmetic operation unit 81 updates the parameter P
which is then stored in a memory ~2q The pattern generaotr 83 uses as the probability data the parameter ~rom the selector 800 and supplies the control signal to the gate circuit 78 through a terminal 708O the gate circuit 78 is then turned on. Thus~ it will ~e appreciatecl that terminals 74 and 75 in Figq 7 correspond to terminals 705 and 704 in Fig~ 8, respectively/ and that terminals 706, 707 and 708 in Fig~ 8 are connected to collision detector 701, buffer 77 and gate circuit 78 i~
Fiy. 7, respectively~
FigO 9 is a block diagram of the arithmetic operation unit 81. The arithmeticroperation unit 81 receives the busy or empty signal, the success or lS collision signal~ the packet arrival pulseJ and the slo~
number ( Q~ 3 data at input terminals 84g 85 3 86 and 87 thereof~ res~ectively. The arithmetic operation unit 81 then generates/receives the parameter P2 through the terminal 88. Thus, it will be appreciated that terminals 841 85 and 8~ in FigO 9 correspond to terminals 705~ 706 and 707, respectively, and that terminals 87 and 88 in Fig. 9 are respectively connected to counter 709 and selector 800 in FigO 8~ A functon generator 89 yenerates Eunction data ~ in response to the signals supplied to the 2s terminals 84 and 85 as follows:
=~ 1 (in the presence of an empty/success signal) l-l (in~the absence of an empty/success signal) 3~'~3~3933 ( 1 0 ) The function data is then supplied to an arithmetic operation circuit 90O The arithm~tic operation circuit gO
performs the following operation in acordance with the unction data ~ from the function generator 89 and the Lagrangean constant updated by an arithmetic operation circuit 91 through an arithmetic operation circuit 93 (i) W ~ P
and subsequent (ii) P ~- Wl for 0 ~Wl< 1 P ~ C ~or WlC ~ (12) P ~- 1 for Wl ~ l where ~ is a small positive number~ The parameter P
obtained from expression (283 is supplied as the updated parameter P~' from the terminal 88 to the memory 82 and is s~ored therein. At the same time, the following operation is per~ormed:
Q 4- Q ~ P ............................ (13j where Q is 2 P~ and the obtained Q is retained~
An averaging circuit ~2 averages the number of input pulses from the terminal 86 so as to obtain an arrival freq~ency ~. The arrival frequency is multiplied by L whiçh is the number of channels. Product or resultant data ~L corresponds to the number of slots required by the user. As the slot number changes from L
to 1 with the slo~ number data supplied from the counter 709 throu~h terminal 87, the arithmetic operation circuit - 19 - .

~ ~3~3 ~ ~

91 receives the constant ~and the data Q from the arithmetic operation circuit 90 at the terminal 87 thereof and performs the following operation;

(i) W2 ~~ )~~ ~ (Q ~ ~L) O.. ..~. (14) S Q ~- O
and subsequent O for W~ ~ 0 ~ ~~ W2 for W2~ o .O.......... O (15) here ~ is a small positive numberO The computed Q and are returned to the arithmetic operation circuit 90.
The ari.thmetic operation circuit 93 computes data obtained from the arithmetic operation circuit 91 as follows:
~ min~J~, ~O ~ $or ~ O ~1 00...(16) The computed result is supplied to the arithmetic operation circuit 90. The data q obtained from the arithmetic operation circuit 91 is also supplie~ per se to -the arithmetic operation circuit 90O
It should be understood that in the arithmetic operation circuit 81 as materialized in thé form~of the Fig. 9 arrangement~ constraints of expression5(14) and (16) are held so that in addition to the basic operation of the multiple access system wherein an ALOHA mode is performed during a light traffic and time slots are assigned to each user in accordance with a TDMA mode dur.ing a heavy traffic~ it is possible to properly assign time slots to ea~ch user even in the case of an irregular, -- 20 - .

high traEfic, if the averaginy circuit 92 is eliminaked, ~L = 1 stands in expression (14~ so that .in addition to the basic operation, it is possible to prevent shutout phenomenon although the proper assignment of the time slots is not assured; and if the arithmetic operation circuits 31 and 93 and the averaging circuit 92 are eliminated~ ~= 0 stands in expression (11) so that only the basic operation is assured, being subject to the shutout phenomenonD
The arrival frequency ~ of the transmitted packet is used in the above embodiment~ However, an arrival ,~
~requency ~' which includes the retransmitted packets may alternatively be used. FurthermoreD if the minimum required number of slots is defined as Lo~ and ~ L <
Lo~ Lo may be given instead of ~L~ In this case~ even if the traffic load is very light, a given user sta~ion can request Lo slots. Instead of~ L, the number of packets stored in the buffer 77 may be used to determine the degre~ of communication necessityO Alternatively, the degree o communication neces~ity may be determined in accordance with a priority order of received packètsO
Figs~ 10 is a block diagram of another embodiment of the control circuit 79 shown in FigO 7O In this embodiment, the slot sync pulse, the busy or empty signal~
the success or collision siqnal and the packet arrival pulse are also received at input terminals 704, 705 and 706, respectively, as in FigO 8. The control circuit then generats a gate control signa1 to control the ON/OFE' operation of the gate circuit 78 through ~he output terminal 708. A counter 709 counts slot sync pulses in units of L ~one frame)~ Present count data (corresponding to a given slot number ~) of the counter 709 is decreased by the number of slots corresponding to the transmission delay time in units of L so as to obtain (modified count) data Q O The counter 709 s~pplies only the data 1 to an arithmetic operation unit 1000 through a selector 800. This i5 because two slot numbers are requried when a packet is transmitted during a given slot and is received during a different slot under the conditions of a great transmission delay.
The selector 800 selects parameter data PQ
corresponding to the slot number ~ and probabiLity data D ~/ ~to be also referred to as a parameter) corresponding to the slot number Q from a memory 82 which stores L
parameters. The parameter PQ i9 supplied to a multiplier 1001, and the parameter PQ/ is supplied to an arithmetic opera-tion uni~ lOOOo The arithmetic operation unit lr~oo updates the parameter P~J 9 and updated data is returned to the selec~or 800. The selector 800 serves to store the updated data in the memory 82.
It should be noted that the arithmetic operation ~5 circuit 1000 updates the parameter P~ in accordance with T~l T ~ ~
an algorithm (e~g., P Q~, = P~ Qn f Qn -1, where T is the unit time corresponding to L slots, and ~ is a small positive number called a cor~ection coefEicient).
A selector 1002 reads out the parameter p from a memory 1003 and supplies this data to the mult.iplier 1001 S and to an arithmetlc and logic unit 10040 The parameter updated by the arithmetic and logic unit 1004 is stored in the memory 1003O
The multiplier 1001 multiplies the parameter P
Erom the selector 800 with the parameter p from the selector 1002. Produc~ data i5 then supplied to a pattern generator 83. In the pattern genera~or 83~ the product data supplied from the multiplier 1001 is detected as a probability and generates a gate control signal which is supplied to the gate circuit 78 through the output terminal 707 in accordance with the obtained probability.
Fig. 11 is a block diagram of the arithmetic operation unit 1004 shown in ~i9D 10~ The arithmetic operation unit 1004 receives the success or collision signal from its input terminal 1005 (corresponding to terminal 706 in FigO 10) and generates or recelves a parameter p from its terminal 1006O A f unction generator 1007 generates a function value ~ as follows:
= -1 (in the presence o~ a collision signal) = ~ ~ >o (in the absence of collision signal) O.O.O ~16) The function value ~ is supplied to an arithmetic operation circuit 1008. The arithmetic operation circuit ~ZS~()933 1008 updates the parameter p supplied to the terminal 1006 in accordance with the function value ~ as follows:
(i) W ~ r and 5 ubsequent S ~ P ~ O for W ~ 0 P ~- W for 0 <W ~ 1 P ~ or 1 > W
where r is a positive constant~ The function value can be precisely set using.the output signal from the carrier detector 69 (Fig. 6)o The updated parameter is returned to the selector 1002 through the terminal 1O06D
~ ig. 12 is a block diagram of a second embodiment of the network control section 53. This ne~work i5 substantially the same as that shown ln Fig. 7, except that a channel collislon detector 1020 is added, and that an output signal from the detector 1020 is supplied to a control circuit 1021 in place of the.control circuit 79.
The channel collision detector 1.020 serves to detect errors in all received packetsO When the channel collision detector 1020 detects a packet error, it determines that this packet is in collision with another packet. As a result, the channel collision detector 1020 I, generates a collision signalO
Fig~ 13 is a bl.ock diagram of the control circuit 1021 shown in Fig 12~ The control circuit 1021 is substantially the same as the first embodiment of the control circuit~79 (Fig. 10), except that the control - 24 - .

~Z~ 33 circuit 1021 receives the collision signal from the channel collision detector lOZ0 through a terminal 1021~
In the above embodiments, a plurality of channels are formed along the time baseO However, the present invention can also be applied to a plurality of channels formed with respect to the frequency bandwidthO

Claims (13)

What is Claimed is:
1. A method for performing packet communication in a multiple access system comprising:
sharing a single communication medium by a plurality of user stations through a plurality of channels;
monitoring by each user station a state of each channel; and controlling probability of packet transmission in accordance with a monitored result.
2. A multiple access system for performing packet communication involving sharing of a single communication medium by a plurality of users through a plurality of channels such that each user monitors a state of each channel and probability of packet transmission is controlled in accordance with a monitored result, comprising:
an interface section for linking data together as a packet;
a modem section for modulatlng/demodulating a packet, said modem section including a carrier detector for detecting whether or not the channel is being used and for generating one of empty and busy signals;
a network control section for performing access control, said network control section including a collision detector for detecting a transmitting packet and a delayed receiving packet so as to detect a collision of the transmitting packet with another transmitting packet, said collision detector generating a success signal when the transmitting packet and the delayed receiving packet coincide with each other and a collision signal when the transmitting packet and the delayed receiving packet do not coincide, a retransmitter for retransmitting a packet identical withe the transmitting packet when the transmitting packet collides with said delayed receiving packet, and a control circuit for receiving a slot sync pulse, one of the busy and empty signals, one of the success and collision signals, and a packet arrival pulse, and for generating a control signal to control packet transmission; and an RF section for converting an IF signal to a high frequency transmission signal and vice versa.
3. A system according to claim 2, wherein said modem section further includes:
a modulator for modulating the packet;
a demodulator for demodulating a modulated packet to generate a demodulated signal; and a slot sync signal detector for receiving the demodulated signal to extract the slot sync signal constantly propagated along the channel and for generating and supplying the slot sync signal to said network control section.
4. A system according to claim 2, wherein said network control section further includes:
a buffer for supplying the packet arrival pulse to said control circuit every time said buffer receives the packet;
a gate circuit which is turned on in response to the control signal supplied from said control circuit thereto so as to pass the packet therethrough;
a delay circuit for delaying the packet from said gate circuit and for supplying a delayed packet to said retransmitter and said collision detector; and an address filter for receiving only the packet destined therefor and supplying the packet to said interface section.
5. A system according to claim 2, wherein said control circuit comprises:
a memory for storing parameter data the number of which corresponds to the number of the channels;
a counter for counting the slot sync pulse in units of one frame, and subtracting the number of slots corresponding to a transmission delay time from count data thereof so as to obtain subtracted data;

a selector for receiving the subtracted data and the count data and for reading out parameter data corresponding to the subtracted data and the count data;
an arithmetic operation unit for receiving the parameter data corresponding to the subtracted data, updating the parameter data, and supplying updated parameter data to said memory, and a pattern generator for receiving the parameter data corresponding to the count data and generating the control signal using as a probability the updated parameter data from said selector, thereby opening said gate circuit in accordance with the probability.
6. A system according to claim 2, wherein said control circuit comprises:
a first memory for storing parameter data the number of which corresponds to the number of the channels;
a second memory for storing single parameter data for controlling a sequence flow;
a counter for counting the slot sync pulse in units of one frame, subtracting a number of slots corresponding to a transmission delay time from count data thereof so as to obtain subtracted data;
a first selector for receiving the subtracted data and the count data and reading out parameter data corresponding to the subtracted data and the count data;
a first arithmetic operation unit for receiving the parameter data corresponding to the subtracted data, updating the parameter data, and supplying updated parameter data to said first memory;
a second selector for reading out the single parameter data from said second memory;
a second arithmetic operation unit for receiving and updating the single parameter data, thereby restoring updated single parameter data in said second memory;
a multiplier for multiplying the updated subtracted parameter data from said first selector by the updated single parameter data from said second selector;
and a pattern generator for receiving multiplied parameter data from said multiplier and generating the control signal using as a probability the multiplied parameter data from said multiplier, thereby opening said gate from said multiplier, thereby opening said gate circuit in accordance with the probability.
7. A system according to claim 5 , wherein said arithmetic operation unit comprises.
a function generator for generating a function value ? ( ?= 1 under a first condition that one of the empty and success signals is detected; ? = -1 under a second condition excluding the first condition); and a first arithmetic logic circuit for receiving the function value ? so as to perform an operation P? ? P? + x ? where ? = 1 ..... L, L being the number of channels, 0?P? ? 1, and x is a small positive number.
8. A system according to claim 7 further comprising.
a second arithmetic operation circuit for performing an operation ( .SIGMA.P? - 1) where ? is a Lagrangean constant, 0??, and ? is a small positive number; and a third arithmetic operation circuit for computing the Lagrangean constant ? in accordance with ?? min (?,?0) for ?0 ?1, whereby said first arithmetic operation circuit is caused to perform an operation P? ?P? + x ( ?+?).
9. A system according to claim 8 further comprising an averaging circuit for producing ? L where ? is an average of arrival frequency, whereby said second arithmetic operation circuit performs an operation
10. A system according to claim 2, wherein said network control section further includes:
a channel collision detector for detecting errors of all the received packets, said control circuit receiving a collision signal from said channel collision detector.
11. A system according to claim 10, wherein said network control section further includes:
a buffer for supplying the packet arrival pulse to said control circuit every time said buffer receives the packet;
a gate circuit which is turned on in response to the control signal supplied from said control circuit so as to pass the packet therethrough;
a delay circuit for delaying the packet from said gate circuit and for supplying a delayed packet to said retransmitter and said collision detector; and an address filter for receiving only the packet destined thereto and supplying the packet to said interface section.
12. A system according to claim 10, wherein said control circuit comprsies:
a first memory for storing parameter data the number of which corresponds to the number of the channels;
a second memory for storing single parameter data for controlling a sequence flow;
a counter for counting the slot sync pulse in units of one frame, subtracting a number of slots corresponding to a transmission delay time from count data thereof so as to obtain subtracted data;
a first selector for receiving the subtracted data and the count data and reading out parameter data corresponding to the subtracted data and the count data;
a first arithmetic operation unit for receiving the parameter data corresponding to the subtracted data, updating the parameter data, and supplying updated parameter data to said first memory;
a second selector for reading out the single parameter data from said second memory;
a second arithmetic operation unit for receiving and updating the single parameter data, thereby restoring updated single parameter data in said second memory;
a multiplier for multiplying the updated subtracted parameter data from said first selector by the updated single parameter data from said second selector;
and a pattern generator for receiving multiplied parameter data from said multiplier and generating the control signal using as a probability the multiplied parameter data from said multiplier, thereby opening said gate circuit in accordance with the probability.
13. A system according to claim 6 or 12, wherein said second arithmetic operation circuit comprises:
a function generator for generating a function value ? ( ? = -1 under a first condition that the collision signal is detected; ? = ?0?0 under a second condition excluding the first condition); and an arithmetic logic circuit for receiving and updating the function value ? in accordance with the updated single parameter data so as to perform an operation P ? P + r ? (where P is the single parameter data 0 ?P?1, ? is the function value, and r is a small positive number.
CA000430342A 1982-06-14 1983-06-14 Multiple access system and method Expired CA1200933A (en)

Applications Claiming Priority (6)

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JP101913/'82 1982-06-14
JP57101913A JPS58219838A (en) 1982-06-14 1982-06-14 Method of multi-access
JP29741/'83 1983-02-24
JP58029741A JPS59154844A (en) 1983-02-24 1983-02-24 Packet communication device
JP40057/'83 1983-03-11
JP58040057A JPS59167150A (en) 1983-03-11 1983-03-11 Packet communicating device

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DE3374507D1 (en) 1987-12-17

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