CA1194155A - Frequency synthesiser - Google Patents
Frequency synthesiserInfo
- Publication number
- CA1194155A CA1194155A CA000423837A CA423837A CA1194155A CA 1194155 A CA1194155 A CA 1194155A CA 000423837 A CA000423837 A CA 000423837A CA 423837 A CA423837 A CA 423837A CA 1194155 A CA1194155 A CA 1194155A
- Authority
- CA
- Canada
- Prior art keywords
- frequency
- circuit
- jitter
- signal
- synthesiser
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
- H03L7/1978—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider using a cycle or pulse removing circuit
Abstract
ABSTRACT
"Frequency synthesiser".
A frequency synthesiser of the type having a reference frequency source CPG, frequency reduction means PS which cancels pulses from a frequency to be reduced and a jitter compensation signal circuit arranged to compensate for any jitter in the output frequency that would otherwise be caused by each cancelled cycle. The jitter compensation signal is derived from a jitter-containing pulse train via a d.c. removal circuit DCR and an integrator INT. Additionally, a perturbation signal is injected by a control device CD which causes pulses to be added to and also to be subtracted, by PA and PS res-pectively, from the frequency to be reduced, the jitter caused by this addition and subtraction also being com-pensated for by the compensation signal circuit.
"Frequency synthesiser".
A frequency synthesiser of the type having a reference frequency source CPG, frequency reduction means PS which cancels pulses from a frequency to be reduced and a jitter compensation signal circuit arranged to compensate for any jitter in the output frequency that would otherwise be caused by each cancelled cycle. The jitter compensation signal is derived from a jitter-containing pulse train via a d.c. removal circuit DCR and an integrator INT. Additionally, a perturbation signal is injected by a control device CD which causes pulses to be added to and also to be subtracted, by PA and PS res-pectively, from the frequency to be reduced, the jitter caused by this addition and subtraction also being com-pensated for by the compensation signal circuit.
Description
1~94~55 PHB 32.864 1 25.8.1982 "Frequency synthesiser"
This invention relates to a frequency synthe-siser comprising a referonce frequency generator, a fre-quency control circuit which includes a variable fre-quency reduction means comprising a cycle cancellation circuit which is arranged to cancel a cycle of the fre-quency to be reduced by the reduction means for each in-put pulse to said circuit from a pulse source, and a jitter compensation signal circuit connected to the fra~
quency control circuit, the output signal of the jitter compensation signal circuit being arranged to compensate, at least partly, for any jitter in the period of the output frequency that would otherwise be caused by each cancelled cycle.
Such frequency synthesisers are known and are either of the "direct" type in which the output frequency is derived directly from the reference frequency or of the indirect, or phase lock loop, type in which the output frequency i5 generated by a variable frequency oscillator forming part of a phase lock loop which locks the oscilla-20 tor to a predetermined rational fraction, which is to be understood as including a multiple, of the reference frequency.
Examples of direct frequency synthesisers are described in U.K. Patent Specifications 1,545,953 and
This invention relates to a frequency synthe-siser comprising a referonce frequency generator, a fre-quency control circuit which includes a variable fre-quency reduction means comprising a cycle cancellation circuit which is arranged to cancel a cycle of the fre-quency to be reduced by the reduction means for each in-put pulse to said circuit from a pulse source, and a jitter compensation signal circuit connected to the fra~
quency control circuit, the output signal of the jitter compensation signal circuit being arranged to compensate, at least partly, for any jitter in the period of the output frequency that would otherwise be caused by each cancelled cycle.
Such frequency synthesisers are known and are either of the "direct" type in which the output frequency is derived directly from the reference frequency or of the indirect, or phase lock loop, type in which the output frequency i5 generated by a variable frequency oscillator forming part of a phase lock loop which locks the oscilla-20 tor to a predetermined rational fraction, which is to be understood as including a multiple, of the reference frequency.
Examples of direct frequency synthesisers are described in U.K. Patent Specifications 1,545,953 and
2~ 2,062,315, and examples of phase lock loop synthesisers are described in U.K. Patent Specifications 1,447,418 and 2,068,185~. In each type, it is known to in~lude in the frequency reduction means a variable modulus divider to provide the major part o:f the required frequency reduction.
Such dividers generally produce spectrally pure frequen-cies which are exact subharmonics of the frequency whichis to be divided. The frequencies other than subharmonics 1~94~55 PHB 32.86~ 2 25.8.1982 are produced by a cycle cancellation technique in which selected cycles of the frequency to be reduced are can-celled. Such a technique is well known and is alternative-ly referred to as sidestep programming (see for example A.F. Evers and D.J. Martin, "Improved forms of digital frequency synthesisers", IEE Colloquium Digest 197Z~11, pp. 9/1 to 9/5), pulse blanking~ pulse removal, pulse cancellation, and pulse or cycle swallowing. The technique is also described in Mullard Technical Note 142 "Versatile LSI frequency synthesiser" pp. 8, 9.
For example a frequency synthesiser may have a range of 1.6 MHz to 30 MHz adjustable by means of one or more modulo-N dividers where N is adjustable to provide the range in 1 kHz steps. These steps may then be further subdivided by the use of a rate, or fractional, multiplier which, for example, produces an output frequency variation of 0 to 990 Hz in 10 Hz fractional steps. In this manner, the whole range 1.6 MHz to 30 MHz is covered in 10 Hz fractional steps. The adjustable frequency given by these fractional steps is usually referred to as the offset fre-quency and is provided by means of a cycle cancellation circuit controlled by the output of the rate multiplier which constitutes the above~mentioned pulse source.
In the prior art devices the pulse source derives the cycle-cancelling pulses from the reference frequency or from the variable frequency oscillator, typically by means of at least a programmable rate multiplier which produces a programmable number of output pulses for a fixed number of input pul~es. These output pulses have an average frequency which can be any rational fraction of the frequency from which they are derived. Since they are strobed by the input pulses, however, the periods between successive output pulses may vary due to the missing pulses and these variations (referred to as "jitterl') would produce variations in the output frequency unless a said compensation circuit is provided to reduce the effects of the jitter.
1~94~55 PHB 32.864 3 25.8.1982 In the frequency synthesiser described in the above-mentioned patent specification 1,447,418, the fre-quency reduction is partly effected by a successive addition rate multiplier which, for each input pulse there-to, adds a programmable increment -to an accumulated value and gives an output pulse each time the capacity of the accumulator is exceeded, leaving the excess as a residue in the accumulator. The principle of its operation can readily be appreciated by taking a simple example in which the capacity of -the accumulator is unity and each input pulse adds 0.7 to the value in the accumulator. Thus the accumulator overflows and gives an output pulse for the 2nd, 3rd, 5th9 6th, 8th~ 9th and 10th input pulses- i.e.
seven output pulses for ten input pulses. In other words, the average pulse repetition rate has been multiplied by 0.7 by the rate multiplier. The said patent specification describes a phase lock loop system in which the residue in the accumulator is converted to analogue form in a digital-to-analogue converter and the resultant analogue signal is used to compensate for any variation in the out-put of a phase comparator, in the phase lock loop, due to jitter.
If there is any residual imbalance in the jitter compensation arrangement 9 this imbalance appears in the output frequency as a spurious discrete sideband signal.
This signal may typically be 30 dB down with respect to the main output signal and whilst this is adequate in the audio pass band in communication receivers, it is not adequate for broadcast receivers. If, for example the output frequency is 100 k~z and the offset frequency is 12.5 kHz, any spurious signal would be in the adjacent channel, whereas the specification for such equipment re-quires the level of any such signal to be at least 90 dB
down. One object of the invention is at least to mitigate this problem.
In known frequency synthesisers, the compensation signal, which effectively predicts any jitter, is derived 1~94~55 PHB 32.86~ 4 25.8.1982 ~rom the circuitry of, or associated with, the rate multi-plier, or at least depends upon the "history" of the pulses which cause the cycle cancellation, in order to provide the predictive compensation signal. The relevant circuitry involved is fairly complex. A furtherobject of the invention is to provide a frequency synthesiser of the type defined in the opening paragraph hereof which enables the electronic hardware to be reduced, provides improved sideband suppression, and enables any pulse source to be used.
The above-mentioned U,K. Patent Specification 2,o68,185A describes a frequency synthesiser of the type including an automatic servo which includès a detector arranged to detect any residual jitter in the circuit after application of the compensation signal, and a variable gain amplifier arranged to control the amplitude of the compensation signal, the gain of the amplifier being controlled by the detector to reduce any said residual jitter. In this manner the detector and amplifier form an automatic servo which adjusts the amplitude of the com-pensation signal in dependence upon the detected residual jitter in order to minimise that jitter.
The frequency synthesiser described in the above-mentioned U.K. Patent Specification No. 2,068,185A employs such an automatic servo. However after a frequency step change in which the offset frequency step size is a small fraction of the main step size, the servo may take some little time to settle. This time, although adequate for many purposes, may be too long for the frequency synthe-siser to be used for example in frequency-hopping radio systems or as a microwave synthesiser. The reason for this delay in the settling time can be explained by taking the example referred to above in which the main step size is 1 kHz and the offset frequency is adjustable in lO Hz steps, The fractional step is thus O.Ol and the servo re-ceives information at the lO Hz rate; that is to say that in the worst case the servo may have to wait for one-~9~55 PHB 32.864 5 25 8.1982 tenth of a second before it senses whether or not thesystem has any residual imbalance. For this reason it is necessary to include a time constant of this order in the servo loop to ensure satisfactory operation under the worst case conditions where the offset frequency is lO Hz or 99O Hz. Yet a further object of the invention is to enable this time constant to be very substantially reduced in frequency synthesisers provided with an automatic servo.
Accordingly the invention provides a frequency synthesiser comprising a reference frequency generator, a frequency control circuit which includes a variable fre-quency reduction means comprising a cycle cancellation cir-cuit which is arranged to cancel a cycle of the frequency to be reduced by the reduction means for each input pulse to said circuit from a pulse source, and a jitter compen-sation circuit connected to the frequency control circuit, the output signal of the jitter compensation signal cir-cuit being arranged to compensate, at least partly, for any jitter in the period of the output frequency of the synthesiser that would otherwise be caused as a result of each cancelled cycle, characterized in that the jitter com-pensation signal circuit comprises a d.c. removal circuit followed by an analogue integrator, and in that the synthe-siser further includes a control device the control signal output of which is arranged to cause the frequency control circuit to cancel further cycles from, and also to add cycles to, the said frequency to be reduced in a given sequence, and a control signal compensation circuit which is connected to the control device and is arranged to com-pensate for any jitter in the output frequency of the syn-thesiser that would otherwise be caused by the control sig-nal.
A frequency synthesiser according to the in-vention has the advantages that any pulse source may be used to provide the frequency offset and that the compen-sation signal, which in effect predicts the phase jitter, is derived by d.c. removal and analogue integration of ~94~S5 PHB 32.864 6 25.8.1982 any pulse train containing jitter caused by the source.
In known frequency synthesisers of the so-called "phase predict" type in which a jitter compensation signal is generated, the compensation signal circuit uses digital techniques and generally includes a digital-to-analogue converter. In the practical implementation of these tech-niques, it is not possible to get the various analogue step sizes identical over the whole signal range required.
As a result, spurious sideband noise is produced at a level of about 30 dB down with respect to the output signal level. Using direct analogue integration9 however, no con-version errors are produced after gain balancing and the sideband noise level is reduced by a further 20 to 30 dB.
Thus a synthesiser according to the invention not lS only provides a remarkable improvement in sideband reject-ion but also very considerably reduces the circuit com-plexity. It is in fact the case that the compensation cir-cuit can be connected to substantially any point in the synthesiser circuit at which a pulse train appears which contains jitter and may, for example, be connected to the input or to the output of the cycle cancellation circuit.
In the former case the compensation signal is derived from the pulses which cause the cycle cancellation whereas in the latter case it is derived from a pulse train from which the cycles have been cancelled.
For present purposes, the d.c. removal circuit referred to above is to be understood as including not only d.c. blocking circuits but also circuits which compen-sate for or nullify any effect the d.c. may have. Thus
Such dividers generally produce spectrally pure frequen-cies which are exact subharmonics of the frequency whichis to be divided. The frequencies other than subharmonics 1~94~55 PHB 32.86~ 2 25.8.1982 are produced by a cycle cancellation technique in which selected cycles of the frequency to be reduced are can-celled. Such a technique is well known and is alternative-ly referred to as sidestep programming (see for example A.F. Evers and D.J. Martin, "Improved forms of digital frequency synthesisers", IEE Colloquium Digest 197Z~11, pp. 9/1 to 9/5), pulse blanking~ pulse removal, pulse cancellation, and pulse or cycle swallowing. The technique is also described in Mullard Technical Note 142 "Versatile LSI frequency synthesiser" pp. 8, 9.
For example a frequency synthesiser may have a range of 1.6 MHz to 30 MHz adjustable by means of one or more modulo-N dividers where N is adjustable to provide the range in 1 kHz steps. These steps may then be further subdivided by the use of a rate, or fractional, multiplier which, for example, produces an output frequency variation of 0 to 990 Hz in 10 Hz fractional steps. In this manner, the whole range 1.6 MHz to 30 MHz is covered in 10 Hz fractional steps. The adjustable frequency given by these fractional steps is usually referred to as the offset fre-quency and is provided by means of a cycle cancellation circuit controlled by the output of the rate multiplier which constitutes the above~mentioned pulse source.
In the prior art devices the pulse source derives the cycle-cancelling pulses from the reference frequency or from the variable frequency oscillator, typically by means of at least a programmable rate multiplier which produces a programmable number of output pulses for a fixed number of input pul~es. These output pulses have an average frequency which can be any rational fraction of the frequency from which they are derived. Since they are strobed by the input pulses, however, the periods between successive output pulses may vary due to the missing pulses and these variations (referred to as "jitterl') would produce variations in the output frequency unless a said compensation circuit is provided to reduce the effects of the jitter.
1~94~55 PHB 32.864 3 25.8.1982 In the frequency synthesiser described in the above-mentioned patent specification 1,447,418, the fre-quency reduction is partly effected by a successive addition rate multiplier which, for each input pulse there-to, adds a programmable increment -to an accumulated value and gives an output pulse each time the capacity of the accumulator is exceeded, leaving the excess as a residue in the accumulator. The principle of its operation can readily be appreciated by taking a simple example in which the capacity of -the accumulator is unity and each input pulse adds 0.7 to the value in the accumulator. Thus the accumulator overflows and gives an output pulse for the 2nd, 3rd, 5th9 6th, 8th~ 9th and 10th input pulses- i.e.
seven output pulses for ten input pulses. In other words, the average pulse repetition rate has been multiplied by 0.7 by the rate multiplier. The said patent specification describes a phase lock loop system in which the residue in the accumulator is converted to analogue form in a digital-to-analogue converter and the resultant analogue signal is used to compensate for any variation in the out-put of a phase comparator, in the phase lock loop, due to jitter.
If there is any residual imbalance in the jitter compensation arrangement 9 this imbalance appears in the output frequency as a spurious discrete sideband signal.
This signal may typically be 30 dB down with respect to the main output signal and whilst this is adequate in the audio pass band in communication receivers, it is not adequate for broadcast receivers. If, for example the output frequency is 100 k~z and the offset frequency is 12.5 kHz, any spurious signal would be in the adjacent channel, whereas the specification for such equipment re-quires the level of any such signal to be at least 90 dB
down. One object of the invention is at least to mitigate this problem.
In known frequency synthesisers, the compensation signal, which effectively predicts any jitter, is derived 1~94~55 PHB 32.86~ 4 25.8.1982 ~rom the circuitry of, or associated with, the rate multi-plier, or at least depends upon the "history" of the pulses which cause the cycle cancellation, in order to provide the predictive compensation signal. The relevant circuitry involved is fairly complex. A furtherobject of the invention is to provide a frequency synthesiser of the type defined in the opening paragraph hereof which enables the electronic hardware to be reduced, provides improved sideband suppression, and enables any pulse source to be used.
The above-mentioned U,K. Patent Specification 2,o68,185A describes a frequency synthesiser of the type including an automatic servo which includès a detector arranged to detect any residual jitter in the circuit after application of the compensation signal, and a variable gain amplifier arranged to control the amplitude of the compensation signal, the gain of the amplifier being controlled by the detector to reduce any said residual jitter. In this manner the detector and amplifier form an automatic servo which adjusts the amplitude of the com-pensation signal in dependence upon the detected residual jitter in order to minimise that jitter.
The frequency synthesiser described in the above-mentioned U.K. Patent Specification No. 2,068,185A employs such an automatic servo. However after a frequency step change in which the offset frequency step size is a small fraction of the main step size, the servo may take some little time to settle. This time, although adequate for many purposes, may be too long for the frequency synthe-siser to be used for example in frequency-hopping radio systems or as a microwave synthesiser. The reason for this delay in the settling time can be explained by taking the example referred to above in which the main step size is 1 kHz and the offset frequency is adjustable in lO Hz steps, The fractional step is thus O.Ol and the servo re-ceives information at the lO Hz rate; that is to say that in the worst case the servo may have to wait for one-~9~55 PHB 32.864 5 25 8.1982 tenth of a second before it senses whether or not thesystem has any residual imbalance. For this reason it is necessary to include a time constant of this order in the servo loop to ensure satisfactory operation under the worst case conditions where the offset frequency is lO Hz or 99O Hz. Yet a further object of the invention is to enable this time constant to be very substantially reduced in frequency synthesisers provided with an automatic servo.
Accordingly the invention provides a frequency synthesiser comprising a reference frequency generator, a frequency control circuit which includes a variable fre-quency reduction means comprising a cycle cancellation cir-cuit which is arranged to cancel a cycle of the frequency to be reduced by the reduction means for each input pulse to said circuit from a pulse source, and a jitter compen-sation circuit connected to the frequency control circuit, the output signal of the jitter compensation signal cir-cuit being arranged to compensate, at least partly, for any jitter in the period of the output frequency of the synthesiser that would otherwise be caused as a result of each cancelled cycle, characterized in that the jitter com-pensation signal circuit comprises a d.c. removal circuit followed by an analogue integrator, and in that the synthe-siser further includes a control device the control signal output of which is arranged to cause the frequency control circuit to cancel further cycles from, and also to add cycles to, the said frequency to be reduced in a given sequence, and a control signal compensation circuit which is connected to the control device and is arranged to com-pensate for any jitter in the output frequency of the syn-thesiser that would otherwise be caused by the control sig-nal.
A frequency synthesiser according to the in-vention has the advantages that any pulse source may be used to provide the frequency offset and that the compen-sation signal, which in effect predicts the phase jitter, is derived by d.c. removal and analogue integration of ~94~S5 PHB 32.864 6 25.8.1982 any pulse train containing jitter caused by the source.
In known frequency synthesisers of the so-called "phase predict" type in which a jitter compensation signal is generated, the compensation signal circuit uses digital techniques and generally includes a digital-to-analogue converter. In the practical implementation of these tech-niques, it is not possible to get the various analogue step sizes identical over the whole signal range required.
As a result, spurious sideband noise is produced at a level of about 30 dB down with respect to the output signal level. Using direct analogue integration9 however, no con-version errors are produced after gain balancing and the sideband noise level is reduced by a further 20 to 30 dB.
Thus a synthesiser according to the invention not lS only provides a remarkable improvement in sideband reject-ion but also very considerably reduces the circuit com-plexity. It is in fact the case that the compensation cir-cuit can be connected to substantially any point in the synthesiser circuit at which a pulse train appears which contains jitter and may, for example, be connected to the input or to the output of the cycle cancellation circuit.
In the former case the compensation signal is derived from the pulses which cause the cycle cancellation whereas in the latter case it is derived from a pulse train from which the cycles have been cancelled.
For present purposes, the d.c. removal circuit referred to above is to be understood as including not only d.c. blocking circuits but also circuits which compen-sate for or nullify any effect the d.c. may have. Thus
3~ whilst the presence of d c. in the signal applied to the integrator could cause the latter to saturate, the effect of the d.c. can be compensated for or nullified in a manner described, for example, in United Kingdom Patent Specifi-cation No. 2,074,421A.
The compensation signal circuit may include an amplifier the gain of which is inversely proportional to the output frequency of the synthesiser. This not only en-S~
PHB 32.864 7 Z5.8.1982 sures that the level of the compensation signal is correct but also that any variation in the output signal due to large frequency changes in the output frequency o~ the synthesiser is precisely compensated for.
In addition to the reduction of the level of the sideband noise by the use of the d.c. removal circuit and analogue integrator, a very significant reduction in the level of any spurious discrete sideband signal is achieved by the above-mentioned addition and subtraction of cycles.
As referred to above, any residual imbalance in the jitter compensation circuit would give rise to a spurious sideband signal having a discrete frequency determined by the offset ~requency. The effect of adding and subtracting pulses is to introduce a perturbation signal into the system. In the lS event of any residual imbalance in the compensation circuit, the energy in the spurious discrete signal is mixed with the perturbation signal and is spread over a wide spectrum with the result that it appears as noise at a considerably lower level. The result of this double noise reduction is that the synthesiser can be used in broadcast systems, etc.
In frequency sythesisers having an automatic servo, which detects the sign or phase of any residual im-l~d/4nc~
au~ in the system and uses this imbalance to control the gain of the compensation signal or signals in such a direction as to reduce the imbalance, the imbalance sig-nals caused by the added and subtracted pulses implies that the servo receives information at a much higher minimum rate. Thus the time constant can be very considerably shortened and this makes the response of the synthesiser to changes in the required frequency far more rapid, with the result that the utility of the synthesiser is con-siderably extended.
It is not essential for the con-trol device to be arranged to add the same number of cycles as it cancels -any difference between the numbers merely represents a fre-quency offset. Preferably, however, the number of added cycles is substantially the same as the number of cancelled ~4~55 PH~ 32.864 8 25.8.1982 cycles in any given period, since substantially no fre-quency offset is then caused.
The con-trol signal output of the control device may have three states - namely a first state which causes a pulse to be cancelled~ a second (neutral) state which causes no pulse addition or cancellation, and a third state which causes a pulse to be added.
The control signal may comprise at least first and second interspersed pulse sequences, the arrangement lD being such that each pulse of the first sequence causes a cycle to be cancelled from, and each pulse in the second se-quence causes a cycle to be added to~ the frequency to be reduced. By interspersing the sequences, the instantaneous frequency of the frequency to be reduced is, at any instant, closer to its average frequency that would be the case if a long series of cancelled pulses were followed by a long series of corresponding added pulses. The minimum instan-taneous deviation from the average frequency is given if the pulses of the two sequences are arranged alternately. A
very considerable advantage accrues, however, if the two pulse sequences are interspersed and occur in a random manner. Any phase jitter energy in the output frequency caused by any residual imbalance in the compensation signals is then made completely noise-like and is spread over such a wide spec-trum that it is substantially undetectable. Sub-stantially the same spreading effect can be achieved, but in a more convenient practical m~nner, i~ the two sequences together form a pseudo-random sequence since such sequences may easily be generated in well known manner.
In order to minimise the amount of jitter re-sulting from the control signal, the latter may be in Manchester-coded form or may be a differentiated code sig-nal. In this context differentiation means converting a rising transition of a clocked input signal to a +1 output signal, a falling transition to a -1 output signal, and the lack of a transition to a O.
The synthesiser may include means for combining 1~194~S5 PHB 32.86~ 9 25.8.19~2 the outputs of the jitter and control signal compensation circuits to form a combined compensation signal. Thus only a single correction signal need be applied to the jitter correction arrangement, for example a phase modulator or a programmable delay generator. Although the principle of operation of a phase modulator in this art is usually different from that of a programmable delay generator, the effect of each for present purposes is substantially the same.
The frequency synthesiser may include a detector arranged to detect any residual jitter in the circuit after application of the combined compensation signal, and a variable gain amplifier arranged to control the amplitude of the combined compensation signal, the gain of the ampli-fier being controlled by the detector to reduce any said residual jitter. In this manner the detector and amplifier form an automatic servo, referred to above, which adjusts the amplitude of the compensation signal in dependence upon the detected residual jitter in order to minimise that jitter.
Embodiments of the invention will now be des-cribed 9 by way of example, with reference to the accom-panying drawing, of which:
Figure 1 shows a block schematic circuit diagram of a frequency synthesiser of the phase lock loop type, and Figure 2 shows a block schematic circuit diagram of a frequency synthesiser of the direct type.
Figure 1 shows a block schematic circuit diagram of a first embodiment of the invention comprising a voltage-controlled variable frequency oscillator VFO, the output of which constitutes the synthesiser output (fre-quency Fo) and is connected to one input of a pulse swallow circuit PS. The output of circuit PS is connected via a pulse adder PA to a programmable divider PD which di-vides by an adjustable number N ~ 1. The output of dividerPD is connected to a first comparison input of a phase comparator PC and also to the strobe input of a strobing 1~9~55 PHB 32.864 10 25.8.1982 circuit STR. l'he other input of circuit STR is connected to the ou$put of an offset frequency source OFS having a variable of~set frequency Fos in a range which is low re-lative to the output frequency range of the synthesiser.
For example, the synthesiser may have an output frequency range of 1.6 MHz to 30 MHz adjustable by divider PD in 1 kHz steps and the variable offset frequency source OFS
may have a range of O to 990 Hz variable in 10 Hz steps.
The source may, for example~ derive the offset frequency from a clock pulse generator CPG or from the output of ~ivider PD, the connections thereto not being shown in the Figure. Thus, for example, the source OFS may comprise a rate multiplier and a divider as shown at RM and D1 res-pectively in Figure 3 of U.~. Patent Specification 1,447,418 or may simply comprise a rate multiplier R as shown in Figure 2 of that specification. The offset frequency source may alternatively generate an offset frequency directly in response to an analogue or a digital input. There are of course many ways in which such an offset frequency may be provided - all that is required is that the range of the output frequency Fos of the source is low compared with the frequency range of the synthesiser since the con-trollable range of frequency Fos establishes the smallest frequency step of the synthesiser.
The output of strobing circuit STR is connected to the "swallow" command input of pulse swallow circuit PS
and also to the input of a d.c. removal circuit DCR via an adder ADD and a gain controlled amplifier GCA. The out-put of the circuit DCR is fed via an analogue integrator INT to the phase control input of a phase modulator PM. The clock pulse generator CPG provides pulses having a high stable repetition rate (frequency) and the frequency of these pulses is, if required, divided down in a divider DIV to provide a reference frequency Fr (e.g. 1000 p.p.s.) which is fed via the phase modulator PM to ~ second com-parison input of phase comparator PC. The output signal from comparator PC is fed to the frequency control input of oscillator VFO v a low-pass loop filter LP~.
~4~55 PHB 32.864 11 ~ 25.8~1982 The operation of the phase lock loop control circuit VFO-PS-PD-LPF-VFO is well known and is described in terms of these referenced items in the above-mentioned U K. Patent Specification 1,447,418. Briefly, the output signal of comparator PC is integrated in a low-pass filter LPF and adjusts the frequency of the oscillator VFO until the phase of the signal fed to the first comparison input of comparator PC from divider PD is identical to the phase of the signal fed to the second comparison input of the comparator PC via phase modulator PM. If the relative phase of the two input signals to comparator PC tend to differ slightly, then the output signal of comparator PC
changes accordingly in such a direction that the phase of oscillator VFO is shifted to reduce the phase difference between the two input signals to comparator PC to zero The remainder of the circuit differs from the prior art and its operation will therefore be described in more detail. Output pulses from the source OFS, having an average frequency Fos, are strobed in circuit STR
by the output pulses of divider PD to produce output pulses of a defined length. These pulses operate circuit PS in precisely the same manner as the corresponding pulses Fr in Figure 2 of said Patent Specification No.
1,447,418 and offset the output frequency Fo by Fos Thus Fos may be selected to give a very fine control of the output frequency Fo. These pulseq form a pulse signal A
which, ignoring for a moment any effect of adder ADD and amplifier GCA, is applied to the d.c. removal circuit DCR
which either removes any d.c. component in the pulse signal (e.g. by a series capacitor) or compensation for any saturation effect the d.c. may give rise to in the integrator. A particularly suitable compensation method is described in Patent Specification No. GB 2,072,241A. The resulting signal B is in-tegrated by an analogue integrator INT to produce a signal C which is used to control the phase delay generated by phase modulator PM.
As described above, the operation of the circuit 1~34~55 PH~ 32.864 12 25.8.198~
PS in response to the strobed pulse signal A causes jitter in the pulses appearing at the output of divider PD, this jitter appearing as a phase delay in the pulses each time circuit PS is caused to swallow (i.e. cancel or subtract) a pulse by the arrival of a pulse in signal A. This same pulse is used, via the circuit elements DCR and INT, to cause a corresponding phase delay in the pulse from phase modulator PM. Thus the pulse from modulator PM to compa-rator PC is delayed to substantially the same extent as the jitter delay in the corresponding pulse from divider PD. Thus the effects of jit-ter on the output frequency Fo of oscillator ~FO are at least very substantially reduced.
In effect, the signal C has a value which pre-dicts any p~ase delay resulting from jitter and compen-lS sates for this delay accordingly. As would be expected,as the offset frequency Fos is increased, so the amount of jitter per unit of time increases and the value of the jitter-compensating signal C increases The average value of the signal B is zero, due to the removal of the d.c.
content, and hence the signal C is a function of the amount of jitter caused by the pulse swallowing technique.
The function of gain-controlled amplifier GCA will be described below.
Whilst the amplifier GCA is shown preceding the removal circuit DCR, it will be evident to those skilled in the art that it may be located anywhere in the series circuit ADD-DCR-INT-P~.
From the above, it can be appreciated that the phase correction signals are derived in a very simple manner directly from the phase jitter actually caused by the offset frequency source OFS. Further, the correction steps are derived by analogue integration - in contra-distinction to known systems which are based on digital means - with the result that the correction signal does not suffer from the discontinuities which can be intro-duced by inaccuracies of practical digital-to-analogue converters which occur in known phase prediction methods.
1~4~55 PHB 32.864 13 25 8.1~82 Thus a reduction in the system noise is achieved.
The circuit further includes a control device CD fed with synchronising pulses from the output of di-vider PD. Circuit blocks PS, PA, and PD form a frequency control circuit to which control device CD is connected in order to provide a control signal thereto comprising two interspersed sequences of pulses P1 and P2. Each P1 pulse causes adder PA to add a pulse (cycle) to the frequency Fo and each P2 pulse causes pulse swallow circuit PS to cancel a pulse. Preferably a substantially equal number of P1 and P2 pulses are generated such that, over a time average, there is no net phase error introduced as a result of the control signal and so the process generates no fre-quency error in the system.
Control device CD also provides a combined con-trol signal to an input of adder ADD, the combined signal comprising a +1 pulse for each P1 pulse and a -1 pulse for each P2 pulse. The amplitude of these pulses is adjusted by the gain-controlled amplifier GCA and, aftcr d.c. re-moval by circuit DCR and integration by integrator INT, form a compensation signal which controls phase modulator PM in such a manner that the effects of the jitter at the output of divider PD are precisely matched by a corres-ponding jitter in the output of phase modulator P~l.
As explained above, in a corresponding frequency synthesiser not provided with control device CD, pulse adder PA, and adder ADD, the jitter information in signal B can have a relatively low frequency, for example 10 Hz, and as a result a time constant has to be provided in the compensation signal path of one-tenth of a second or greater. Thus the settling time of the synthesiser to a change in required frequency Fo is one-tenth of a second, which may be too long for some applications. The provision of control device CD, however, causes a "perturbation" sig-nal to be added to the compensation signal by adder ADDwith the result that the information in the compensation signal has a considerably higher repetition rate. The 1~94~55 P~B 32.864 14 25.8.1982 respo-lse time of the compensation signal pa-th can there-fore be made very considerably shorter, thereby consi-derably extending the possible fields of use of the syn-thesiser.
Another advantage is that the energy in any spurious discrete sideband signal which may appear in the output frequency Fo due to any imbalance in the compen-sation circuit is spread over a wide frequency spectrum by the residual perturbation signal appearing in the out-1D put as a result of the same imbalance. In this manner any said imbalance will only produce noise in the output signal at such a low level that it is relatively undetectable.
As is well known, the pulse swallow circuit PS
might comprise a so-called n/(n+1) prescaler which di-vides by n (e.g. 10) in the absence of a pulse in signal Aand by (n+1) if a control pulse is present. In a similar manner, pulse adding circuit PA may comprise an n/(n-1) prescaler. Alternatively1 the pulse adder PA may comprise a divide-by-two circuit, for example forming the first stage of divider PD, which normally divides by 2 but which divides by 1 for each P1 pulse. Alternatively the functions of circuits PS, PA, and PD can be performed by a modulo-(n-1)/n/(n+1) divider as described in the specification of GB Patent Application Z,074,421A.
In principle, the +1 and -1 pulses could be interspersed with 0 periods in which the effective di-vision ratio of the divider arrangement is n1, but then the compensation signal fed to adder ADD would include information which apparently serves no useful purpose. How-ever in order to improve the noise-like nature of the com-pensation signal it may be advantageous to include a number of 0 periods.
The control signal from control device CD which would give the maximum rate of information would be alternate +1 and -1 pulses occurring at the comparator fre-quency Fr, giving a square wave of frequency Fr/~. The com-bined signal is, however, preferably derived from or forms ~9~55 PHB 32.864 15 25.8.1982 a random pseudo-random binary sequence which i9 then Manchester-coded (encoded in pairs of (~ 1) or (-1, +1) depending upon the presence of a 0 or 1 respectively in the sequence) or is differentiated. In some circumstances it may be advantageous to differenti~te the Manchester-coded signal. The random sequence has to be generated at a maxi-mum rate of Fr and if it has a total period of T then its spectrum will be noise-like but with discrete components spaced by frequency T . If T is less than about 100 mS for a typical communication synthesiser, the spectrum can be considered as pure noise. In this case any energy in the output frequency resulting f`rom imbalance in the compen-sation system will not appear as a discrete signal but will be spread out as noise spectrum signal. In this manner, the total imbalance energy can be up to 30 dB greater than the maximum imbalance energy that would be tolerable with-out this spreading action and yet still be inaudible. The following example will serve to illustrate this.
The frequency synthesiser may be used in c~n-nection with a multi-channel communication system having, for example, a channel spacing of 12 2 kHz. If the synthe-siser frequency step is 100 kHz and, say, the fractional offset frequency is 122 kHz, than a spurious 122 kHz signal is produced which will be in the adjacent channel. Without special precautions, this signal would be 30 to 50 dB down with respect to the channel carrier but the CITT specifi-cation requires it to be at least 90 dB down. This is readily achievable by the provision of the control signal having a random or pseudo-random distribution.
If a pseudo-random binary sequence is used which is generated in well known manner from an N-stage shift re-gister with feedback, 2 -1 different codes are generated.
Every code is complemented by another particular code e~cept the all-1~s code since there is no complementary all-O's code. Thus there is a small imbalance once in every com-plete sequence of 2 -1 codes. If the sequence is generated, for example by a shift register having N = 17 stages ~94~55 PHB 32.864 16 25.8.1982 clocked by a 1 MXz clock pulse, the total cycle length is 2 7-1 = 131071 bits, i.e. a rate of 7.63 Hz. Thus there will be a very small imbalance at this rate giving a small offset in the final frequency which, in many cases, will be acceptable. Alternatively, in this case, the imbalance may be eli~inated entirely by the use of the Manchester code or a dif~erentiated code.
If, for reasons of imperfect compensation, some residual energy from the pseudo-random binary sequence causes phase jitter, the sideband components of this jitter will be spaced at 7.63 Hz and9 at that frequency spacing, the sideband energy becomes indistinguishable from white noise and is therefore substantially inaudible.
In the circuit so far described - that is without the provision of an automatic servo circuit shown in broken lines and including a correlator M - the gain of the gain-controlled amplifier GCA may be controlled, in a mamler not shown, to be an inverse function of the fre-quency Fo. The reason for this is as follows.
In effect, the signal C has a value which pre-dicts any phase delay resulting from jitter and compen sates for this delay accordingly, As would be expected, as the offset frequency Fos is increased, so the amount of jitter per unit of time increases and the value of the Z5 jitter-compensating signal C increases. The average value of the signal B is zero, due to the removal of the d.c.
content, and hence the signal C is a function of the amount of jitter caused by the pulse swallowing technique. How-ever the voltage step out of the phase comparator PC when a pulse is subtracted at the input to divider PD is pro-portional to the length of the pulse (i.e. one cycle of the VF0 output frequency) and is therefore inversely pro-portional to the frequency Fo. Thus, in the above-mentioned case of a frequency synthesiser having a range of 1.6 ~IHz to 30 ~Hz, the amplitude of the signals dealt with by the jitter compensation circuit can vary if the synthesiser is switched from one end of its output frequency range to the ~L94~55 PHB 32.864 17 25.8.1982 other. This can cause inaccuracies in the jitter correct-ion signal C and, to compensate for this, the gain-con-trolled amplifier GCA included in the correction signalcircuit may have its gain controlled by a period-to-analogue converter having the frequency Fo fed to its input. In this way, a very precise and accurate compensation for the effects of jitter is provided over the whole frequency range.
Preferably, however, the amplifier GCA forms part of an automatic servo circuit, shown with broken line connections, which further includes a correlator M. The signal input of correlator M is connected to the output of phase comparator PC and the reference input is connected to the output of adder ADD. The correlation signal output of correlator M controls the gain of amplifier GCA. In this manner, correlator M detects any residual jitter appearing at the output of phase comparator PC and varies the gain of amplifier GCA - and hence the amplitude of the correction signal C - to eliminate any residual jitter automatically.
Whilst the ampli~ier GCA is shown preceding the removal circuit DCR, it will be evident to those skilled in the art that it may be located anywhere in the series circuit ADD-DCR-INT-PM.
From the above, it can be appreciated that the phase correction signals are derived in a very simple manner directly from the phase jitter actually in the off-set frequency source OFS. Further, the correctîon steps are derived by analogue means - in contradistinction to known systems which are based on digital means - with the res-ult that the correction signal does not suffer from the discontinuities which can be introduced by inaccuracies of practical digital-to-analogue converters which occur in known phase prediction methods.
In modern frequency synthesisers, there is a requirement for closely-spaced output frequencies and this results in large division ratios and small values of Fos for a given output frequency. This may result in unaccept~
~94~55 P~IB 32.864 18 25.8.1982 able performance in terms of oubput noise and switching speed. The frequency synthesiser according to the invent-iont however, allows small frequency increments whilst at the same time having the noise and switching speed per-formance of a system with a considerably higher referencefrequency Fr.
Figure 2 shows a frequency synthesiser of the direct type, that is to say one in which a variable number of pulses from a reference frequency generator is cancelled in order to provide the required (lower) output frequency.
The synthesiser comprises, in sequence, a stable frequency source comprising a clock pulse generator CPG, a programmable divider DIV (if required) whose output com-prises pulses having a repetition rate (frequency) Fr, a pulse adder PA, a pulse subtractor PS~ a rate multiplier R~l, a delay DL, a ramp generator RG having start and reset inputs S and R respectively, and an analogue comparator COM the output of which constitutes the output frequency Fo of the synthesiser. The compensation signal circuit com-prises a d c~ removal circuit DCR, an analogue integratorINT, a divider DV, a gain-controlled amplifier GCA, and a summing circuit SUM. The multiplying factor of rate multiplier RM is controlled by an input signal n which also determines the division factor of divider DV. It further comprises a correlator M, a low pass filter F and a control device CD. Ths correlator M, filter F, and gain-controlled amplifier GCA form an optional automatic servo.
Ignoring for the moment the operation of the automatic servo M.F.GCA and assuming that the gain of amplifier GCA is unity, ~he operation of the circuit is as follows.
The operation of control device CD, pulse adder PA, and pulse subtractor PS is the same as that described with reference to Figure 1; namely to provide a signal at the input to rate multiplier RM comprising the reference frequency Fr perturbed by added and subtracted cycles (pulses) wnder the control of device CD. Rate multiplier RM
1: L94:~55 PHB 32.864 19 25 8.1982 produces pulses at its output at an average rate given by Frm = nFr where O < n ~ 1 and assuming that the number of pulses added by the arrangement CD-PA-PS is the same over a gi~en period as the number of pulses it subtracts.
These output pulses are synchronised with the input pulses to rate multiplier RM and the extra jitter caused by the added and subtracted pulses appears at the input to d.c.
removal circuit DCR together with the jitter caused by -the rate multiplier RM. The output pulses of circuit DCR are integrated by analogue integrator INT and the integrated signal is then divided by the rate multiplier control sig-nal n in divider DV which may comprise in practice a multiplying digital-to-analogue converter.
The output analogue signal of divider DV is now proportional to the time advances required in the rate multiplier output in order to produce an evenly-spaced pulse train. However, because the ramp generator RM and comparator COM combination is only able to delay the rate multiplier output signals and not to advance them, it is necessary to offset the value of the output of divider DV
by an analogue voltage which represents one whole period ("1") of the clock pulses. This is effected by summing circuit SUM.
The production of evenly-spaced output pulses is as follows. An output pulse from the rate multiplier RM
is delayed by delay DL for one clock period of Fr to allow time for the analogue integration process to take place.
This delayed pulse is then applied to the start input S
of the ramp generator RG and causes generator RG to pro-duce a ramp voltage at its output to the non-inverting (+) input of a comparator COM comprising, for example, a differential operational amplifier. The voltage pro-portional to the required delay is fed to the inverting (-) input of comparator COM from summing circuit SU~I. When the ramp voltage reaches this delay voltage, the comparator outpwt goes high and, in turn, resets the ramp generator via its input R. The synthesiser output thus consists of a ~94~;5 PHB 32.864 20 25.8.1982 very short output pulse from comparator COM. Further out-put.s from the rate multiplier are similarly delayed by the correct amount resulting in an evenly-space train of frequency Fo = nFr at the comparator output, where 0 < n /~ 1.
The summing circuit SUM, the ramp gonerator RG and comparator COM together constitute a programmable delay generator which is controlled by the compensation signal from divider DV such that the output pulses of the delay generator are respectively delayed by such an amount that the periods of occurrence are equal.
The operation of the automatic servo is closely similar to that of the servo described with reference to Figure 1, namely that the correlator M detects the sign or phase of any residual jitter in the output by correlating this jitter with a reference signal formed by the output of delay DL and uses this to control the amplitude of the compensation signal fed to the inverting input of compara-tor COM. The output of correlator M is integrated by low pass filter F and the resulting analogue signal controls the gain of gain-controlled amplifier GCA such that any residual jitter in the frequency Fo is reduced at least substantially to zero.
It is to be noted that the pulse addition and subtraction circuits PA and PS may alternatively be located in the path between rate multiplier RM and delay DL.
The compensation signal circuit may include an amplifier the gain of which is inversely proportional to the output frequency of the synthesiser. This not only en-S~
PHB 32.864 7 Z5.8.1982 sures that the level of the compensation signal is correct but also that any variation in the output signal due to large frequency changes in the output frequency o~ the synthesiser is precisely compensated for.
In addition to the reduction of the level of the sideband noise by the use of the d.c. removal circuit and analogue integrator, a very significant reduction in the level of any spurious discrete sideband signal is achieved by the above-mentioned addition and subtraction of cycles.
As referred to above, any residual imbalance in the jitter compensation circuit would give rise to a spurious sideband signal having a discrete frequency determined by the offset ~requency. The effect of adding and subtracting pulses is to introduce a perturbation signal into the system. In the lS event of any residual imbalance in the compensation circuit, the energy in the spurious discrete signal is mixed with the perturbation signal and is spread over a wide spectrum with the result that it appears as noise at a considerably lower level. The result of this double noise reduction is that the synthesiser can be used in broadcast systems, etc.
In frequency sythesisers having an automatic servo, which detects the sign or phase of any residual im-l~d/4nc~
au~ in the system and uses this imbalance to control the gain of the compensation signal or signals in such a direction as to reduce the imbalance, the imbalance sig-nals caused by the added and subtracted pulses implies that the servo receives information at a much higher minimum rate. Thus the time constant can be very considerably shortened and this makes the response of the synthesiser to changes in the required frequency far more rapid, with the result that the utility of the synthesiser is con-siderably extended.
It is not essential for the con-trol device to be arranged to add the same number of cycles as it cancels -any difference between the numbers merely represents a fre-quency offset. Preferably, however, the number of added cycles is substantially the same as the number of cancelled ~4~55 PH~ 32.864 8 25.8.1982 cycles in any given period, since substantially no fre-quency offset is then caused.
The con-trol signal output of the control device may have three states - namely a first state which causes a pulse to be cancelled~ a second (neutral) state which causes no pulse addition or cancellation, and a third state which causes a pulse to be added.
The control signal may comprise at least first and second interspersed pulse sequences, the arrangement lD being such that each pulse of the first sequence causes a cycle to be cancelled from, and each pulse in the second se-quence causes a cycle to be added to~ the frequency to be reduced. By interspersing the sequences, the instantaneous frequency of the frequency to be reduced is, at any instant, closer to its average frequency that would be the case if a long series of cancelled pulses were followed by a long series of corresponding added pulses. The minimum instan-taneous deviation from the average frequency is given if the pulses of the two sequences are arranged alternately. A
very considerable advantage accrues, however, if the two pulse sequences are interspersed and occur in a random manner. Any phase jitter energy in the output frequency caused by any residual imbalance in the compensation signals is then made completely noise-like and is spread over such a wide spec-trum that it is substantially undetectable. Sub-stantially the same spreading effect can be achieved, but in a more convenient practical m~nner, i~ the two sequences together form a pseudo-random sequence since such sequences may easily be generated in well known manner.
In order to minimise the amount of jitter re-sulting from the control signal, the latter may be in Manchester-coded form or may be a differentiated code sig-nal. In this context differentiation means converting a rising transition of a clocked input signal to a +1 output signal, a falling transition to a -1 output signal, and the lack of a transition to a O.
The synthesiser may include means for combining 1~194~S5 PHB 32.86~ 9 25.8.19~2 the outputs of the jitter and control signal compensation circuits to form a combined compensation signal. Thus only a single correction signal need be applied to the jitter correction arrangement, for example a phase modulator or a programmable delay generator. Although the principle of operation of a phase modulator in this art is usually different from that of a programmable delay generator, the effect of each for present purposes is substantially the same.
The frequency synthesiser may include a detector arranged to detect any residual jitter in the circuit after application of the combined compensation signal, and a variable gain amplifier arranged to control the amplitude of the combined compensation signal, the gain of the ampli-fier being controlled by the detector to reduce any said residual jitter. In this manner the detector and amplifier form an automatic servo, referred to above, which adjusts the amplitude of the compensation signal in dependence upon the detected residual jitter in order to minimise that jitter.
Embodiments of the invention will now be des-cribed 9 by way of example, with reference to the accom-panying drawing, of which:
Figure 1 shows a block schematic circuit diagram of a frequency synthesiser of the phase lock loop type, and Figure 2 shows a block schematic circuit diagram of a frequency synthesiser of the direct type.
Figure 1 shows a block schematic circuit diagram of a first embodiment of the invention comprising a voltage-controlled variable frequency oscillator VFO, the output of which constitutes the synthesiser output (fre-quency Fo) and is connected to one input of a pulse swallow circuit PS. The output of circuit PS is connected via a pulse adder PA to a programmable divider PD which di-vides by an adjustable number N ~ 1. The output of dividerPD is connected to a first comparison input of a phase comparator PC and also to the strobe input of a strobing 1~9~55 PHB 32.864 10 25.8.1982 circuit STR. l'he other input of circuit STR is connected to the ou$put of an offset frequency source OFS having a variable of~set frequency Fos in a range which is low re-lative to the output frequency range of the synthesiser.
For example, the synthesiser may have an output frequency range of 1.6 MHz to 30 MHz adjustable by divider PD in 1 kHz steps and the variable offset frequency source OFS
may have a range of O to 990 Hz variable in 10 Hz steps.
The source may, for example~ derive the offset frequency from a clock pulse generator CPG or from the output of ~ivider PD, the connections thereto not being shown in the Figure. Thus, for example, the source OFS may comprise a rate multiplier and a divider as shown at RM and D1 res-pectively in Figure 3 of U.~. Patent Specification 1,447,418 or may simply comprise a rate multiplier R as shown in Figure 2 of that specification. The offset frequency source may alternatively generate an offset frequency directly in response to an analogue or a digital input. There are of course many ways in which such an offset frequency may be provided - all that is required is that the range of the output frequency Fos of the source is low compared with the frequency range of the synthesiser since the con-trollable range of frequency Fos establishes the smallest frequency step of the synthesiser.
The output of strobing circuit STR is connected to the "swallow" command input of pulse swallow circuit PS
and also to the input of a d.c. removal circuit DCR via an adder ADD and a gain controlled amplifier GCA. The out-put of the circuit DCR is fed via an analogue integrator INT to the phase control input of a phase modulator PM. The clock pulse generator CPG provides pulses having a high stable repetition rate (frequency) and the frequency of these pulses is, if required, divided down in a divider DIV to provide a reference frequency Fr (e.g. 1000 p.p.s.) which is fed via the phase modulator PM to ~ second com-parison input of phase comparator PC. The output signal from comparator PC is fed to the frequency control input of oscillator VFO v a low-pass loop filter LP~.
~4~55 PHB 32.864 11 ~ 25.8~1982 The operation of the phase lock loop control circuit VFO-PS-PD-LPF-VFO is well known and is described in terms of these referenced items in the above-mentioned U K. Patent Specification 1,447,418. Briefly, the output signal of comparator PC is integrated in a low-pass filter LPF and adjusts the frequency of the oscillator VFO until the phase of the signal fed to the first comparison input of comparator PC from divider PD is identical to the phase of the signal fed to the second comparison input of the comparator PC via phase modulator PM. If the relative phase of the two input signals to comparator PC tend to differ slightly, then the output signal of comparator PC
changes accordingly in such a direction that the phase of oscillator VFO is shifted to reduce the phase difference between the two input signals to comparator PC to zero The remainder of the circuit differs from the prior art and its operation will therefore be described in more detail. Output pulses from the source OFS, having an average frequency Fos, are strobed in circuit STR
by the output pulses of divider PD to produce output pulses of a defined length. These pulses operate circuit PS in precisely the same manner as the corresponding pulses Fr in Figure 2 of said Patent Specification No.
1,447,418 and offset the output frequency Fo by Fos Thus Fos may be selected to give a very fine control of the output frequency Fo. These pulseq form a pulse signal A
which, ignoring for a moment any effect of adder ADD and amplifier GCA, is applied to the d.c. removal circuit DCR
which either removes any d.c. component in the pulse signal (e.g. by a series capacitor) or compensation for any saturation effect the d.c. may give rise to in the integrator. A particularly suitable compensation method is described in Patent Specification No. GB 2,072,241A. The resulting signal B is in-tegrated by an analogue integrator INT to produce a signal C which is used to control the phase delay generated by phase modulator PM.
As described above, the operation of the circuit 1~34~55 PH~ 32.864 12 25.8.198~
PS in response to the strobed pulse signal A causes jitter in the pulses appearing at the output of divider PD, this jitter appearing as a phase delay in the pulses each time circuit PS is caused to swallow (i.e. cancel or subtract) a pulse by the arrival of a pulse in signal A. This same pulse is used, via the circuit elements DCR and INT, to cause a corresponding phase delay in the pulse from phase modulator PM. Thus the pulse from modulator PM to compa-rator PC is delayed to substantially the same extent as the jitter delay in the corresponding pulse from divider PD. Thus the effects of jit-ter on the output frequency Fo of oscillator ~FO are at least very substantially reduced.
In effect, the signal C has a value which pre-dicts any p~ase delay resulting from jitter and compen-lS sates for this delay accordingly. As would be expected,as the offset frequency Fos is increased, so the amount of jitter per unit of time increases and the value of the jitter-compensating signal C increases The average value of the signal B is zero, due to the removal of the d.c.
content, and hence the signal C is a function of the amount of jitter caused by the pulse swallowing technique.
The function of gain-controlled amplifier GCA will be described below.
Whilst the amplifier GCA is shown preceding the removal circuit DCR, it will be evident to those skilled in the art that it may be located anywhere in the series circuit ADD-DCR-INT-P~.
From the above, it can be appreciated that the phase correction signals are derived in a very simple manner directly from the phase jitter actually caused by the offset frequency source OFS. Further, the correction steps are derived by analogue integration - in contra-distinction to known systems which are based on digital means - with the result that the correction signal does not suffer from the discontinuities which can be intro-duced by inaccuracies of practical digital-to-analogue converters which occur in known phase prediction methods.
1~4~55 PHB 32.864 13 25 8.1~82 Thus a reduction in the system noise is achieved.
The circuit further includes a control device CD fed with synchronising pulses from the output of di-vider PD. Circuit blocks PS, PA, and PD form a frequency control circuit to which control device CD is connected in order to provide a control signal thereto comprising two interspersed sequences of pulses P1 and P2. Each P1 pulse causes adder PA to add a pulse (cycle) to the frequency Fo and each P2 pulse causes pulse swallow circuit PS to cancel a pulse. Preferably a substantially equal number of P1 and P2 pulses are generated such that, over a time average, there is no net phase error introduced as a result of the control signal and so the process generates no fre-quency error in the system.
Control device CD also provides a combined con-trol signal to an input of adder ADD, the combined signal comprising a +1 pulse for each P1 pulse and a -1 pulse for each P2 pulse. The amplitude of these pulses is adjusted by the gain-controlled amplifier GCA and, aftcr d.c. re-moval by circuit DCR and integration by integrator INT, form a compensation signal which controls phase modulator PM in such a manner that the effects of the jitter at the output of divider PD are precisely matched by a corres-ponding jitter in the output of phase modulator P~l.
As explained above, in a corresponding frequency synthesiser not provided with control device CD, pulse adder PA, and adder ADD, the jitter information in signal B can have a relatively low frequency, for example 10 Hz, and as a result a time constant has to be provided in the compensation signal path of one-tenth of a second or greater. Thus the settling time of the synthesiser to a change in required frequency Fo is one-tenth of a second, which may be too long for some applications. The provision of control device CD, however, causes a "perturbation" sig-nal to be added to the compensation signal by adder ADDwith the result that the information in the compensation signal has a considerably higher repetition rate. The 1~94~55 P~B 32.864 14 25.8.1982 respo-lse time of the compensation signal pa-th can there-fore be made very considerably shorter, thereby consi-derably extending the possible fields of use of the syn-thesiser.
Another advantage is that the energy in any spurious discrete sideband signal which may appear in the output frequency Fo due to any imbalance in the compen-sation circuit is spread over a wide frequency spectrum by the residual perturbation signal appearing in the out-1D put as a result of the same imbalance. In this manner any said imbalance will only produce noise in the output signal at such a low level that it is relatively undetectable.
As is well known, the pulse swallow circuit PS
might comprise a so-called n/(n+1) prescaler which di-vides by n (e.g. 10) in the absence of a pulse in signal Aand by (n+1) if a control pulse is present. In a similar manner, pulse adding circuit PA may comprise an n/(n-1) prescaler. Alternatively1 the pulse adder PA may comprise a divide-by-two circuit, for example forming the first stage of divider PD, which normally divides by 2 but which divides by 1 for each P1 pulse. Alternatively the functions of circuits PS, PA, and PD can be performed by a modulo-(n-1)/n/(n+1) divider as described in the specification of GB Patent Application Z,074,421A.
In principle, the +1 and -1 pulses could be interspersed with 0 periods in which the effective di-vision ratio of the divider arrangement is n1, but then the compensation signal fed to adder ADD would include information which apparently serves no useful purpose. How-ever in order to improve the noise-like nature of the com-pensation signal it may be advantageous to include a number of 0 periods.
The control signal from control device CD which would give the maximum rate of information would be alternate +1 and -1 pulses occurring at the comparator fre-quency Fr, giving a square wave of frequency Fr/~. The com-bined signal is, however, preferably derived from or forms ~9~55 PHB 32.864 15 25.8.1982 a random pseudo-random binary sequence which i9 then Manchester-coded (encoded in pairs of (~ 1) or (-1, +1) depending upon the presence of a 0 or 1 respectively in the sequence) or is differentiated. In some circumstances it may be advantageous to differenti~te the Manchester-coded signal. The random sequence has to be generated at a maxi-mum rate of Fr and if it has a total period of T then its spectrum will be noise-like but with discrete components spaced by frequency T . If T is less than about 100 mS for a typical communication synthesiser, the spectrum can be considered as pure noise. In this case any energy in the output frequency resulting f`rom imbalance in the compen-sation system will not appear as a discrete signal but will be spread out as noise spectrum signal. In this manner, the total imbalance energy can be up to 30 dB greater than the maximum imbalance energy that would be tolerable with-out this spreading action and yet still be inaudible. The following example will serve to illustrate this.
The frequency synthesiser may be used in c~n-nection with a multi-channel communication system having, for example, a channel spacing of 12 2 kHz. If the synthe-siser frequency step is 100 kHz and, say, the fractional offset frequency is 122 kHz, than a spurious 122 kHz signal is produced which will be in the adjacent channel. Without special precautions, this signal would be 30 to 50 dB down with respect to the channel carrier but the CITT specifi-cation requires it to be at least 90 dB down. This is readily achievable by the provision of the control signal having a random or pseudo-random distribution.
If a pseudo-random binary sequence is used which is generated in well known manner from an N-stage shift re-gister with feedback, 2 -1 different codes are generated.
Every code is complemented by another particular code e~cept the all-1~s code since there is no complementary all-O's code. Thus there is a small imbalance once in every com-plete sequence of 2 -1 codes. If the sequence is generated, for example by a shift register having N = 17 stages ~94~55 PHB 32.864 16 25.8.1982 clocked by a 1 MXz clock pulse, the total cycle length is 2 7-1 = 131071 bits, i.e. a rate of 7.63 Hz. Thus there will be a very small imbalance at this rate giving a small offset in the final frequency which, in many cases, will be acceptable. Alternatively, in this case, the imbalance may be eli~inated entirely by the use of the Manchester code or a dif~erentiated code.
If, for reasons of imperfect compensation, some residual energy from the pseudo-random binary sequence causes phase jitter, the sideband components of this jitter will be spaced at 7.63 Hz and9 at that frequency spacing, the sideband energy becomes indistinguishable from white noise and is therefore substantially inaudible.
In the circuit so far described - that is without the provision of an automatic servo circuit shown in broken lines and including a correlator M - the gain of the gain-controlled amplifier GCA may be controlled, in a mamler not shown, to be an inverse function of the fre-quency Fo. The reason for this is as follows.
In effect, the signal C has a value which pre-dicts any phase delay resulting from jitter and compen sates for this delay accordingly, As would be expected, as the offset frequency Fos is increased, so the amount of jitter per unit of time increases and the value of the Z5 jitter-compensating signal C increases. The average value of the signal B is zero, due to the removal of the d.c.
content, and hence the signal C is a function of the amount of jitter caused by the pulse swallowing technique. How-ever the voltage step out of the phase comparator PC when a pulse is subtracted at the input to divider PD is pro-portional to the length of the pulse (i.e. one cycle of the VF0 output frequency) and is therefore inversely pro-portional to the frequency Fo. Thus, in the above-mentioned case of a frequency synthesiser having a range of 1.6 ~IHz to 30 ~Hz, the amplitude of the signals dealt with by the jitter compensation circuit can vary if the synthesiser is switched from one end of its output frequency range to the ~L94~55 PHB 32.864 17 25.8.1982 other. This can cause inaccuracies in the jitter correct-ion signal C and, to compensate for this, the gain-con-trolled amplifier GCA included in the correction signalcircuit may have its gain controlled by a period-to-analogue converter having the frequency Fo fed to its input. In this way, a very precise and accurate compensation for the effects of jitter is provided over the whole frequency range.
Preferably, however, the amplifier GCA forms part of an automatic servo circuit, shown with broken line connections, which further includes a correlator M. The signal input of correlator M is connected to the output of phase comparator PC and the reference input is connected to the output of adder ADD. The correlation signal output of correlator M controls the gain of amplifier GCA. In this manner, correlator M detects any residual jitter appearing at the output of phase comparator PC and varies the gain of amplifier GCA - and hence the amplitude of the correction signal C - to eliminate any residual jitter automatically.
Whilst the ampli~ier GCA is shown preceding the removal circuit DCR, it will be evident to those skilled in the art that it may be located anywhere in the series circuit ADD-DCR-INT-PM.
From the above, it can be appreciated that the phase correction signals are derived in a very simple manner directly from the phase jitter actually in the off-set frequency source OFS. Further, the correctîon steps are derived by analogue means - in contradistinction to known systems which are based on digital means - with the res-ult that the correction signal does not suffer from the discontinuities which can be introduced by inaccuracies of practical digital-to-analogue converters which occur in known phase prediction methods.
In modern frequency synthesisers, there is a requirement for closely-spaced output frequencies and this results in large division ratios and small values of Fos for a given output frequency. This may result in unaccept~
~94~55 P~IB 32.864 18 25.8.1982 able performance in terms of oubput noise and switching speed. The frequency synthesiser according to the invent-iont however, allows small frequency increments whilst at the same time having the noise and switching speed per-formance of a system with a considerably higher referencefrequency Fr.
Figure 2 shows a frequency synthesiser of the direct type, that is to say one in which a variable number of pulses from a reference frequency generator is cancelled in order to provide the required (lower) output frequency.
The synthesiser comprises, in sequence, a stable frequency source comprising a clock pulse generator CPG, a programmable divider DIV (if required) whose output com-prises pulses having a repetition rate (frequency) Fr, a pulse adder PA, a pulse subtractor PS~ a rate multiplier R~l, a delay DL, a ramp generator RG having start and reset inputs S and R respectively, and an analogue comparator COM the output of which constitutes the output frequency Fo of the synthesiser. The compensation signal circuit com-prises a d c~ removal circuit DCR, an analogue integratorINT, a divider DV, a gain-controlled amplifier GCA, and a summing circuit SUM. The multiplying factor of rate multiplier RM is controlled by an input signal n which also determines the division factor of divider DV. It further comprises a correlator M, a low pass filter F and a control device CD. Ths correlator M, filter F, and gain-controlled amplifier GCA form an optional automatic servo.
Ignoring for the moment the operation of the automatic servo M.F.GCA and assuming that the gain of amplifier GCA is unity, ~he operation of the circuit is as follows.
The operation of control device CD, pulse adder PA, and pulse subtractor PS is the same as that described with reference to Figure 1; namely to provide a signal at the input to rate multiplier RM comprising the reference frequency Fr perturbed by added and subtracted cycles (pulses) wnder the control of device CD. Rate multiplier RM
1: L94:~55 PHB 32.864 19 25 8.1982 produces pulses at its output at an average rate given by Frm = nFr where O < n ~ 1 and assuming that the number of pulses added by the arrangement CD-PA-PS is the same over a gi~en period as the number of pulses it subtracts.
These output pulses are synchronised with the input pulses to rate multiplier RM and the extra jitter caused by the added and subtracted pulses appears at the input to d.c.
removal circuit DCR together with the jitter caused by -the rate multiplier RM. The output pulses of circuit DCR are integrated by analogue integrator INT and the integrated signal is then divided by the rate multiplier control sig-nal n in divider DV which may comprise in practice a multiplying digital-to-analogue converter.
The output analogue signal of divider DV is now proportional to the time advances required in the rate multiplier output in order to produce an evenly-spaced pulse train. However, because the ramp generator RM and comparator COM combination is only able to delay the rate multiplier output signals and not to advance them, it is necessary to offset the value of the output of divider DV
by an analogue voltage which represents one whole period ("1") of the clock pulses. This is effected by summing circuit SUM.
The production of evenly-spaced output pulses is as follows. An output pulse from the rate multiplier RM
is delayed by delay DL for one clock period of Fr to allow time for the analogue integration process to take place.
This delayed pulse is then applied to the start input S
of the ramp generator RG and causes generator RG to pro-duce a ramp voltage at its output to the non-inverting (+) input of a comparator COM comprising, for example, a differential operational amplifier. The voltage pro-portional to the required delay is fed to the inverting (-) input of comparator COM from summing circuit SU~I. When the ramp voltage reaches this delay voltage, the comparator outpwt goes high and, in turn, resets the ramp generator via its input R. The synthesiser output thus consists of a ~94~;5 PHB 32.864 20 25.8.1982 very short output pulse from comparator COM. Further out-put.s from the rate multiplier are similarly delayed by the correct amount resulting in an evenly-space train of frequency Fo = nFr at the comparator output, where 0 < n /~ 1.
The summing circuit SUM, the ramp gonerator RG and comparator COM together constitute a programmable delay generator which is controlled by the compensation signal from divider DV such that the output pulses of the delay generator are respectively delayed by such an amount that the periods of occurrence are equal.
The operation of the automatic servo is closely similar to that of the servo described with reference to Figure 1, namely that the correlator M detects the sign or phase of any residual jitter in the output by correlating this jitter with a reference signal formed by the output of delay DL and uses this to control the amplitude of the compensation signal fed to the inverting input of compara-tor COM. The output of correlator M is integrated by low pass filter F and the resulting analogue signal controls the gain of gain-controlled amplifier GCA such that any residual jitter in the frequency Fo is reduced at least substantially to zero.
It is to be noted that the pulse addition and subtraction circuits PA and PS may alternatively be located in the path between rate multiplier RM and delay DL.
Claims (8)
PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A frequency synthesiser comprising a reference frequency generator, a frequency control circuit which includes a variable frequency reduction means comprising a cycle cancellation circuit which is arranged to cancel a cycle of the frequency to be reduced by the reduction means for each input pulse to said circuit from a pulse source, and a jitter compensation circuit connected to the frequency control circuit, the output signal of the jitter compensation signal circuit being arranged to compensate, at least partly, for any jitter in the period of the out-put frequency of the synthesiser that would otherwise be caused as a result of each cancelled cycle, characterised in that the jitter compensation signal circuit comprises a d.c. removal circuit followed by an analogue integrator, and in that the synthesiser further includes a control device the control signal output of which is arranged to cause the frequency control circuit to cancel further cycles from, and also to add cycles to, the said fre-quency to be reduced in a given sequence, and a control signal compensation circuit which is connected to the control device and is arranged to compensate for any jitter in the output frequency of the synthesiser that would otherwise be caused by the control signal.
2. A frequency synthesiser as claimed in Claim 1, wherein the jitter compensation circuit derives the jitter compensation signal directly from a pulse train in the synthesiser which itself contains jitter which would otherwise cause said jitter in the period of the output frequency.
3. A frequency synthesiser as claimed in Claim 2, wherein the input of the compensation signal circuit is connected to the input or the output of the cycle can-cellation circuit.
4. A frequency synthesiser as claimed in Claim 1, 2 or 3, wherein the number of cycles added by the control signal in a given period is substantially the same as the number of cycles cancelled by the control signal in that period.
5. A frequency synthesiser as claimed in Claim 1, wherein the given sequence comprises at least first and second interspersed pulse sequences, the arrangement being such that each pulse of the first sequence causes a cycle to be cancelled from and each pulse of the second sequence causes a cycle to be added to, the frequency to be reduced.
6. A frequency synthesiser as claimed in Claim 5, wherein the two sequences together form a pseudo-random sequence.
7. A frequency synthesiser as claimed in Claim 1, 2 or 5, including means for combining the outputs of the jitter compensation signal circuit and control signal compensation circuit to form a combined compensation sig-nal.
8. A frequency synthesiser as claimed in Claim 1, 2 or 5, including a detector arranged to detect any resi-dual jitter in the circuit after the application of said combined compensation signal, and a variable gain ampli-fier arranged to control the amplitude of the combined compensation signal, the gain of the amplifier being con-trolled by the detector to reduce any said residual jitter.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8208096 | 1982-03-19 | ||
| GB08208096A GB2117199A (en) | 1982-03-19 | 1982-03-19 | Frequency synthesiser |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1194155A true CA1194155A (en) | 1985-09-24 |
Family
ID=10529132
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000423837A Expired CA1194155A (en) | 1982-03-19 | 1983-03-17 | Frequency synthesiser |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4746870A (en) |
| EP (1) | EP0089723B1 (en) |
| JP (1) | JPS58170227A (en) |
| AU (1) | AU566522B2 (en) |
| CA (1) | CA1194155A (en) |
| DE (1) | DE3374506D1 (en) |
| GB (1) | GB2117199A (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2150775A (en) * | 1983-12-02 | 1985-07-03 | Plessey Co Plc | Frequency synthesiser |
| KR910001675B1 (en) * | 1988-05-27 | 1991-03-18 | 삼성전자 주식회사 | Dtmf and high-lowtone generating circuit |
| US5097219A (en) * | 1988-12-15 | 1992-03-17 | Mitsubishi Denki Kabushiki Kaisha | Pll for controlling frequency deviation of a variable frequency oscillator |
| GB2228840B (en) * | 1989-03-04 | 1993-02-10 | Racal Dana Instr Ltd | Frequency synthesisers |
| EP0630129A2 (en) * | 1993-06-09 | 1994-12-21 | Alcatel SEL Aktiengesellschaft | Method for generating a synchronised clock signal with a circuit for an adjustable oscillator |
| JPH07245603A (en) * | 1994-01-11 | 1995-09-19 | Fujitsu Ltd | Jitter suppression control method and its circuit |
| US5692023A (en) * | 1994-11-04 | 1997-11-25 | Lsi Logic Corporation | Phase locked loop including distributed phase correction pulses for reducing output ripple |
| GB2310331B (en) * | 1996-02-15 | 2000-06-28 | Surrey University Of | Phase noise reduction circuits |
| US6127859A (en) * | 1999-03-26 | 2000-10-03 | Tritech Microelectronics Ltd. | All-digital minimal jitter frequency synthesizer incorporating an improved pulse stripping method to reduce spurious tones |
| US6470042B1 (en) * | 1999-11-18 | 2002-10-22 | Vtech Communications, Ltd. | Phase-locked loop controller for a frequency hopping radio |
| US7027424B1 (en) | 2000-05-24 | 2006-04-11 | Vtech Communications, Ltd. | Method for avoiding interference in a digital communication system |
| GB0416627D0 (en) * | 2004-07-26 | 2004-08-25 | Toric Ltd | Anti-jitter circuits |
| DE102004047266A1 (en) * | 2004-09-24 | 2006-04-06 | Hauni Maschinenbau Ag | Device for transferring rod-shaped articles |
| US7693488B2 (en) * | 2004-09-30 | 2010-04-06 | Vtech Telecommunications Limited | System and method for asymmetric enhanced mode operation in a digital communication system |
| US7362107B2 (en) * | 2005-11-08 | 2008-04-22 | Mediatek Inc. | Systems and methods for automatically eliminating imbalance between signals |
| US8451701B2 (en) * | 2010-01-15 | 2013-05-28 | Laufer Teknik, Inc. | System and method for suppressing jitter |
| US8995243B2 (en) | 2010-01-15 | 2015-03-31 | Laufer Teknik, Inc. | System and method for suppressing jitter in digital data signals including image, video and audio data signals |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1447418A (en) * | 1974-03-29 | 1976-08-25 | Mullard Ltd | Frequency synthesiser |
| US3976945A (en) * | 1975-09-05 | 1976-08-24 | Hewlett-Packard Company | Frequency synthesizer |
| GB2026268B (en) * | 1978-07-22 | 1982-07-28 | Racal Communcations Equipment | Frequency synthesizers |
| DE2926587C2 (en) * | 1979-06-30 | 1983-12-01 | Felten & Guilleaume Fernmeldeanlagen GmbH, 8500 Nürnberg | Frequency synthesis arrangement |
| GB2062315B (en) * | 1979-10-30 | 1983-06-08 | Philips Electronic Associated | Frequency divider |
| GB2068185B (en) * | 1980-01-21 | 1983-06-22 | Philips Electronic Associated | Frequency synthesiser of the phase lock loop type |
| GB2074421B (en) * | 1980-04-16 | 1983-12-07 | Philips Electronic Associated | Frequency modulator circuit arrangement |
| DE3025326C2 (en) * | 1980-07-04 | 1983-10-27 | Siemens AG, 1000 Berlin und 8000 München | Phase tracking control loop based on the DLL principle |
| US4410954A (en) * | 1980-10-08 | 1983-10-18 | Rockwell International Corporation | Digital frequency synthesizer with random jittering for reducing discrete spectral spurs |
| GB2117198A (en) * | 1982-03-19 | 1983-10-05 | Philips Electronic Associated | Frequency synthesiser |
| GB2117197A (en) * | 1982-03-19 | 1983-10-05 | Philips Electronic Associated | Frequency synthesiser |
-
1982
- 1982-03-19 GB GB08208096A patent/GB2117199A/en not_active Withdrawn
-
1983
- 1983-03-17 EP EP83200373A patent/EP0089723B1/en not_active Expired
- 1983-03-17 DE DE8383200373T patent/DE3374506D1/en not_active Expired
- 1983-03-17 AU AU12525/83A patent/AU566522B2/en not_active Ceased
- 1983-03-17 CA CA000423837A patent/CA1194155A/en not_active Expired
- 1983-03-19 JP JP58045343A patent/JPS58170227A/en active Pending
-
1987
- 1987-06-23 US US07/065,631 patent/US4746870A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE3374506D1 (en) | 1987-12-17 |
| US4746870A (en) | 1988-05-24 |
| EP0089723B1 (en) | 1987-11-11 |
| EP0089723A1 (en) | 1983-09-28 |
| JPS58170227A (en) | 1983-10-06 |
| AU566522B2 (en) | 1987-10-22 |
| AU1252583A (en) | 1983-09-22 |
| GB2117199A (en) | 1983-10-05 |
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