CA1179071A

CA1179071A - Semiconductor device

Info

Publication number: CA1179071A
Application number: CA000405274A
Authority: CA
Inventors: Tadashi Fukuzawa; Eizaburo Yamada; Michiharu Nakamura
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1981-06-17
Filing date: 1982-06-16
Publication date: 1984-12-04
Also published as: EP0067721B1; US5001536A; EP0067721A3; EP0067721A2; DE3279663D1

Abstract

Abstract of the Disclosure A semiconductor device has a first semiconductor layer that contains substantially no impurity and a second semi-conductor layer that has a band gap greater than that of the first semiconductor layer and contains an impurity.
An interface between these layers forms a heterojunction.
At least one pair of electrodes are electronically connected with the first semiconductor layer, and the arrangement controls carriers developing at the heterojunction interface.
The invention is characterized in that the first semi-conductor layer is a Ge layer, while the second semiconductor layer is a group III - V compound semiconductor layer. The result is a product with improved hole mobility.

Description

~ ~7~37~

SEMICONDUCTOR DEVICE

This invention relates to semiconductor devices with enhanced hale mobility.
A complementary field effect transistor that employs Si as a semiconductor material uses a p-type channel and an n-type channel, and utilizes the fact that the characteristics of currents switched by the gates thereof are the reverse of each other. Such an arrangement has the advantage that a signal can be amplified without requiring any considerable current to flow through field effect transistors (hereinbelow, abbreviated to "FETs") and that a logic operation is possible with very low power consumption.
Most of the present-day ICs (integrated circuits) in which logic circuits are built are semiconductor devices of this type. The operating speed of the element, however, is determined by the value of the lower one of the hole and electron mobilities (respectively denoted by ~h and ~e).
In the case of Si, ~h = 480 cm2V lsec determines the speed of the element. The semiconductor materlal GaAs is higher than Si in ~e and is considered the preferred material for ultra high speed devices of the coming generation. Since, however, the hole mobility l~h) of this material is only 300 cm2 V lsec 1, i.e. lower than that of Si, the advantage of the high electron mobility cannot be fully exploited in a semiconductor device of the complement ary type. Accordingly, this material cannot be fully utilized for the semiconductor devices that will form the mainstream of ICs and LSIs (large scale integrated circuits).
High speed switching elements utilizing the larger electron mobility of GaAs have heretofore been proposed, as exemplified by T. Mimura et al. "Japanese Journal of Applied Physics" vol. 19, L 225, 1980.
The presen-t invention provides a multilayered-structure semiconductor device having a high hole mobility that can also generate sufficient signal current.
According to the present invention~a semiconductor device capable of fast operation and exhibiting very low power consumption can be realized using a group III - V compound semiconductor material.
The fundamental technical idea of the present invention consists in utilizing as the carrier of a signal, a two-dimensional hole gas which develops at the hetero-structure interface between a group III - V semiconductor layer heavily doped to p-type and a Ge layer of very low impurity concentrationO In this way, a semiconductor device having high hole mobility can be realized.
More specifically, the invention consists of a semi-conductor device having at least a first semiconductor layer containing substantially no impurity, a second semiconductor layer having a band gap greater than that of the first semi-conductor layer and containing an impurity, an interface between the first and second semiconductor layers forming a heterojunction, at least one pair of electrodes electronically connected with the first semiconductor layer, and means to control carriers developing at the hetero-junction interface; characterized in that the first semi-conductor layer is a Ge layer, while the second semiconductorlayer is a group III - V compound semiconductor layer.
As typical semiconductor materials, being binary, ternary or quaternary solid solutions among the group III -V compound semiconductors, the following materials can be mentioned:
GaAs, Ga1 Al As, AlxInl_xP, AlxInl_x ~ x l-x AlAs Sb , Ga Inl xP, GaxInl_xAS~ Alx l-x y 1-y, x nl-xASyPl_y~ GaxInl xAsySbl ~79~

Above all, GaAs is a practically useful material. It is a compound semiconductor of the binary system, and is easy of manufacture.
In the drawings:
Figure 1 is a schematic energy band diagram at the junction between a p-type GaAs layer and an undoped Ge layer;
Figure 2 is a schematic energy band diagram at the junction between an n-type GaAs layer and an undoped Ge layer;
Figures 3, 4, 5, 6 and 8 are sectional views of devices each showing an embodiment of the present invention;
Figure 7 is a schematic energy band diagram of a double hetero-structure made of Ge and GaAs;
Figure 9 is a sectional view of portions of a complementary semiconductor device constructed on the principle of the present invention;
Figure 10 is a diagram showing an equivalent circuit of the semiconductor device in Figure 9; and Figure 11 is a schematic energy band diagram of a stacked layer of n~GaAlAs - GaAs - p-GaAlAs.
Detailed Description of the Preferred Embodiments The group III - V semiconductor layer and the Ge layer are grown by, for example, the molecular beam epitaxial method (hereinbelow, abbreviated to the "MBE method"). They are lattice-matched to an extent sufficient in practice.
Typical examples of materials of the former layer are as mentioned above. As these materials, there are selected semiconductor materials that belong to group III - V binary, ternary or quaternary solid solutions and have lattice constants of 5.658 -~ 0.05 A and energy band gaps of values greater than 0.66 eV.
In order to prevent lattice mismatching of the compound semiconductors with Ge, the compositions are usuallv selected within the following ranges of mole fractions:
Gal XAlxAs ( O < x < 1 ) AlxInl xP (0.4 < x < 0.6) ~L~L79~)7~L

xInl-xAS (O . 9 < x < 1) GaASxsbl-x ( O . 9 < x < 1) x l-x ( O . 9 < x < 1 ) GaxInl xP (0.4 < x < 0.6) 5GaxInl_xAs (0.9 < x < 1) The layers of these semiconductor materials being group III - V ternary or qua~ernary solid solutions are doped into the p-type at impurity concentrations of the order of 5 x 1016 /cm3 - 2 x 1013 /cm3. The thickness of each p-type semiconductor layer is set at approximately 300 A - 3000 A.
The density of holes is basically determined by the impurity concentration of the p-type semiconductor layer and the thickness thereof.
As dopants, there are used Be, Zn, Cd etc.
The Ge layer is usually left undoped or naturally doped.
Be, Al, Ga, In etc. are considered as impurities in the Ge layer, and are usually at or below l x 10l5 /cm3. More preferably, the impurity concentration is made 1 x 1014 /cm3 or less. The thickness of the Ge layer is made at least 500 A. It is set, in general, within a range of 500 A - 3000 A, and more preferably 500 A - lO00 A.
Although the Ge layer may well be still thicker, it need not be thickened unnecessarily.
Hereunder, the present invention will be described by taking GaAs as the typical example of the group III - V
compound semiconductor materials. Needless to say, however, similar operations can be effected with the other group III -V compound semiconductor materials.
The GaAs layer is doped into p-type at an impurity concentration of the order of 5 x 10l6 /cm3 - 2 x 10l8 /cm3.
The thickness of the p-type GaAs layer is set at approximately 300 A - 3000 A. The density of holes is basically determined by the impurity concentration of the GaAs layer and the thickness thereof.

:

Figure 1 shows the energy band diagram of a multi-layered, p-type, GaAs-undoped Ge structure. In addition, Figure 2 shows the energy band diagram of a mu]tilayered, n-type,GaAs-undoped Ge structure.
In Figures 1 and 2, numerals 1 and 1' designate the vacuum levels of GaAs, numeral 2 the vacuum level of Ge, numerals 3 and 3' the bottom parts of the conduction bands of GaAs numeral 4 the bottom part of the conduction band of Ge, numeral 5 the Fermi level, numerals 6 and 6' the top parts of the valence bands of GaAs, numeral 7 the top part of the valence band of Ge, and symbol ~E the gap of the valence band, which is 0.69 eV in this example. Numeral 9 indicates the gap ~E of the conduction band, which is 0.06 eV in this example.
Among the impurity atoms with which the p-GaAs layer has been doped, those neighboring the interface between the p-GaAs layer and the Ge layer transfer holes into the Ge layer of lower energy, so that the Ge layer can have a sufficient hole density (Nh) in spite of scarcely possessing any ionized impurity atoms (NI) in itself.
The density of holes required for conduction can thus be attained without scattering by the ionized impurity.
More preferably in practical use, an undoped GaAs layer that is about 20 - 70 A thick is disposed at the interface be-tween the p-GaAs layer and the Ge layer in order to avoid lowering of the mobility of holes attributed to the fact that the holes accumulated in the spike-like carrier profile of the valence band at the interface between the p-GaAs layer and the ~ndoped Ge layer are subjected to the Coulomb scattering of ionized impurity atoms in the p-GaAs layer.
This measure is also effective to prevent ions from mixing from the p-GaAs layer into the Ge layer.
When keeping an element of the above construction at a low temperature, holes having a high hole mobility exist in the spike-like carrier profile 10 of the valence band at a sufficient concentration without the freezing of carriers, unlike the situation when cooling p-type Ge alone.

~ ~9 7~07~

The two-dimensional hole gas in such state is utilized as the carriers of a signal. By way of example, ohmic contacts with the two-dimensional hole gas existing in the portion 10 are provided in two places and are respectively used for a source and a drain, and a gate is disposed there-between so as to control the flow of the holes, whereby a semiconductor device of ~ery high carrier mobility can be realized. Such structure is applicable to the channel region of a field effect transistor.
Embodiment 1:
Figure 3 is a sectional view of a device showing an embodiment of the present invention. It is an example of a Schottky type field effect transistor. On a semi-insulating Ge substrate 11 (impurity concentration: NA ~ ND
~ 2 x 1014 /cm3), a single-crystal layer 12 of undoped Ge is formed. As stated before, it is made at least 300 A
o o thick. In general, it is made 300 A - 3000 A thick. It is formed by the molecular beam epitaxial method. In an example, the front surface of the substrate was the (110) plane, the substrate temperature was 410C, and the vapor deposition rate was 10 A/minute.
Subsequently, a p-type GaAs layer 14 is formed by raising the substrate temperature to 500C - 600C and employing Be as an impurity. The thickness of the p-type GaAs layer 14 is 300 A, and the impurity concentration is 1 x 1013 /cm3. Pt is evaporated to a thickness of about 3000 A without taking the sample substrate out of the growth chamber of a molecular beam epitaxial growth equipment.
The Pt layer other than a part to construct a Schottky gate 16 is remo~ed. Conventional ion milling may be resorted to. Impurity regions 19, 20 are formed to under-lie ohmic electrodes by the use of ion implantation employing Be. The impurity concentration is 1 x 101 /cm . The regions implanted with the Be ions are so deep as to reach the Ge layer 12. Ohmic electrodes 15 and 17 are formed on the Be ion implanted regions. The material of the ohmic electrodes may be, for example, a stacked layer consisting of 0.03 ~m ~ ~907~

of Cr, 0.03 ~m of Ti and 0.5 ~m of Au. An insulating layer 18 is disposed between the respective elec-trodes.
The foregoing structure in which a thin, undoped GaAs layer 13 is disposed between the Ge layer 12 and the p-type GaAs layer 14, is as shown in Figure 4. This structure may be constructed in such a way that, after the undoped Ge layer 12 has been formed on the semi-insulating Ge substrate 11 by the molecular beam epitaxial method, the GaAs layer 13 is grown about 50 A while the shutter of the vaporization source of Be to be used as the impurity is held closed, the p-type GaAs layer 14 being subsequently formed after opening the shutter of the Be vaporization source. The other manufacturing steps are as explained in connection with Figure 3.
In the present embodiment, the interface of the hetero-junction between the GaAs layer and the Ge layer produces an abrupt gap in the valence band, in such a manner that Be (being the impurity) does not diffuse into Ge owing to the presence of the undoped GaAs layer 50 A thick. The holes supplied from the GaAs side into Ge and the ionized impurity form a curve in the band structure, and the two dimensional hole gas is accumulated in the spike-like carrier profile 10 of the band structure. The band structure diagram illustrative of this situation is shown in Figure 1.
The ohmic electrode 15 and the two~dimensional hole gas are connected by the P region that is formed by the Be ion implantation. In an example, a device having a gate length of 0.5 ~m was cooled to 77K, to reduce scattering attributed to lattices. The channel portion where the holes are conducted is the spike-like carrier profile 10, and since no impurity exists, the impurity scattering is also little. When 0.5 V was applied across the source and the drain, a transconductance of 300 ms/mm was attained.
This semiconductor device of the present embodiment uses the Schottky gate in contact with p-GaAs, and achieves an excellent effect when operated at a low temperature.

7a Even if the materials listed in Table 1 are used instead of GaAs for the semiconductor layer 14, semi-conductor devices of the same sort can be fabricated.
Table 1 Group III - V ternary or quaternary Mole fraction solid solu.tion.
_ _ _ _ _ . . _ . _ l_xAlxAs x = 0.1

2 AlxInl_xP x = 0.5

3 GaxInl xP x = 0.5 10 4 AlxInl xAs x = 0.98 x bl-x x = 0.99 6 AlASxsbl_x x = 0.96 7 GaxInl xAs x = 0.97 8 AlxGal_xAsysbl-y x = 0.3 y = 0.95 15 9 x l-x y l-y x - 0 822 Ga In As Sb x l-x y l-y y = O.99 Embodiment 2:
.
This is an example employing a film of an oxide of GaAlAs as a gate electrode portion, and will be described with reference to Figure 5.
As explained in Embodiment 1, an undoped Ge layer 12, an undoped GaAs layer 13 and a p-type GaAs layer 14 are grown on a semi-insulating Ge substrate 11 by the molecular beam epitaxial method. Subsequently, while GaAlAs (for example, GaO 7Alo 3As) is being grown, oxygen (2) gas is introduced into a molecular beam epitaxial growth equipment (abbreviated to the "MBE equipmen-t") so as to grow a GaAlAs oxide film 19 to a thickness of 100 A. Ti and W are evaporated in vacuum, the Ti-W, in parts other than a gate portion 20, are removed, Be ions are further implanted at 30 kV to a depth of about 500 A by employing the gate ~7~07~
g portion as a mask, and the resultant substrate is sub-sequently annealed at 600C for 20 minutes. Thus, a ~
semiconductor region 18, implanted with the Be ions, is formed. Ohmic electrodes 15 and 17 are formed on the P
semiconductor region 18. Using the interface between the undoped Ge layer and GaAs layer as a channel region, fast operation is possible.
By employing any of the foregoing ternary or quaternary solid solutions of group III - ~, a similar construction can be realized as ~he p-type semiconductor layer 14.
Embodiment 3-This is an example employing a GaAs substrate, and willbe described with reference to Fi~gure 6 and 7.
A semi-insulating GaAs substrate 21 (face orientation:
(110)) is lapped by the mechanochemical method, and is further etched with an etchant consisting of H2SO4 : H2O2:
H2O at a volumetric ratio of 3 : 1 : 1. Thereafter, the substrate is cleaned by Ar ions at 750 eV in the sample preparing chamber of an MBE equipment. The substrate temperature is set at 575C. Further, after shutting off the ion source of the Ar ions, annealing is carried out at the same temperature. The GaAs substrate is shifted into a crystal growth chamber and has its temperature set within a range of 500 - 600C~ whereupon an undoped GaAs layer 22 (500 A thick) is crystal-grown at a rate of 5 - 30 A/min.
Subsequently, the substrate temperature is fixed within a range of 350 - 525C, to grow an undoped Ge layer 12 to a thickness of 500 A. Subsequently, the substrate temperature is fixed again to 500 - 600 C, to grow an undoped GaAs layer 13 to a thickness of 40 A. Thereafter, Be used as a p--type dopant and the molecular beam of GaAs are simultaneously thrown onto the crystal so as to grow a p-type GaAs (p = 1 x 10 /cm3) layer 14 to 500 A. An energy band structure diagram of the stacked structure in this case is shown in Figure 7. In Figure 7, the very thin, undoped GaAs layer 13 is omitted, because it does not affect the ~7~6~7~

fundamental operation. Numeral 27 indicates the bottom part of a conduction band, numeral 28 the Fermi level, and numeral 29 the top part of a valence band. Shown at numeral 31 is the spike-like carrier profile of the valence band. Basically, the principle explained with reference to Figure 1 holds. The Ge layer 12 is sandwiched between the GaAs layers 22 and 14 with large band gaps, and holes are trapped in the Ge layer 12 used as a channel. When the undoped GaAs layer 22 is turned into p-GaAs, holes are injected into the Ge from the part of such p-GaAs layer located on the Ge side, and the two-dimensional hole gas increases, so that the current of a device increases. On the other hand, however, there arise the difficulties that a normally-off operation is difficult and the residual current at pinch-off is large.
In an example of the present semiconductor device, the hole mobility at 77K was 30000 cm2 V 1 sec 1, and the transconductance was 430 ms at a source-drain voltage of 0.5 V.
Even when the GaAs layer 13 was replaced with an un-doped GaAsO gSbo 1 layer (thickness: 40 A) and the p-type GaAs layer 14 was replaced with a p-type GaAsO gSbo 1 layer (dopant: p = 1 x 10 /cm , thickness: 500 A), similar operations could be realized.
Embodiment 4:
Using a semi-insulating GaAs substrate, a semiconductor device was manufactured by the method described in Embodiment 2. A sectional view of the device is shown in Figure 8. The same symbols as in Figure 6 denote the same layers. The fact that, after the formation of the p-type GaAs layer 14, the GaAlAs oxide film 19 is formed by introducing oxygen gas while growing GaO 7Alo 3As; that the Be ion implanted region 18' is formed; and the formation of the electrodes are the same as explained in connection with Embodiment 2.
In the figure, numeral 22 represen-ts undoped GaAs, which is intended to improve the interface between the Ge and the GaAs.

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In the present semiconductor device, the gate 20 is formed on the GaAlAs oxide film 19, and no gate current flows. Further, a double-heterostructure in which the un-doped Ge layer 12 forming a channel is sandwiched, is constructed, the residual current being small. In addition, since the gate and the P+ region have a self-alignment structure, a FET of short gate length in which the source-drain distance is small can be readily fabricated. This embodiment has numerous advantages.
Even when the p-type GaAs layer 14 was replaced with a p-type GaO gAlo lAs layer, a similar operation could be performed.
Embodiment 5:
A complementary FET was fabricated by combining the two-dimensional hole gas developing at the interface between a p-GaAs layer and an undoped Be layer and a two dimensional elec~ron gas developing at the interface be-tween n-Ga~ 7Alo 3As and undoped GaAs. Figure 9 is a sectional view of the main portions of such a semiconductor device, while Figure 10 is an equivalent circuit diagram thereof. An n-type FET having a gate 43 and a p-type FET
having a gate 40 can execute a logic operation with very low power consumption, because currents do not simultaneously flow across sources and drains in response to an input signal of one polarity.
On a semi-insulating GaAs substrate 33, an undoped GaO 7Alo 3As layer 34 is grown to a thickness of 1 ~m by the MBE method. This layer is usually made about 300 A -1 ~m thick. An undoped Ge layer 35 is grown on a part of the undoped GaO 7Alo 3As layer 34 to a thickness of 0.05 ~m by the MBE method, and an undoped GaAs layer 47 and a p-type GaAs layer 37 are further grown on the undoped Ge layer 35 to respective thicknesses of 40 A and 0.03 ~m. The semiconductor element having a p-type channel region is formed in these stacked regions. Numerals 39 and 39' in Figure 8 indicate p+ semiconductor regions formed by ion implantation, and ohmic electrodes 41 and 42 are formed 1~790~

thereon. Numeral ~0 indicates the ga-te electrode. The specific construction of the element is substantially the same as in Embodiment 3.
On the other area of the undoped GaO 7Alo 3As layer 34~ an undoped GaAs layer 36 is formed to a thickness of 0.05 ~m, and an undoped GaO 7Alo 3As layer 48 60 A thick ype Ga0.7Al0 3As (n-concentration 7 x 1017 cm~3) layer 38 are further formed thereon. The semiconductor element, having an n-type channel region, is formed in these stacked regions. In the figure, numerals 46 and 46' indica-te regions implanted with Si ions, and ohmic electrodes 44 and 45 are formed thereon. Numeral 43 indicates the gate electrode.
The n-type channel semiconductor device uses as carriers the two-dimensional electron gas which develops at the interface between n-GaAlAs and undoped GaAs. Figure ll shows the band structure of these semiconductor regions.
The solid line indicates the lower ends of conduction bands.
A spike-like carrier profile 49 appears in the conduction band based on a heterostructure. EF indicates the Fermi level at the application of a gate voltage. Electrons are accumulated in a part lower than the Fermi level, and perform two-dimensional conduction. In this example, the p-GaAlAs layer 34 exists in contact with the GaAs layer 36.
Owing to this layer, a potential barrier 50 is formed in the conduction band and hinders electrons from migrating to the substrate side, so that the pinch-off characteristic becomes excellent.
As to the n-Gal xAlx~s layer 38, 0.02 < x is effectively used. The impurity concentration is made at least 1016 /cm2 - 1013 /cm2 or so. The GaAs layer 36 has its impurity concentration made 1014 - l0l5 /cm2 or less. Of course, it may be undoped.
The construction of the n-channel region can be realized even with a different group III - V compound semi-conductor. More specifically, a heterojunction is formed ~79al o ~

of a semiconductor layer of narrow forbidden band and a semiconductor layer of broad forbidden band. The semi-conductor layer of broad forbidden band is doped with an impurity, carriers are transferred into a semiconductor layer of great electron affinity, and the carriers developing at the interface of the heterojunction are controlled.
Multilayered heterojunction devices of high electron mobility according to such construction are described in 10detail in U.S. Patent 4,194,935 issued March 25, 1980 to Raymond Dingle, et al. The principle may be applied.
The crystal growth in the device of the present embodiment is preferably performed by the MBE method employing a mask.
15First, on the GaAs substrate 33, the undoped GaAlAs layer 34 1 ~m thick is grown on the whole surface in an MBE growth chamber. Thereafter, using a Mo metal mask which has an opening in only the area of the p-type FET, the layers 35 and 37 are grown. Subsequently, thé mask is moved to the area of the n-type FET, and the layers 36 and 38 are grown. The subsequent process is similar to the ordinary process for fabricating FETs. That is, the parts 39 and 39' are implanted with Be ions to form the p+ regions as the underlying regions for the ohmic electrodes, and the parts 46 and 46' are implanted with Si ions to form the n regions.
As regards the materials of the electrodes, the electrodes 41, 42 and 43 are made of Ti and W simultaneously evaporated, the electrode 40 is made of Pt, and the electrodes 44 and 45 are made of an Au-Ge-Ni alloy.
In test patterns formed on an identical wafer, the low field mobility of electrons in the n-type channel semi-conductor element was 42000 cm2 V lsec 1 at 77K, and that in the p-type channel semiconductor element was 29500 cm2 V lsec 1. These values correspond to about 100 times the mobility in a Si-MOS transistor when uniformly doped with an impurity at a concentration of 1 x 1017 /cm3, and the present semiconductor device is one order greater in the value of its transconductance gm than the p-type channel MOS transistor employing Si.
Eigure 10 shows the equivalent circuit of this semi-conductor device, and numerals in the figure indicate thecorresponding parts in Figure 9.
Even when the undoped GaAs layer 47 was replaced with an undoped GaO 7Alo 3As layer and the p-type GaAs layer 37 was replaced with a p-type GaO 7Alo 3As layer, similar operations could be performed.
Needless to say, the device of the present embodiment can be realized with the other group III - V compound semiconductor materials, along the lines already described.
In this case, Ge is, of course, used for constructing the device region of high hole mobility.

Claims

Claims:

1. A semiconductor device having at least a first semiconductor layer containing substantially no impurity, a second semiconductor layer having a band gap greater than that of the first semiconductor layer and containing an impurity, an interface between the first and second semiconductor layers forming a heterojunction, at least one pair of electrodes electronically connected with the first semiconductor layer, and means to control carriers developing at the heterojunction interface; characterized in that the first semiconductor layer is a Ge layer, while the second semiconductor layer is a group III - V compound semi-conductor layer.

2. A semiconductor device as defined in claim 1, where-in a thin, second semiconductor region containing sub-stantially no impurity exists in a part of said second semi-conductor layer adjacent said heterojunction.

3. A semiconductor device as defined in claim 1 or 2, including an active region which comprises at least a third semiconductor layer containing substantially no impurity, a fourth semiconductor layer having a band gap greater than that of the first semiconductor layer and containing an impurity, an interface between the first and second semi-conductor layers forming a heterojunction, at least one pair of electrodes electronically connected with the first semi-conductor layer, and means to control carriers developing at the heterojunction interface, wherein said third and fourth semiconductor layer is each a group III - V
compound semiconductor layer.

4. A semiconductor device as defined in claim 1 or 2, characterized in that said second semiconductor layer is a GaAs layer.