CA1166756A - Pipeline control system for a computer - Google Patents
Pipeline control system for a computerInfo
- Publication number
- CA1166756A CA1166756A CA000356690A CA356690A CA1166756A CA 1166756 A CA1166756 A CA 1166756A CA 000356690 A CA000356690 A CA 000356690A CA 356690 A CA356690 A CA 356690A CA 1166756 A CA1166756 A CA 1166756A
- Authority
- CA
- Canada
- Prior art keywords
- tag
- phase
- flows
- processing
- executing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
- G06F9/381—Loop buffering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
- G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
Abstract
ABSTRACT OF THE DISCLOSURE The present invention provides an improvement in a pipeline control system for a computer. Thus, in such a system in which the flows of processings successively proceed through a plurality of processing stages, pre-determined tag data are given to each of the processing stages to simultaneously effect the processings through the processing stages so that a plurality of processing flows proceed successively while maintaining a time lag. With this invention, the improvement resides in storing the predetermined tag data in a plurality of tag registers during the step of executing a first sequence of operation flows in order to repetitively execute the flow of process-ing which is based on the same tag data. The required tag is selected from the tags stored in the tag registers in steps for executing second and subse-quent operation flows in which the same operation flows will be repeated. Thus, an execution is initiated from the second phase without executing the first phase. The system of this invention increases the operation speed of a pipeline computer system by eliminating the additional operation flow which has hitherto been employed when one instruction was to be switched to another instruc-tion.
Description
1 i6f~5~;
..
The prese.nt invention relates to a pipeli.ne control system for a computer.
Th.e present invention has ~ee'n proposed to s-olve the problems inheren-t in conventional systems, as wi.ll ~e discussed he:reinafter.
The principal ohjec-t of the present invention is to increase 'the operation speed of a pipeline computer system ~y elimïnating the additïonal operation flow which has hitherto been employed wh.en one instruction was to be lQ switched to another instruction.
According to the present invention, there is provided a pipeline control system for a computer in which the flows of processings successively proceed through.a plurality of processing stages, predetermined tag data are given to each of said processing stages to simultaneously effect the processings through said processing stages, such that a plurality of processing flows proceed successively while maïntaining a time lag, wherein the improvement is - :
ch.aracterized in th.at predetermined tag data are stored in a plurality of tag registers during a step for executing a first sequence of operation flows in order to repetitively execute the flow of processing ~hich. is ~ased upon the same ''' tag data, and a required tag is selected from said tags stored in said tag registers in steps for executing second and subsequences of operation flows in which the same operation flows will ~e repeated, so that an execution is initiated from a second phase without executing a first phase.
Having thus generally described the invention, reference will now ~e made to the accompanying drawings~
illustrating the prior art and preferred em~odiments of the present invention, in ~hic~.:
FIGURE 1 is a diagram sche'mati.cally illustrating, in series, an operati.on for pipe.l'ine controlling an electronic computer~
.
~ ,1 6~7~)G
..
The prese.nt invention relates to a pipeli.ne control system for a computer.
Th.e present invention has ~ee'n proposed to s-olve the problems inheren-t in conventional systems, as wi.ll ~e discussed he:reinafter.
The principal ohjec-t of the present invention is to increase 'the operation speed of a pipeline computer system ~y elimïnating the additïonal operation flow which has hitherto been employed wh.en one instruction was to be lQ switched to another instruction.
According to the present invention, there is provided a pipeline control system for a computer in which the flows of processings successively proceed through.a plurality of processing stages, predetermined tag data are given to each of said processing stages to simultaneously effect the processings through said processing stages, such that a plurality of processing flows proceed successively while maïntaining a time lag, wherein the improvement is - :
ch.aracterized in th.at predetermined tag data are stored in a plurality of tag registers during a step for executing a first sequence of operation flows in order to repetitively execute the flow of processing ~hich. is ~ased upon the same ''' tag data, and a required tag is selected from said tags stored in said tag registers in steps for executing second and subsequences of operation flows in which the same operation flows will ~e repeated, so that an execution is initiated from a second phase without executing a first phase.
Having thus generally described the invention, reference will now ~e made to the accompanying drawings~
illustrating the prior art and preferred em~odiments of the present invention, in ~hic~.:
FIGURE 1 is a diagram sche'mati.cally illustrating, in series, an operati.on for pipe.l'ine controlling an electronic computer~
.
~ ,1 6~7~)G
- 2 FIGURE 2 is a diagram of tag registers ~hich are arrayed in series to i.llustrate an operatlon of a conven-tional pipeline control system;
FrGURE 3 is a diagram illustrating, in series, an operation of a series of tag regi.sters of Fig. 2;
FIGURE 4 is a diagram of a series of tag registers which are used for a pipeli~e control system according to an embodiment of the present invention; and FIGUR~ 5 is a di.agram illustrating, in series, an lQ operation of th.e series of tag registers of Fi.g. 4.
Referring now to the drawings in greater detail, in general, when an eIectronic computex is to ~e controlled relying upon a pipeline: control met~od, instruction 1 through. instruction 13 successively pass through processing lS stages I throuyh VI according to a time as determined by reference clock cycles tO, tl, t2, ...tl3, as illustrated in Fig. 1. For example, in the processing stage I, an instruction is taken out by processing cycles Ia, I~l and Ib2.
In the processing stage II, an instruction is decoded by processing cycles D and R. In the processing stage III, an operand is read-out by processing cycles A, Bl and B2. In the processing stage IV, an operation is executed by pro~
cessing cycles El, E2 and E2D. In the processing stage V, a result of operation is checked ~y a processing cycle CKo In the processing stage VI, the result of operation is stored by a processing cycle W.
In a pipeline control system as illustrated in Fig. 2, a processing flow is formed ~y a series of processing cycles consisting of a cycle D, for decoding, a cycle R, for reading, 3a cycle A, for address calculation, cycles Bl and B2, for operand read-out, cycles El and E2, for operation execution, a cycle CK, for operation result checking, and a cycle ~, for operation result ~riti.ng. These processing c~cles are divi.ded ïnto phases. Namely, the cycles D and R are included in a phase-l, the cycles A and Bl are included in a :~ , G
phase-2, the 'cycles B2 and El are i,ncluded in a phase-3, the cycle E2 is included in a phase-4, the' c~cle CK is included in a p~ase-5, and the cycle W is included in a' phase-6. The processing flow- i5 controlled hy an instruc-tion register INS RE:G, a control storage CS, a tag register of phase-l PH:-1 TAG, a tag,re~ister of phase-2 PH~2 TAG, a tag register of phase-3 PH-3TAG, a tag register of phase-4 PH-4 TAG, and a tag regist-er of pha'se-5 PH-5 TAG.
Tag data necessary for ex'ecuting instructions are stored in the' control stora~e 'CS. When instructions are to ~e ex'ecuted, the tag data are successively read out from the control storage CS depending uPon the data of the instruction registe~ INS REG, and are supplied to a group of tag registers PH-1 TAG, PX- 2 TAG, PH 3 TAG, PH 4 TAG and PH:- 5 TAG.
The operation of the' conventi,onal pipeline control system of Fig. 2 is illustrated in Fig. 3. Let it ~e assumed that an operation consisting of two operation flows (fl and f2~ is carried out for one instruction. In this case, even if the same operation flow such as a move character MVC is repetïtively executed, the phase-l PH 1 generates a predetermined tag PH-l TAG every time for each operation flow. However, when one instruction is finished and then another operation of another instruction is to ~e , 25 carried out, a tag data for another operation must be taken out from the control storage CS and must ~e fed to the tag registers PH-l TAG, PH-2 TAG, PH-3 TAG, PH-4 TAG and PH-5 TAG. When one instruction is to be switched to another instruction, therefore, a procedure is required to withdraw the previously employed tag and to introduce a new tag~ The a~ove procedure, hbwever, requires an additional operation flow f2' as well as additional time for effecting the additional operation flow f2'. This is ~ecause the decision of switchi'ng to the'next instruotion is esta~lished in the phase-2 of the 'last operation f]ow o~ the present instruction, and in that phas~ 2, the phase-l of the ne~t ; 7,5 ~;
operation flow f2' has already started. ~ith the system of ~ig. 2, therefore, the operation speed of the whole apparatus ten'ds to ~e decreased.
An em~odiment of the' present invention is illustrated in Figs. 4 and 5. Fig. 4 illustrates a series of processing cycles ïn an operation of a pipeline control system. Th:e series of processing cycles consists of a cycle D, ~or decoding, a cycle R, for reading, a cycle A, for address calculation, cycles ~1 and ~2, for operand lQ read-out, cycles El and E2, for operation execution, a cycle 'CK,' for operatîon result checking, and a cycle W, for operation result writing. These processing cycles are divided into phases. The 'cycles D and ~ are included in a phase-l CPH'-l~, the cycles A and ~1 are included in a phase-2 (PH-21, the cycles B2 and El are included in a phase-3 CPH-3~, the cycle E2 is included in a phase-4 ~PH-4~, the cycle CK i5 included in a phase-5 (PH-5), and the cycle W is included in a phase-6 (PH-61. The operation is performed ~y an instruction register INS REG, a control 2C storage'CS, a'tag register PH-l TAG of the phase-l, tag registers P~I-2 TAG No. 1 and PH-2 TAG No. 2 of the phase-2, a selection controller SEL CONT, a seIector SEL, a tag register PH-3 TAG of the phase-3, a tag register PH-4 TAG
of the phase-4, and a tag register P~-5 TAG of the phase-5.
The phase-2 ~PH'-2) contains a plurality of tag registers as denoted ~y'No. 1 and No. 2 which will ~e selected by the selector SEL that is controlled ~y output signals of the selection controller SEL CONT.
Fig. 5 illustrates an example of an operation of 3C Fig. 4. When the operatïon consists of two operation flows fll and f21, a tag of phase-l is written on the' register PH-l TAG, and tags of phase-2'are written on the registers PH-2 TAG No. 1 and P~-2 TAG No. 2, corresponding to the two flows fll and f21, respectivel~O The flows of operation successiveIy proceed from the phase-l to the phase-5 and repeat until a finish of operation is detected. After the .. ..
~- ~
.~: . . .
7~ G
first sequence of the operation flows fll and f21 has been executed, the next sequence of the operation flows fl2 and f22 is repeated in the same manner as the operation flows fll and f21 if there is no change in the operation command.
In the operation flow fl2, in this case, the register PH-2 TAG No. 1 is used as a tag of the phase-2, and the flow is initiated from the address calculation cycle A of the phase 2. Namely, the cycle D, for decoding, and the cycle R, for reading, of the phase-l are omitted. In the operation flow f22, the register PH~2 TAG No. 2 is used as ! a tag of the phase-2, and the flow is initiated from the cycle A, for address caluculation, of the phase-2. Namely, the cycle D and the cycle R of the phase-l are omitted.
When the instruction i5 switched to another instruction, a 15 flow f3 is performed. In the flow f3, while the previous operation flow is being repea~ed, the next tag is taken out by using the tag PH~l TAG in the phase-l which is in a vacant state in the repeated flows. The cycle D and the cycle R are repeated in the flow f3 until a completion of 20 the previous operation is detected. After the completion of the previous operation has been detected, the operation is immediately switched to another operation flow, and the cycle A and subsequent cycles are carried out following the cycle D and the cycle R. If the end of the repetition is f 25 detected in the phase-2 of the flow f22, for example, the phase-2 of the next flow f3 is immediately started following said phase-2 of the flow f22. That is to say, the additional operation flow f2' required in the conventional operation of Fig. 3, is eliminated.
30 Consequently, the operation speed of the pipeline-type computer sys-tem can be prevented from being decreased.
The tags of phase-2 are selected by the selector SEL
which is controlled by the selection controller SEL CONT.
The above-mentioned selection can be effected by employing 35 either a selection bit in the tags of phase-2 or a selection correct signal SS which is applied to the selection controller SEL CONT. Further, the number of tags . .
I ~ ~6~56 in the phase-2 needs not be limited to two, i.e~, tag No. 1 and tag No. 2, but may be three or more.
' ' ~
FrGURE 3 is a diagram illustrating, in series, an operation of a series of tag regi.sters of Fig. 2;
FIGURE 4 is a diagram of a series of tag registers which are used for a pipeli~e control system according to an embodiment of the present invention; and FIGUR~ 5 is a di.agram illustrating, in series, an lQ operation of th.e series of tag registers of Fi.g. 4.
Referring now to the drawings in greater detail, in general, when an eIectronic computex is to ~e controlled relying upon a pipeline: control met~od, instruction 1 through. instruction 13 successively pass through processing lS stages I throuyh VI according to a time as determined by reference clock cycles tO, tl, t2, ...tl3, as illustrated in Fig. 1. For example, in the processing stage I, an instruction is taken out by processing cycles Ia, I~l and Ib2.
In the processing stage II, an instruction is decoded by processing cycles D and R. In the processing stage III, an operand is read-out by processing cycles A, Bl and B2. In the processing stage IV, an operation is executed by pro~
cessing cycles El, E2 and E2D. In the processing stage V, a result of operation is checked ~y a processing cycle CKo In the processing stage VI, the result of operation is stored by a processing cycle W.
In a pipeline control system as illustrated in Fig. 2, a processing flow is formed ~y a series of processing cycles consisting of a cycle D, for decoding, a cycle R, for reading, 3a cycle A, for address calculation, cycles Bl and B2, for operand read-out, cycles El and E2, for operation execution, a cycle CK, for operation result checking, and a cycle ~, for operation result ~riti.ng. These processing c~cles are divi.ded ïnto phases. Namely, the cycles D and R are included in a phase-l, the cycles A and Bl are included in a :~ , G
phase-2, the 'cycles B2 and El are i,ncluded in a phase-3, the cycle E2 is included in a phase-4, the' c~cle CK is included in a p~ase-5, and the cycle W is included in a' phase-6. The processing flow- i5 controlled hy an instruc-tion register INS RE:G, a control storage CS, a tag register of phase-l PH:-1 TAG, a tag,re~ister of phase-2 PH~2 TAG, a tag register of phase-3 PH-3TAG, a tag register of phase-4 PH-4 TAG, and a tag regist-er of pha'se-5 PH-5 TAG.
Tag data necessary for ex'ecuting instructions are stored in the' control stora~e 'CS. When instructions are to ~e ex'ecuted, the tag data are successively read out from the control storage CS depending uPon the data of the instruction registe~ INS REG, and are supplied to a group of tag registers PH-1 TAG, PX- 2 TAG, PH 3 TAG, PH 4 TAG and PH:- 5 TAG.
The operation of the' conventi,onal pipeline control system of Fig. 2 is illustrated in Fig. 3. Let it ~e assumed that an operation consisting of two operation flows (fl and f2~ is carried out for one instruction. In this case, even if the same operation flow such as a move character MVC is repetïtively executed, the phase-l PH 1 generates a predetermined tag PH-l TAG every time for each operation flow. However, when one instruction is finished and then another operation of another instruction is to ~e , 25 carried out, a tag data for another operation must be taken out from the control storage CS and must ~e fed to the tag registers PH-l TAG, PH-2 TAG, PH-3 TAG, PH-4 TAG and PH-5 TAG. When one instruction is to be switched to another instruction, therefore, a procedure is required to withdraw the previously employed tag and to introduce a new tag~ The a~ove procedure, hbwever, requires an additional operation flow f2' as well as additional time for effecting the additional operation flow f2'. This is ~ecause the decision of switchi'ng to the'next instruotion is esta~lished in the phase-2 of the 'last operation f]ow o~ the present instruction, and in that phas~ 2, the phase-l of the ne~t ; 7,5 ~;
operation flow f2' has already started. ~ith the system of ~ig. 2, therefore, the operation speed of the whole apparatus ten'ds to ~e decreased.
An em~odiment of the' present invention is illustrated in Figs. 4 and 5. Fig. 4 illustrates a series of processing cycles ïn an operation of a pipeline control system. Th:e series of processing cycles consists of a cycle D, ~or decoding, a cycle R, for reading, a cycle A, for address calculation, cycles ~1 and ~2, for operand lQ read-out, cycles El and E2, for operation execution, a cycle 'CK,' for operatîon result checking, and a cycle W, for operation result writing. These processing cycles are divided into phases. The 'cycles D and ~ are included in a phase-l CPH'-l~, the cycles A and ~1 are included in a phase-2 (PH-21, the cycles B2 and El are included in a phase-3 CPH-3~, the cycle E2 is included in a phase-4 ~PH-4~, the cycle CK i5 included in a phase-5 (PH-5), and the cycle W is included in a phase-6 (PH-61. The operation is performed ~y an instruction register INS REG, a control 2C storage'CS, a'tag register PH-l TAG of the phase-l, tag registers P~I-2 TAG No. 1 and PH-2 TAG No. 2 of the phase-2, a selection controller SEL CONT, a seIector SEL, a tag register PH-3 TAG of the phase-3, a tag register PH-4 TAG
of the phase-4, and a tag register P~-5 TAG of the phase-5.
The phase-2 ~PH'-2) contains a plurality of tag registers as denoted ~y'No. 1 and No. 2 which will ~e selected by the selector SEL that is controlled ~y output signals of the selection controller SEL CONT.
Fig. 5 illustrates an example of an operation of 3C Fig. 4. When the operatïon consists of two operation flows fll and f21, a tag of phase-l is written on the' register PH-l TAG, and tags of phase-2'are written on the registers PH-2 TAG No. 1 and P~-2 TAG No. 2, corresponding to the two flows fll and f21, respectivel~O The flows of operation successiveIy proceed from the phase-l to the phase-5 and repeat until a finish of operation is detected. After the .. ..
~- ~
.~: . . .
7~ G
first sequence of the operation flows fll and f21 has been executed, the next sequence of the operation flows fl2 and f22 is repeated in the same manner as the operation flows fll and f21 if there is no change in the operation command.
In the operation flow fl2, in this case, the register PH-2 TAG No. 1 is used as a tag of the phase-2, and the flow is initiated from the address calculation cycle A of the phase 2. Namely, the cycle D, for decoding, and the cycle R, for reading, of the phase-l are omitted. In the operation flow f22, the register PH~2 TAG No. 2 is used as ! a tag of the phase-2, and the flow is initiated from the cycle A, for address caluculation, of the phase-2. Namely, the cycle D and the cycle R of the phase-l are omitted.
When the instruction i5 switched to another instruction, a 15 flow f3 is performed. In the flow f3, while the previous operation flow is being repea~ed, the next tag is taken out by using the tag PH~l TAG in the phase-l which is in a vacant state in the repeated flows. The cycle D and the cycle R are repeated in the flow f3 until a completion of 20 the previous operation is detected. After the completion of the previous operation has been detected, the operation is immediately switched to another operation flow, and the cycle A and subsequent cycles are carried out following the cycle D and the cycle R. If the end of the repetition is f 25 detected in the phase-2 of the flow f22, for example, the phase-2 of the next flow f3 is immediately started following said phase-2 of the flow f22. That is to say, the additional operation flow f2' required in the conventional operation of Fig. 3, is eliminated.
30 Consequently, the operation speed of the pipeline-type computer sys-tem can be prevented from being decreased.
The tags of phase-2 are selected by the selector SEL
which is controlled by the selection controller SEL CONT.
The above-mentioned selection can be effected by employing 35 either a selection bit in the tags of phase-2 or a selection correct signal SS which is applied to the selection controller SEL CONT. Further, the number of tags . .
I ~ ~6~56 in the phase-2 needs not be limited to two, i.e~, tag No. 1 and tag No. 2, but may be three or more.
' ' ~
Claims (2)
1. A pipeline control system for a computer in which the flows of processings successively proceed through a plurality of processing stages, predetermined tag data are given to each of said processing stages to simultaneously effect the processings through said processing stages, such that a plurality of processing flows proceed successively while maintaining a time lag, wherein the improvement is characterized in that predetermined tag data are stored in a plurality of tag registers during a step for executing a first sequence of operation flows in order to repetitively execute a flow of processing which is based upon the same tag data, and a required tag is selected from said tags stored in said tag registers in steps for executing second and subsequent sequences of operation flows in which the same operation flows will be repeated, so that an execution is initiated from a second phase without executing a first phase.
2. A pipeline control system for a computer as set forth in claim 1, wherein a plurality of tag registers are provided for the second phase, and said plurality of tag registers are selected by a selector.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP96231/79 | 1979-07-28 | ||
| JP9623179A JPS5621242A (en) | 1979-07-28 | 1979-07-28 | Pipeline control method for computer operation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1166756A true CA1166756A (en) | 1984-05-01 |
Family
ID=14159446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000356690A Expired CA1166756A (en) | 1979-07-28 | 1980-07-22 | Pipeline control system for a computer |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4794518A (en) |
| EP (1) | EP0032515B1 (en) |
| JP (1) | JPS5621242A (en) |
| AU (1) | AU525682B2 (en) |
| CA (1) | CA1166756A (en) |
| DE (1) | DE3067752D1 (en) |
| WO (1) | WO1981000474A1 (en) |
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| WO1991010954A1 (en) * | 1990-01-19 | 1991-07-25 | Alliant Computer Systems Corporation | A risc vectorization system |
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| JP2943464B2 (en) * | 1991-12-09 | 1999-08-30 | 松下電器産業株式会社 | Program control method and program control device |
| US5694564A (en) * | 1993-01-04 | 1997-12-02 | Motorola, Inc. | Data processing system a method for performing register renaming having back-up capability |
| DE10034869A1 (en) * | 2000-07-18 | 2002-02-07 | Siemens Ag | Method for automatically obtaining a functional sequence of processes and tools for this |
| US20060090015A1 (en) * | 2004-10-26 | 2006-04-27 | Bradfield Travis A | Pipelined circuit for tag availability with multi-threaded direct memory access (DMA) activity |
| US7454598B2 (en) * | 2005-05-16 | 2008-11-18 | Infineon Technologies Ag | Controlling out of order execution pipelines issue tagging |
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| JPS5466048A (en) * | 1977-11-07 | 1979-05-28 | Hitachi Ltd | Information processor |
| US4228497A (en) * | 1977-11-17 | 1980-10-14 | Burroughs Corporation | Template micromemory structure for a pipelined microprogrammable data processing system |
| JPS6024985B2 (en) * | 1978-08-31 | 1985-06-15 | 富士通株式会社 | Data processing method |
| US4253147A (en) * | 1979-04-09 | 1981-02-24 | Rockwell International Corporation | Memory unit with pipelined cycle of operations |
| US4310880A (en) * | 1979-09-10 | 1982-01-12 | Nixdorf Computer Corporation | High-speed synchronous computer using pipelined registers and a two-level fixed priority circuit |
| JPS58129550A (en) * | 1982-01-27 | 1983-08-02 | Toshiba Corp | Arithmetic sequence device |
| US4594655A (en) * | 1983-03-14 | 1986-06-10 | International Business Machines Corporation | (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions |
-
1979
- 1979-07-28 JP JP9623179A patent/JPS5621242A/en active Granted
-
1980
- 1980-07-22 CA CA000356690A patent/CA1166756A/en not_active Expired
- 1980-07-25 WO PCT/JP1980/000171 patent/WO1981000474A1/en active IP Right Grant
- 1980-07-25 AU AU61250/80A patent/AU525682B2/en not_active Expired
- 1980-07-25 DE DE8080901417T patent/DE3067752D1/en not_active Expired
- 1980-07-25 EP EP80901417A patent/EP0032515B1/en not_active Expired
-
1985
- 1985-09-26 US US06/780,645 patent/US4794518A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5757740B2 (en) | 1982-12-06 |
| EP0032515A4 (en) | 1982-02-05 |
| AU525682B2 (en) | 1982-11-18 |
| EP0032515B1 (en) | 1984-05-09 |
| DE3067752D1 (en) | 1984-06-14 |
| AU6125080A (en) | 1981-03-03 |
| JPS5621242A (en) | 1981-02-27 |
| EP0032515A1 (en) | 1981-07-29 |
| WO1981000474A1 (en) | 1981-02-19 |
| US4794518A (en) | 1988-12-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry | ||
| MKEX | Expiry |
Effective date: 20010501 |