CA1133154A - Digital bus communications system - Google Patents
Digital bus communications systemInfo
- Publication number
- CA1133154A CA1133154A CA322,336A CA322336A CA1133154A CA 1133154 A CA1133154 A CA 1133154A CA 322336 A CA322336 A CA 322336A CA 1133154 A CA1133154 A CA 1133154A
- Authority
- CA
- Canada
- Prior art keywords
- terminals
- time slots
- signal
- path
- slot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
- H04J3/245—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially in which the allocation protocols between more than two stations share the same transmission medium
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/417—Bus networks with decentralised control with deterministic access, e.g. token passing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Astronomy & Astrophysics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Small-Scale Networks (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
This invention relates to a novel time division multiple access communication system. The system comprises a common signal path (or bus) and a set of terminals coupled to the path, the set includes means for establishing one or more communication links over the path between one or more of the terminals, and means for transferring digital signals between linked terminals in one or more time slots associated with the links, the time slots are in a repetitive framed sequence, each of the terminals has an associated address and includes means to identify and receive correspondingly addressed digital signals on the path. The terminal further includes means for transmitting an addressed primary slot allocation signal on the signal path in at least one of the time slots, the primary slot allocation signal is addressed to one or more other terminals and includes data representative of the identity of an allocated one or more of the time slots in which the other terminals may transmit addressed signals on the path. The system allows for control of bus access and communication link formation to be distributed over a plurality of terminals in the system. It provides a system in which subscriber terminals contend for transmission time slots and accommodates both high and low duty cycle subscribers by controlling slot allocations and contention slot transmissions.
This invention relates to a novel time division multiple access communication system. The system comprises a common signal path (or bus) and a set of terminals coupled to the path, the set includes means for establishing one or more communication links over the path between one or more of the terminals, and means for transferring digital signals between linked terminals in one or more time slots associated with the links, the time slots are in a repetitive framed sequence, each of the terminals has an associated address and includes means to identify and receive correspondingly addressed digital signals on the path. The terminal further includes means for transmitting an addressed primary slot allocation signal on the signal path in at least one of the time slots, the primary slot allocation signal is addressed to one or more other terminals and includes data representative of the identity of an allocated one or more of the time slots in which the other terminals may transmit addressed signals on the path. The system allows for control of bus access and communication link formation to be distributed over a plurality of terminals in the system. It provides a system in which subscriber terminals contend for transmission time slots and accommodates both high and low duty cycle subscribers by controlling slot allocations and contention slot transmissions.
Description
~lL3~
. .
The f.ield of this invention is communica-tions systems, and more particularly, time division multiple access digital bus communications systems~
There.are many forms of multiple access communications systems known in the art, including for example the time division system disclosed in U.S. Patent No. 3,851,104. These systems, basically provide an information bus for transferring digital message signals between remote terminals. In the prior art 1~ systems J there are a number of protocols u-tilized to accommodate the various terminals in the network and provide them with access to a communications bus. Such protocols include simple polling, priority request, contention~ and cyclic time division with fixed slot allocations.
In the polling type systems, a central controller sequentially polls each of the remote terminals, offeri~g each an opportunity to ac~ess the communications bus when available.
In priority request systems, remote terminals ready to transmit a message make a request, and are granted access to the bus according to priorities established by a bus arbiter at a central controller. In contention systems, remote terminals may transmit messages at random times, monitor the signals on the bus, and subsequently re-transmit tn the event two or more simultaneous transmissions are detected.
The polling and priority request approaches have been applied to time division systems in the prior art whereby a central terminal controls the bus access. However, such systems are typically characterized by a rigid formating of messages and an inflexible set of system constraints controlling the time periods at which the various remote terminals may ga.in access to ~.
1 the communication pathO In addition, the various data rates at which the individual remote terminals may transmit message signals are hard-wired into the systems to define predetermined portions of the channel bandwidth which are allocated to each of the remote terminals.
The cyclic time division systems, including that dis~
closed in U.S. Patent No. 3,851,104 dedicate regularly occurrin~
time slots in a repetitive framed sequence to specific users for their transmissions, and hence, may be referred to as a fixed slot allocation system. In the system described in U.S. Patent No. 3,851r104 the slot allocations may be tailored somewhat to specific user requirements through the procedure whereby remote terminals may request certain portions of the bus spectrum in predetermined access request time slots. In this system, a central controller then allocates families of message time slots to the requesting terminals in accordance with various parameters, such as predetermined priorities, time slot availabilities, and the like.
The system described in U.S. Patent No. 3,851,10~
overcomes these disadvantages to a large extent by permitting dynamic allocation of time slots in order to accommodate desired access time and data rate variations. However, in the referenced systems, all the control is achieved at a central terminal, which must control bus access and link formation for the entire system.
Consequently, the level of complexity for that control terminal is relatively high. In addition, outage of that central terminal causes failure of the entire system.
Typically, in operating environments, a system is required to accommodate high duty cycle subscribers, low duty cycle subscribers, and combinations of both. The high duty cycle ~ 3~
1 subscrihers, such as inter-computar lin]cs, have generally been accommodated in the prior art by the cyclic time division systems wherein the various subscribers are assigned fixed slot alloca-tions in the repetitive time framed time sequence on the bus4 The low duty cycle, or bursty, subscribers, such as communications terminals, have been accommodated in the prior art by unslotted contention type systems, where the entire bus bandwidth is allocated to a single subscriber. Although these types of systems are specifically tailored for the particular types of subscribers, neither system type optimally accommodates both high and low duty cycle subscribers.
~ ccordingly, it is an object of the present invention to provide a time division multiple access communications system in which control of bus access and communication link formation is distributed over a plurality of terminals in the system.
It is another object to provide,a time division multiple access communications system in which subscriber terminals contend for transmission time slots.
A further object is to provide a time ~iviaion multiple access communications system which accommodates both high and low duty cycle subscribers by controlling slot allocations and contention slot transmissions~
SUMMARY OF THE IN~ENTION
Briefly, the present invention provides a time division multiple access communications system including a plurality of terminals coupled to a co~mon signal path, or bus. Communication links are established over the path between one or more of the terminals wherein digital signals may be transferred in time slots in a repetitive ~ramed sequence between linked terminals.
In one form of the invention, selected time slots within ~L~3~
1 the framed sequence are allocated on a relatively static basis to various requesting terminals to establish the lin~. In accordance with the invention, the slot allocation function may be distributed over th~ entire system, wherein at least one terminal having the slot allocation capability may address selected other terminals and allocate that slot allocation capability among those selected other terminals. Thereafter, the signal path bandwidth may be effectively allocated by either the primar~ terminal or the selected other terminals, permitting a flexible, dynamic allocation of the system bandwidth. The primary slot allocating terminal may accordingly address selected ones of - the other terminals, and may transfer data to those terminals representative of the identity of an allocated one or more unused time slots which may be allocated by those selected terminals to the various other terminals coupled to the path. In this form, the administration workload for the s~stem may be distributed so that no single terminal is required to perform all of the bus access control functions. The system may efficiently accommodate relatively high usage and priority subscriber terminals with a desired portion of the signal path bandwidth, while controlling the mean time to access the signal path for the remaining terminalsO
In a second form, the present invention provides a slotted time division system wherein the various subscriber terminals contend for access to the signal path. In this form, the common signal path includes one or more pairs- of oppositely directed unidirectional signal paths connecting each o~ the terminals. A connector network at a central location is adapted to receive signals from time slots along the paths inbound ~o that connector, and to txansfer those signals to the paths 1 outbound from that connector network in corresponding time slots associated with that outbound path. The entire signal path band-width is allocated to a single terminal at a time. Each terminal with this contention capability is operative to transmit a message signal in the slots on the inbound path, and then monitors the outbound path to detect the presence of that transmitted signal.
The connector detects signal collisions (from two or more terminals) in the various time slots on the inbound path, and when such a collision is detected, the connector network inhibits the transfer of signals from the inbound path to the outbound path. Thus, when a collision is de-tected, no slot ; signal is transferred to the outbound path and the transmitting terminal is unable to confirm that its transmission was success-ful ~i.e avoided collision). In this con-figuration, the con-nector also includes a retransmit tirne signal generator for transmitting on the out~ound path signals addressed to the various remote terminals and including data for controlling the selection of a re-transmission time slot by the trans-mitting terminal. The transmitting terminal is responsive to that signal to select a subsequen~ time slot for commencing the re-transmission of the message. The process repeats un~il the transmitting terminal gains access (wit11out collision1 to the signal path. This second form of the invention is particularly well suited to low duty cycle, or bursty, subscriber terminals.
In a third form of the invention, a dual mode communi cation system is provided wherein certain of the time slots on the signal path are controlled for use in dynamic allocation operation with relatively static slot assignments (in conjunction with a set of terminals adapted for dynamic allocation) in the .
1 manner descrlbed above for the first form of the invention, and a second set of time slots in the signal path are adapted to be used by -terminals operating in accordance with the contention form of the invention described above. In this third form, the ratio of use of time slots between the allocation and contention mode of operation may be adaptively controlled in the form of the number of time slots allocated for each unction~ or by means of the mode of operation for the various termlnals and ratio of such terminals connected to the system. In this third form, the dual mode system may be dynamically varied to accommodate any desired current usage of both bursty (low duty cycle) and long-~ term (high duty cycle) subscriber terminals. Typically, computers ; are high duty cycle users and receive dedicated slot assign-ments which may be varied according to priorities through the allocation of ~he varying numbers of slots per frame to the par-ticular terminals. Low duty cycle or bursty users, like communi-.~
cation terminals, are each given the same slot assignments and ` contend for transmission in that set of slots. In this third form, each type of subscriber may communicate with any subscriber of either type since the data message formats are identical.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects of this invention, the various features thereof, as well as the invention itself, may be more fully understood from the following description, when read together with the accompanying drawings in which:
Fig. 1 shows in block diagram form a communications system in accordance with the invention;
Fig. 2 shows the general message signal format for the system of Fig. 1;
- Fig. 3 shows in block diagram form an exemplary embodiment of a digital bus repeater for the system of Fig. 1;
Fig. 4 shows in block diagram form an exemplary embodiment of the bus interface unit ~BIU) o~ the system of Fig. l;
Fig. 5 shows in block diagram form an exemplary embodiment of the modulator of the BIU oE Fig. 4;
Fig. 6 shows in block diagram form an exemplary embodiment of the demodulator of the BIU of Fig~ 4;
Fig. 7 shows in block diagram form an exemplary embodiment of the control logic of the BIU of Fig. 4;
Fig. 8 shows in block diagram form an exemplary embodiment of the microcontroller of the control logic of Fig. 7;
Fig. 9 shows the instruction format for the micro-controller of Fig. 8;
Fig. 10 shows the operational cycle for microcontroller of Fig~ 8;
Figs llA-E show exemplary message signal formats for use with the system of Fig. l;
Fig, 12 shows in block diagram form an exemplary embodiment for the input/output logic of the BIU of Fig. 4.
DESCRIPTION OF THE PREFERRED ~MBODIMENT
A high speed time division multiple access (TDMA) digital comrnunications system is shown in block diagram form in Fig. 1. The system includes a common si~nal path comprisin~
inbound bus 10 and outbound bus 12, and a set of addressed sub-scriber devices coupled to the buses 10 and 12. As shown, the set includes subscriber devices 14, 16 and 18. Each sub-scriber device is coupled to both inbound bus 10 and outbound bus 12 by a respective one of bus interface units (BIU's) 20, 22 1 and 24. In alternative embodiments, a plurality of subscriber devices may be coupled to the bus by each of the BIU's, and different numbers of subscribe.r devices and associated BIU's may be coupled to the buses~ The present system is adap-ted to pro-vide a transfer of digital signals between subscriber devices coupled to the common signal path in one or more time slots in a repetitive framed sequence.
In the present embodiment, the inbound bus 10 and out-bound bus 12 comprise oppositely-directed unidirectional digital signal paths coupled at a system head-end by a digital bus re-peater (DBR) 26. By way of example, the inbound bus 10 and outbound bus 12 may be separate channels on a conventional wide-band distribution system, such as a ~wo cable television (CATV) . trunk/feeder network. In alternative embodiments, the common signal path may comprise a bidlrectional signal path coupling each of the subscriber devices.
Each BIU is adapted to transmit a serial bit stream in selected time slots on the inbound bus 10, and to recei~e a continuous serial bit stream from the outbound bus 12. The BIU's provide access to the data bus for their associated devlces and establish electrical and functional capabilities between the buses and the respective subscribers.
The data bus repeater (DBR) 26 is a connector network which receives inbound da-ta on bus 10, retimes and reformats such data with a one slot delay, and retransmits it under control of a master clock onto the outbound bus 12. The retransmitted data is available for reception by all BIU's coupled to bus 12.
In operation, the buses carry digital signals in tlme slots in the repetitive framed sequence. As described more fully belowr the time slot signals may be either of two types, control - 8 ~
~ or message. Control type signals transfer control data between - BIU's which is processed to establish various control functions for the system (such as monitoring status, or establishing a communication link between terminals). Message type signals transf~r message data between terminals, generally for inter-subscriber communication purposes. In general, in addition to the control or message data, each signal on bus 12 includes an originating terminal address, a desired destination terminal addr~ss, and a data word indicative of the type, i.e. either control or message.
~ ach BIU coupled to bus 12 continuously monitors the data slots on that bus, examining various data fields in -those slots for type and other information, e.g. destination address.
In general, if an address is detected which matches that of its, or one of its, associated terminals, the BIU either transfers the message data to the terminal (when the slot signal is a data type), or processes the control data internally (when the slot is a control type).
Each BIU may be assigned a set of slots in the framed sequence for the transmission of time slot signals on the inbound bus 10. In the present embodiment, sets of slots are defined in the same manner described in U.S. Patent No. 3,851,104, i.e., first slot number and slot spacing. In alternative embodiments, different time slot set designations may be utilized. The present embodiment is a dual mode system wherein a first set of the BIU/subscriber device pairs (referred to below as static slot terminals) have relatively static slot assignments where a set of slots may be uniquely assigned to a single BIU. The remaining BIU/subscriber device pairs (referred to below as contention slot terminals) have contention slot assignments where one or more slots may be assigned to a plurality of BIU's, each of which must contend for those slots. In the dual mode embodiment, time slots in a ~irst predetermined (or static) set in the repetitive framed sequence are available for static slot assignment, e.g. to high duty cycle subscribers. The remaining time slots form a second (or contention) set and are available for assignment to a plural-ity of BIUIs on a contention basis, and thus are well suited or subscribers whose messages are characteri~ed by a high peak-to-average transmission rate, i.e. bursty subscribers with low duty 1~ cycle. A single BIU/subscriber device pair may act as a network controller and control the ratio of static to contention slots for the system. In alternative embodiments, this ratio ma~ be ~ixed. In still other embodiments, e.gO single mode systems, all slots may be contention slots, or all slots may be static slots.
The static slot terminals are adapted to transmit signals in the static set of time slots. For the static slot terminals, the particular time slots of the static set in which any particular BIU may transmit may be varied. In addition, the right to transmit in such slots may be allocated and re~
29 allocated to various static slot terminals throughout the system.
~ypically, for high duty cycle subscribers, such as computers, the slot assignment is static, i.e. dedicated and time invariant However, the static assignment can be changed by inter~terminal communication, for example, in response to a terminal-initiated request for a higher data rate, or Easter mean time of access to the bus. In the present embodiment, such requests are pro-cessed in substantially the same manner as in the incorporated reference.
In addition to providing variations in static slot assignment by a single "central control" terminal, as in U.S.
1 Patent No. 3,851,104, the present embodiment also provides at least one terminal from the set of static slot terminals which may allocate the capability to vary the communication links.
This terminal may transmit an addressed control type slot signal, where the control data is representative of a primary slot allocation signal. This primary slot allocation signal includes data representative of the identity of one or more time slo-ts in the static set in which the addressed terminal may transmit signals on the inbound bus 10, or which that addressed terminal may sub-allocate to other static slot terminals. The addressed terminal may subsequentl~ transmit control type slot signals, with control data representative of secondary slot allocation signals which are addressed to one or more of the remaining other terminals. The secondary allocation signals may identify other time slots from the static set in which the remaining other terminals may transmit addressed control or message signals on th~ inbound bus 10, or may further sub~allocate those other slots. Accordingly, the various subscribers may allocate and sub-allocate various ones of the static slots, thereby permitting the modifica~ion of a static slot assignment for the respective static slot terminals on a distri~uted basis over the system.
The basic time slot format is illustrated in Fig. 2 for the present system~ where the system data rate is 7.3728 Mbps with 16,384 slots per frame, and 384 bits per slot, 5~ micro-seconds per slot and .8533 seconds per frame. As shown in Fig. 2, each slot includes 16 bit guard words at the beginning and end to accommodate minor timing errors~ An 8 bit message syn-chronization word (00001011) follows the ~irst guard word, and is utilized by the BIU's for synchronization purposes in a con~
3~ ventional manner. The following 8 bit word is representative 1 of a message type code. The next two 16 bit words are repre-sentative of the destination address and originator address, respectively for the time slot~ Following these address words, is a 48 bit field dependent on message type, and a 256 bit data field. The slot formats are described more fully below in conjunction with Figs. llA-E.
Fig. 3 illustrates the digital bus repeater (DBR) 26 in block diagram form. The repeater 26 is coupled between the buses 10 and 12 and operates to regenerate data received rom bus 10 and retransmit that data on bus 12 with new timing and interleaved with a frame synchronization slot signal. DBR 26 further includes a network for detecting when slot signals from two or more terminals occupy a sinyle slot on bus 10, and for inhibiting the transfer of slot signals from bus 10 to bus 12 when a collision is detected. In addition, DBR 26 includes a network for generating retransmission message siynals (repre-sentative of a retransmission parameter, RTP) and transmitting those signals on the outbound bus 12.
The signals from bus 10 are applied to a demodulator (and timing/data regenerator) 32 to extract baseband data and timing signalsO The regenerated data signal is transferred to a dual buffer data memory 34. The signals from bus 10 are also applied to collision detection network 35. Network 35 includes carrier detector 36 and multiple reception detector 37. Detec~ !
tor 36 monitors the amplitude of the incoming carrier from bus 10. If there is a carrier level change during a slot period (which would result from interference of two or more carrier signals from different but simultaneously transmitting BIU's) a simultaneous transmission, ox collision, condition is identified by block 37 and a control signal representative of that condition ~ J~
1 is transferred to a connector control 38.
DBR 26 also includes a frame sync generator 42 and associated dual buffer memory 43 and an RTP generator 44 and associated dual buffer memory 45. Blocks 42 and 43 and blocks 44 and 45 generate and store frame synchronization words and retransmission parameter works, respectively.
The memories 34, 43 and 45 are coupled by a select switch 40 to a modulator 46 and in turn to the outbound bus 12.
The connector control 38 establishes the slot count ~or the out-bound bus 12 and controls the operation of switch 40 so thatslot signals are transmitted on bus 12 with a one slot de3ay relative to the inbound bus 10. Switch 40 is controlled to peri-odically apply a frame synchronization word (from memory 43) to modulator 46. When there are no collisions detected, switch 40 operates to transfer a data slot signal from memory 34 to modu-lator 46 in the slot on bus 12 corresponding to the slot on bus 10 in which the respective data slot signal was received. When a collision is detected for a slot, no data signal is trans-ferred for the corresponding outhound bus 12 slot. Control 38 also periodically controls switch 40 to generate retransmitmessage signals (from the retransmit parameter stored in memory 45) which are used by contention terminals (as described more fully below) to control the selection of retransmission in the event of collisions. Control 38 also keys modulator 46 so that the carrier level is low for the first bit of the synchroniza-tion word of each slot.
While in the present embodiment the control 38~ re-transmission parameter generator 44 and memory 45 are all located at DBR 26, those e]ements in alternative embodiments may 3~ be located elsewhere along buses 10 and 12, and coupled to those ~ 13 -3~
1 buses by a BIU, or may be remotely located but coupled by dedicated communications channels.
In the present embodiment, BIU 20 is shown in hlock diagram form in Fig. 4. The other BIU's in the present en~odi-ment are substantially similar to BIU 20 and thus are not des-cribed further. BIU 20 includes modem 50 having modulator 52 and demodulator 54 for coupling the associated subscriber termi.nal 14 to buses 10 and 12 by way of control l.ogi.c 56 and input/
output (I/o) logic 58. Control logic 56 establishes and main-tains synchronization both with the outbound bus 12 and inboundbus 10, permitting the receptinn and demultip].exing of messages from bus 12 according to bit patterns in predefined locati.ons within each time slot, and permitting the multiplexing o~ messages in the proper time slots on bus 10. I~0 logic 58 provides electrical and operational compatibi.lity (e.g. voltage levels, circuit resistance, and the like) between the BIU 20 and sub-scriber terminal 14. For operational compatibility, BIU 20 supports the mode and data ra~e at which the subscri~er terminal 14 operates, provides serial or parallel data transfers as required, and the "hand shaking" lines required by terminal 14.
In the present embodiment, the modem 50 is an FM/FSK
network which opera es at a center frequency of 45 MHz. The modulation index is approximately one and the transmitted signal occupies a bandwidth of 20 MHz. Modulator 52 is shown in detailed block diagram form in Fig~ 5. The modulator 52 converts a 7.3728 Mbps input serial data stream from the control.logic 56 into an FM/FSK signal centered at 45 MHz. The modulator includes level converter 62, FM oscillator 64, level converter 66, RF amplifier 68 and band-pass filter (BPF) 70 configured 3~ in a conventional manner. Modulator 52 transmits a signal during active conditions of the transmit key signal from control logic 56.
The demodulator 54 is shown in detailed block diagram form in Fig. 6. Demodulator 54 comprises band-pass filter 72, RF amplifier 74, FM demodulator 76, timing regenerator 78, carrier detector 80 and message synchronization detector 82, all configured in a conventional manner to demodulate the received RF data from bus 12 and transform that data into signals representative of the received timing, and received data, and apply these signals to the control logic 56. The message syn-chronization detector 82 provides a received start-of-message (RSOM) signal to the control logic 56 in response to detection of the 8 blt message synchronization word in each time slot.
In operation, the signal from amplifier 74 is applied to carrier detector 80 to detect carrier presence and FM demodu-lator 76 to recover the data stream. After level resto~ation, the data signal from demodulator 76 is processed further by timing regenerator 78 and detector 82. During the synchroniza-tion word period, edges of the received data signals are used to
. .
The f.ield of this invention is communica-tions systems, and more particularly, time division multiple access digital bus communications systems~
There.are many forms of multiple access communications systems known in the art, including for example the time division system disclosed in U.S. Patent No. 3,851,104. These systems, basically provide an information bus for transferring digital message signals between remote terminals. In the prior art 1~ systems J there are a number of protocols u-tilized to accommodate the various terminals in the network and provide them with access to a communications bus. Such protocols include simple polling, priority request, contention~ and cyclic time division with fixed slot allocations.
In the polling type systems, a central controller sequentially polls each of the remote terminals, offeri~g each an opportunity to ac~ess the communications bus when available.
In priority request systems, remote terminals ready to transmit a message make a request, and are granted access to the bus according to priorities established by a bus arbiter at a central controller. In contention systems, remote terminals may transmit messages at random times, monitor the signals on the bus, and subsequently re-transmit tn the event two or more simultaneous transmissions are detected.
The polling and priority request approaches have been applied to time division systems in the prior art whereby a central terminal controls the bus access. However, such systems are typically characterized by a rigid formating of messages and an inflexible set of system constraints controlling the time periods at which the various remote terminals may ga.in access to ~.
1 the communication pathO In addition, the various data rates at which the individual remote terminals may transmit message signals are hard-wired into the systems to define predetermined portions of the channel bandwidth which are allocated to each of the remote terminals.
The cyclic time division systems, including that dis~
closed in U.S. Patent No. 3,851,104 dedicate regularly occurrin~
time slots in a repetitive framed sequence to specific users for their transmissions, and hence, may be referred to as a fixed slot allocation system. In the system described in U.S. Patent No. 3,851r104 the slot allocations may be tailored somewhat to specific user requirements through the procedure whereby remote terminals may request certain portions of the bus spectrum in predetermined access request time slots. In this system, a central controller then allocates families of message time slots to the requesting terminals in accordance with various parameters, such as predetermined priorities, time slot availabilities, and the like.
The system described in U.S. Patent No. 3,851,10~
overcomes these disadvantages to a large extent by permitting dynamic allocation of time slots in order to accommodate desired access time and data rate variations. However, in the referenced systems, all the control is achieved at a central terminal, which must control bus access and link formation for the entire system.
Consequently, the level of complexity for that control terminal is relatively high. In addition, outage of that central terminal causes failure of the entire system.
Typically, in operating environments, a system is required to accommodate high duty cycle subscribers, low duty cycle subscribers, and combinations of both. The high duty cycle ~ 3~
1 subscrihers, such as inter-computar lin]cs, have generally been accommodated in the prior art by the cyclic time division systems wherein the various subscribers are assigned fixed slot alloca-tions in the repetitive time framed time sequence on the bus4 The low duty cycle, or bursty, subscribers, such as communications terminals, have been accommodated in the prior art by unslotted contention type systems, where the entire bus bandwidth is allocated to a single subscriber. Although these types of systems are specifically tailored for the particular types of subscribers, neither system type optimally accommodates both high and low duty cycle subscribers.
~ ccordingly, it is an object of the present invention to provide a time division multiple access communications system in which control of bus access and communication link formation is distributed over a plurality of terminals in the system.
It is another object to provide,a time division multiple access communications system in which subscriber terminals contend for transmission time slots.
A further object is to provide a time ~iviaion multiple access communications system which accommodates both high and low duty cycle subscribers by controlling slot allocations and contention slot transmissions~
SUMMARY OF THE IN~ENTION
Briefly, the present invention provides a time division multiple access communications system including a plurality of terminals coupled to a co~mon signal path, or bus. Communication links are established over the path between one or more of the terminals wherein digital signals may be transferred in time slots in a repetitive ~ramed sequence between linked terminals.
In one form of the invention, selected time slots within ~L~3~
1 the framed sequence are allocated on a relatively static basis to various requesting terminals to establish the lin~. In accordance with the invention, the slot allocation function may be distributed over th~ entire system, wherein at least one terminal having the slot allocation capability may address selected other terminals and allocate that slot allocation capability among those selected other terminals. Thereafter, the signal path bandwidth may be effectively allocated by either the primar~ terminal or the selected other terminals, permitting a flexible, dynamic allocation of the system bandwidth. The primary slot allocating terminal may accordingly address selected ones of - the other terminals, and may transfer data to those terminals representative of the identity of an allocated one or more unused time slots which may be allocated by those selected terminals to the various other terminals coupled to the path. In this form, the administration workload for the s~stem may be distributed so that no single terminal is required to perform all of the bus access control functions. The system may efficiently accommodate relatively high usage and priority subscriber terminals with a desired portion of the signal path bandwidth, while controlling the mean time to access the signal path for the remaining terminalsO
In a second form, the present invention provides a slotted time division system wherein the various subscriber terminals contend for access to the signal path. In this form, the common signal path includes one or more pairs- of oppositely directed unidirectional signal paths connecting each o~ the terminals. A connector network at a central location is adapted to receive signals from time slots along the paths inbound ~o that connector, and to txansfer those signals to the paths 1 outbound from that connector network in corresponding time slots associated with that outbound path. The entire signal path band-width is allocated to a single terminal at a time. Each terminal with this contention capability is operative to transmit a message signal in the slots on the inbound path, and then monitors the outbound path to detect the presence of that transmitted signal.
The connector detects signal collisions (from two or more terminals) in the various time slots on the inbound path, and when such a collision is detected, the connector network inhibits the transfer of signals from the inbound path to the outbound path. Thus, when a collision is de-tected, no slot ; signal is transferred to the outbound path and the transmitting terminal is unable to confirm that its transmission was success-ful ~i.e avoided collision). In this con-figuration, the con-nector also includes a retransmit tirne signal generator for transmitting on the out~ound path signals addressed to the various remote terminals and including data for controlling the selection of a re-transmission time slot by the trans-mitting terminal. The transmitting terminal is responsive to that signal to select a subsequen~ time slot for commencing the re-transmission of the message. The process repeats un~il the transmitting terminal gains access (wit11out collision1 to the signal path. This second form of the invention is particularly well suited to low duty cycle, or bursty, subscriber terminals.
In a third form of the invention, a dual mode communi cation system is provided wherein certain of the time slots on the signal path are controlled for use in dynamic allocation operation with relatively static slot assignments (in conjunction with a set of terminals adapted for dynamic allocation) in the .
1 manner descrlbed above for the first form of the invention, and a second set of time slots in the signal path are adapted to be used by -terminals operating in accordance with the contention form of the invention described above. In this third form, the ratio of use of time slots between the allocation and contention mode of operation may be adaptively controlled in the form of the number of time slots allocated for each unction~ or by means of the mode of operation for the various termlnals and ratio of such terminals connected to the system. In this third form, the dual mode system may be dynamically varied to accommodate any desired current usage of both bursty (low duty cycle) and long-~ term (high duty cycle) subscriber terminals. Typically, computers ; are high duty cycle users and receive dedicated slot assign-ments which may be varied according to priorities through the allocation of ~he varying numbers of slots per frame to the par-ticular terminals. Low duty cycle or bursty users, like communi-.~
cation terminals, are each given the same slot assignments and ` contend for transmission in that set of slots. In this third form, each type of subscriber may communicate with any subscriber of either type since the data message formats are identical.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects of this invention, the various features thereof, as well as the invention itself, may be more fully understood from the following description, when read together with the accompanying drawings in which:
Fig. 1 shows in block diagram form a communications system in accordance with the invention;
Fig. 2 shows the general message signal format for the system of Fig. 1;
- Fig. 3 shows in block diagram form an exemplary embodiment of a digital bus repeater for the system of Fig. 1;
Fig. 4 shows in block diagram form an exemplary embodiment of the bus interface unit ~BIU) o~ the system of Fig. l;
Fig. 5 shows in block diagram form an exemplary embodiment of the modulator of the BIU oE Fig. 4;
Fig. 6 shows in block diagram form an exemplary embodiment of the demodulator of the BIU of Fig~ 4;
Fig. 7 shows in block diagram form an exemplary embodiment of the control logic of the BIU of Fig. 4;
Fig. 8 shows in block diagram form an exemplary embodiment of the microcontroller of the control logic of Fig. 7;
Fig. 9 shows the instruction format for the micro-controller of Fig. 8;
Fig. 10 shows the operational cycle for microcontroller of Fig~ 8;
Figs llA-E show exemplary message signal formats for use with the system of Fig. l;
Fig, 12 shows in block diagram form an exemplary embodiment for the input/output logic of the BIU of Fig. 4.
DESCRIPTION OF THE PREFERRED ~MBODIMENT
A high speed time division multiple access (TDMA) digital comrnunications system is shown in block diagram form in Fig. 1. The system includes a common si~nal path comprisin~
inbound bus 10 and outbound bus 12, and a set of addressed sub-scriber devices coupled to the buses 10 and 12. As shown, the set includes subscriber devices 14, 16 and 18. Each sub-scriber device is coupled to both inbound bus 10 and outbound bus 12 by a respective one of bus interface units (BIU's) 20, 22 1 and 24. In alternative embodiments, a plurality of subscriber devices may be coupled to the bus by each of the BIU's, and different numbers of subscribe.r devices and associated BIU's may be coupled to the buses~ The present system is adap-ted to pro-vide a transfer of digital signals between subscriber devices coupled to the common signal path in one or more time slots in a repetitive framed sequence.
In the present embodiment, the inbound bus 10 and out-bound bus 12 comprise oppositely-directed unidirectional digital signal paths coupled at a system head-end by a digital bus re-peater (DBR) 26. By way of example, the inbound bus 10 and outbound bus 12 may be separate channels on a conventional wide-band distribution system, such as a ~wo cable television (CATV) . trunk/feeder network. In alternative embodiments, the common signal path may comprise a bidlrectional signal path coupling each of the subscriber devices.
Each BIU is adapted to transmit a serial bit stream in selected time slots on the inbound bus 10, and to recei~e a continuous serial bit stream from the outbound bus 12. The BIU's provide access to the data bus for their associated devlces and establish electrical and functional capabilities between the buses and the respective subscribers.
The data bus repeater (DBR) 26 is a connector network which receives inbound da-ta on bus 10, retimes and reformats such data with a one slot delay, and retransmits it under control of a master clock onto the outbound bus 12. The retransmitted data is available for reception by all BIU's coupled to bus 12.
In operation, the buses carry digital signals in tlme slots in the repetitive framed sequence. As described more fully belowr the time slot signals may be either of two types, control - 8 ~
~ or message. Control type signals transfer control data between - BIU's which is processed to establish various control functions for the system (such as monitoring status, or establishing a communication link between terminals). Message type signals transf~r message data between terminals, generally for inter-subscriber communication purposes. In general, in addition to the control or message data, each signal on bus 12 includes an originating terminal address, a desired destination terminal addr~ss, and a data word indicative of the type, i.e. either control or message.
~ ach BIU coupled to bus 12 continuously monitors the data slots on that bus, examining various data fields in -those slots for type and other information, e.g. destination address.
In general, if an address is detected which matches that of its, or one of its, associated terminals, the BIU either transfers the message data to the terminal (when the slot signal is a data type), or processes the control data internally (when the slot is a control type).
Each BIU may be assigned a set of slots in the framed sequence for the transmission of time slot signals on the inbound bus 10. In the present embodiment, sets of slots are defined in the same manner described in U.S. Patent No. 3,851,104, i.e., first slot number and slot spacing. In alternative embodiments, different time slot set designations may be utilized. The present embodiment is a dual mode system wherein a first set of the BIU/subscriber device pairs (referred to below as static slot terminals) have relatively static slot assignments where a set of slots may be uniquely assigned to a single BIU. The remaining BIU/subscriber device pairs (referred to below as contention slot terminals) have contention slot assignments where one or more slots may be assigned to a plurality of BIU's, each of which must contend for those slots. In the dual mode embodiment, time slots in a ~irst predetermined (or static) set in the repetitive framed sequence are available for static slot assignment, e.g. to high duty cycle subscribers. The remaining time slots form a second (or contention) set and are available for assignment to a plural-ity of BIUIs on a contention basis, and thus are well suited or subscribers whose messages are characteri~ed by a high peak-to-average transmission rate, i.e. bursty subscribers with low duty 1~ cycle. A single BIU/subscriber device pair may act as a network controller and control the ratio of static to contention slots for the system. In alternative embodiments, this ratio ma~ be ~ixed. In still other embodiments, e.gO single mode systems, all slots may be contention slots, or all slots may be static slots.
The static slot terminals are adapted to transmit signals in the static set of time slots. For the static slot terminals, the particular time slots of the static set in which any particular BIU may transmit may be varied. In addition, the right to transmit in such slots may be allocated and re~
29 allocated to various static slot terminals throughout the system.
~ypically, for high duty cycle subscribers, such as computers, the slot assignment is static, i.e. dedicated and time invariant However, the static assignment can be changed by inter~terminal communication, for example, in response to a terminal-initiated request for a higher data rate, or Easter mean time of access to the bus. In the present embodiment, such requests are pro-cessed in substantially the same manner as in the incorporated reference.
In addition to providing variations in static slot assignment by a single "central control" terminal, as in U.S.
1 Patent No. 3,851,104, the present embodiment also provides at least one terminal from the set of static slot terminals which may allocate the capability to vary the communication links.
This terminal may transmit an addressed control type slot signal, where the control data is representative of a primary slot allocation signal. This primary slot allocation signal includes data representative of the identity of one or more time slo-ts in the static set in which the addressed terminal may transmit signals on the inbound bus 10, or which that addressed terminal may sub-allocate to other static slot terminals. The addressed terminal may subsequentl~ transmit control type slot signals, with control data representative of secondary slot allocation signals which are addressed to one or more of the remaining other terminals. The secondary allocation signals may identify other time slots from the static set in which the remaining other terminals may transmit addressed control or message signals on th~ inbound bus 10, or may further sub~allocate those other slots. Accordingly, the various subscribers may allocate and sub-allocate various ones of the static slots, thereby permitting the modifica~ion of a static slot assignment for the respective static slot terminals on a distri~uted basis over the system.
The basic time slot format is illustrated in Fig. 2 for the present system~ where the system data rate is 7.3728 Mbps with 16,384 slots per frame, and 384 bits per slot, 5~ micro-seconds per slot and .8533 seconds per frame. As shown in Fig. 2, each slot includes 16 bit guard words at the beginning and end to accommodate minor timing errors~ An 8 bit message syn-chronization word (00001011) follows the ~irst guard word, and is utilized by the BIU's for synchronization purposes in a con~
3~ ventional manner. The following 8 bit word is representative 1 of a message type code. The next two 16 bit words are repre-sentative of the destination address and originator address, respectively for the time slot~ Following these address words, is a 48 bit field dependent on message type, and a 256 bit data field. The slot formats are described more fully below in conjunction with Figs. llA-E.
Fig. 3 illustrates the digital bus repeater (DBR) 26 in block diagram form. The repeater 26 is coupled between the buses 10 and 12 and operates to regenerate data received rom bus 10 and retransmit that data on bus 12 with new timing and interleaved with a frame synchronization slot signal. DBR 26 further includes a network for detecting when slot signals from two or more terminals occupy a sinyle slot on bus 10, and for inhibiting the transfer of slot signals from bus 10 to bus 12 when a collision is detected. In addition, DBR 26 includes a network for generating retransmission message siynals (repre-sentative of a retransmission parameter, RTP) and transmitting those signals on the outbound bus 12.
The signals from bus 10 are applied to a demodulator (and timing/data regenerator) 32 to extract baseband data and timing signalsO The regenerated data signal is transferred to a dual buffer data memory 34. The signals from bus 10 are also applied to collision detection network 35. Network 35 includes carrier detector 36 and multiple reception detector 37. Detec~ !
tor 36 monitors the amplitude of the incoming carrier from bus 10. If there is a carrier level change during a slot period (which would result from interference of two or more carrier signals from different but simultaneously transmitting BIU's) a simultaneous transmission, ox collision, condition is identified by block 37 and a control signal representative of that condition ~ J~
1 is transferred to a connector control 38.
DBR 26 also includes a frame sync generator 42 and associated dual buffer memory 43 and an RTP generator 44 and associated dual buffer memory 45. Blocks 42 and 43 and blocks 44 and 45 generate and store frame synchronization words and retransmission parameter works, respectively.
The memories 34, 43 and 45 are coupled by a select switch 40 to a modulator 46 and in turn to the outbound bus 12.
The connector control 38 establishes the slot count ~or the out-bound bus 12 and controls the operation of switch 40 so thatslot signals are transmitted on bus 12 with a one slot de3ay relative to the inbound bus 10. Switch 40 is controlled to peri-odically apply a frame synchronization word (from memory 43) to modulator 46. When there are no collisions detected, switch 40 operates to transfer a data slot signal from memory 34 to modu-lator 46 in the slot on bus 12 corresponding to the slot on bus 10 in which the respective data slot signal was received. When a collision is detected for a slot, no data signal is trans-ferred for the corresponding outhound bus 12 slot. Control 38 also periodically controls switch 40 to generate retransmitmessage signals (from the retransmit parameter stored in memory 45) which are used by contention terminals (as described more fully below) to control the selection of retransmission in the event of collisions. Control 38 also keys modulator 46 so that the carrier level is low for the first bit of the synchroniza-tion word of each slot.
While in the present embodiment the control 38~ re-transmission parameter generator 44 and memory 45 are all located at DBR 26, those e]ements in alternative embodiments may 3~ be located elsewhere along buses 10 and 12, and coupled to those ~ 13 -3~
1 buses by a BIU, or may be remotely located but coupled by dedicated communications channels.
In the present embodiment, BIU 20 is shown in hlock diagram form in Fig. 4. The other BIU's in the present en~odi-ment are substantially similar to BIU 20 and thus are not des-cribed further. BIU 20 includes modem 50 having modulator 52 and demodulator 54 for coupling the associated subscriber termi.nal 14 to buses 10 and 12 by way of control l.ogi.c 56 and input/
output (I/o) logic 58. Control logic 56 establishes and main-tains synchronization both with the outbound bus 12 and inboundbus 10, permitting the receptinn and demultip].exing of messages from bus 12 according to bit patterns in predefined locati.ons within each time slot, and permitting the multiplexing o~ messages in the proper time slots on bus 10. I~0 logic 58 provides electrical and operational compatibi.lity (e.g. voltage levels, circuit resistance, and the like) between the BIU 20 and sub-scriber terminal 14. For operational compatibility, BIU 20 supports the mode and data ra~e at which the subscri~er terminal 14 operates, provides serial or parallel data transfers as required, and the "hand shaking" lines required by terminal 14.
In the present embodiment, the modem 50 is an FM/FSK
network which opera es at a center frequency of 45 MHz. The modulation index is approximately one and the transmitted signal occupies a bandwidth of 20 MHz. Modulator 52 is shown in detailed block diagram form in Fig~ 5. The modulator 52 converts a 7.3728 Mbps input serial data stream from the control.logic 56 into an FM/FSK signal centered at 45 MHz. The modulator includes level converter 62, FM oscillator 64, level converter 66, RF amplifier 68 and band-pass filter (BPF) 70 configured 3~ in a conventional manner. Modulator 52 transmits a signal during active conditions of the transmit key signal from control logic 56.
The demodulator 54 is shown in detailed block diagram form in Fig. 6. Demodulator 54 comprises band-pass filter 72, RF amplifier 74, FM demodulator 76, timing regenerator 78, carrier detector 80 and message synchronization detector 82, all configured in a conventional manner to demodulate the received RF data from bus 12 and transform that data into signals representative of the received timing, and received data, and apply these signals to the control logic 56. The message syn-chronization detector 82 provides a received start-of-message (RSOM) signal to the control logic 56 in response to detection of the 8 blt message synchronization word in each time slot.
In operation, the signal from amplifier 74 is applied to carrier detector 80 to detect carrier presence and FM demodu-lator 76 to recover the data stream. After level resto~ation, the data signal from demodulator 76 is processed further by timing regenerator 78 and detector 82. During the synchroniza-tion word period, edges of the received data signals are used to
2~ phase a receive clock within regenerator 78 so that negative transitions of the clock signal will occur in the center of data bits. The data is then entered into a 2-bit shift register where the first presence of two adjacent ones after a positive transition of carrier level causes the generation of the RSO~I
pulse.
The control logic 56 of a BIU is shown in detailed form in Fig. 7, and includes receiver 92, transmitter 9~, buffer memories 96 and 98, header buffers 100 and 102, message sync (MSYI~C) network 104, pseudo random number generator 108, and bit count control 110, all coupled to a microcontroller 112 by 1 control and status lines. The header buffers 100 and 102 include forty-eight 16 bit words of random access memory con-trolled by microcontroller 112. In Fig. 7, the double line arrows are representative of data buses and the single line arrows are representative of control and status lines.
In operationl the serial data received from the demodu-lator 54 is converted into 8 or 16-bit words by the receiver 92.
All of the 8-bit words of each slot on the bus 12 are stored in one of the two buffers (IN Mem A or IN Mem B) of 10 buffer memory ~6. The availability of these buffers is con-trolled by a BIU register control in I/O logic 58, as described more fully below. The first seven 16-bit words comprise the header portion of every received slot, and are also stored in the input header buffer 100 for processing by the microcon-troller 112~ MSYNC network 104 maintains message synchronization in a conventional manner and the bit count control 110 includes receive and transmit bit counters.
The transmitter 94 controls the transmission of messages in the assigned slots. The data for transmission is obtained from the output header buffer 102 and the buffers (OUT
Mem ~ or OUT Mem ~ of memory 98. The data in the output header buffer 102 is generated by the microcontroller 112 while the I/O logic 58 loads the OUT Mem A and OUT Mem B data. In the present embodiment, the header portion of a transmit slot is generated by control logic 56, except guard hits, message syn~
chronization code, and the twelve mos-t significant bits of the originator's address. Alternatively, the header portion may be generated by I/O logic 58.
The pseudo random number generator 108 consists of a free running counter that provides a 16-bit number to the ~3c~
1 microcontroller 112 (to be used for random de.lay for retransmis-sion in contention slots).
The microcontroller 112 is a microprocessor based module that controls the operation of the control logic 56 and is shown in detailed form in Fig. 8. In the present embodiment, microcontroller 112 includes an array 120 of four 4-bit micro~
processor slices (four Advanced Micro Devices Type AMD2901 units), sequence controller 122 (Signetics Type 8X02), instruction PROM 124 (eight Signetics Type 82S131 units) programmed as set forth in Appendix I, instruction decoder 126 (Signetics Type 74S series logic units), multiplexer 128 (four Signetics Type 82S129 units), multiplexer 130 (three Signetics Type 935151 units), and message type decode PROM 132 (two Signetics Type 82S129 units). The microcontroller 112 is conventionally con-figured so that each instruction may be executed in one 320 nanosecond cycle. The data words are 16-bits wide and the instructions are 32-bits wide. The instruction storage in this configuration has a maximum of 512 32-bit instructions and is expandable to 1024, if required. The microcontroller 112 includes sixteen 16-bit registers on the microprocessor slices.
With this confiyuration, in operation, the instruction from the instruction PROM 124 is decoded by the instruction decoder 126 which generates all the commands and the control signals for blocks 92, 94, 96, 98, 100, 102~ 104, 108 and 110.
The instruction decodex 126 also provides the immediate data and the branch address for immediate and branch instructions, respectively. The microprocessor array 120 performs the arithmetic and the logic functions on the contents of internal general registers. The general registers may be loaded with the immediate data or the data read in from the header buffer 100.
1 The array 120 generates a 16-bit data word and a 3~bit status word as a result of a processor arithmetic/logic function.
The output data word is loaded into the header buffer 102 under control of the instruction decoder 126. The status word and the branch address is used by the sequence controller 122 to generate the next instruction address~ The branch address may be the output of the message type decode PROM 132 or may be provided by the instruction. The decode PROM 132 consists of branch addresses to subroutines to process different received message t~pes as determined from the 8-bit message type word in the header field provided by header buffer 100 for a slot.
The 32-bit instructions executed by the microcontrollar 112 are divided into five groups having the format shown in Fig. 9. Group I instructions are register-to-re~ister instruc-tions. The next instruction is skipped if the test condition is satisfied and the instruction is a command for rest of the con trol logic 56 (e.g. enable transmit), Group II instructions are register-to-register instructions with a branch to an address given in the instruc~ion or the I/O vector if the test condition is satisfied. Group III instruc~ions are immediat~ instructions wherein the sixteen least significant bits include immediate data. Group ~V instructions enable the microprocessor ~rray 1~0 to rea~ a 16-bit word from the receive header buf~er 100, into one of its general registers~ ~ skip may also be executed if the test condition is satisfied. Group V instructions are register-to-register instructions in which the processor output may be written into a storage device such as the transmit header buf~er. ~ skip may also be executed if the test condition is
pulse.
The control logic 56 of a BIU is shown in detailed form in Fig. 7, and includes receiver 92, transmitter 9~, buffer memories 96 and 98, header buffers 100 and 102, message sync (MSYI~C) network 104, pseudo random number generator 108, and bit count control 110, all coupled to a microcontroller 112 by 1 control and status lines. The header buffers 100 and 102 include forty-eight 16 bit words of random access memory con-trolled by microcontroller 112. In Fig. 7, the double line arrows are representative of data buses and the single line arrows are representative of control and status lines.
In operationl the serial data received from the demodu-lator 54 is converted into 8 or 16-bit words by the receiver 92.
All of the 8-bit words of each slot on the bus 12 are stored in one of the two buffers (IN Mem A or IN Mem B) of 10 buffer memory ~6. The availability of these buffers is con-trolled by a BIU register control in I/O logic 58, as described more fully below. The first seven 16-bit words comprise the header portion of every received slot, and are also stored in the input header buffer 100 for processing by the microcon-troller 112~ MSYNC network 104 maintains message synchronization in a conventional manner and the bit count control 110 includes receive and transmit bit counters.
The transmitter 94 controls the transmission of messages in the assigned slots. The data for transmission is obtained from the output header buffer 102 and the buffers (OUT
Mem ~ or OUT Mem ~ of memory 98. The data in the output header buffer 102 is generated by the microcontroller 112 while the I/O logic 58 loads the OUT Mem A and OUT Mem B data. In the present embodiment, the header portion of a transmit slot is generated by control logic 56, except guard hits, message syn~
chronization code, and the twelve mos-t significant bits of the originator's address. Alternatively, the header portion may be generated by I/O logic 58.
The pseudo random number generator 108 consists of a free running counter that provides a 16-bit number to the ~3c~
1 microcontroller 112 (to be used for random de.lay for retransmis-sion in contention slots).
The microcontroller 112 is a microprocessor based module that controls the operation of the control logic 56 and is shown in detailed form in Fig. 8. In the present embodiment, microcontroller 112 includes an array 120 of four 4-bit micro~
processor slices (four Advanced Micro Devices Type AMD2901 units), sequence controller 122 (Signetics Type 8X02), instruction PROM 124 (eight Signetics Type 82S131 units) programmed as set forth in Appendix I, instruction decoder 126 (Signetics Type 74S series logic units), multiplexer 128 (four Signetics Type 82S129 units), multiplexer 130 (three Signetics Type 935151 units), and message type decode PROM 132 (two Signetics Type 82S129 units). The microcontroller 112 is conventionally con-figured so that each instruction may be executed in one 320 nanosecond cycle. The data words are 16-bits wide and the instructions are 32-bits wide. The instruction storage in this configuration has a maximum of 512 32-bit instructions and is expandable to 1024, if required. The microcontroller 112 includes sixteen 16-bit registers on the microprocessor slices.
With this confiyuration, in operation, the instruction from the instruction PROM 124 is decoded by the instruction decoder 126 which generates all the commands and the control signals for blocks 92, 94, 96, 98, 100, 102~ 104, 108 and 110.
The instruction decodex 126 also provides the immediate data and the branch address for immediate and branch instructions, respectively. The microprocessor array 120 performs the arithmetic and the logic functions on the contents of internal general registers. The general registers may be loaded with the immediate data or the data read in from the header buffer 100.
1 The array 120 generates a 16-bit data word and a 3~bit status word as a result of a processor arithmetic/logic function.
The output data word is loaded into the header buffer 102 under control of the instruction decoder 126. The status word and the branch address is used by the sequence controller 122 to generate the next instruction address~ The branch address may be the output of the message type decode PROM 132 or may be provided by the instruction. The decode PROM 132 consists of branch addresses to subroutines to process different received message t~pes as determined from the 8-bit message type word in the header field provided by header buffer 100 for a slot.
The 32-bit instructions executed by the microcontrollar 112 are divided into five groups having the format shown in Fig. 9. Group I instructions are register-to-re~ister instruc-tions. The next instruction is skipped if the test condition is satisfied and the instruction is a command for rest of the con trol logic 56 (e.g. enable transmit), Group II instructions are register-to-register instructions with a branch to an address given in the instruc~ion or the I/O vector if the test condition is satisfied. Group III instruc~ions are immediat~ instructions wherein the sixteen least significant bits include immediate data. Group ~V instructions enable the microprocessor ~rray 1~0 to rea~ a 16-bit word from the receive header buf~er 100, into one of its general registers~ ~ skip may also be executed if the test condition is satisfied. Group V instructions are register-to-register instructions in which the processor output may be written into a storage device such as the transmit header buf~er. ~ skip may also be executed if the test condition is
3~ satisfied.
~3~7 ~i~
1 The instruction execution time is 320 ~anoseconds.
This execution time is divided into eight periods of 40 nano-seconds (shown in Fig. 10) during which four functions are per-formed. The four functions are denoted A, B, C or C* and D and are shown in Table I:
TABLE I
Function A - NEXT INSTRUCTION ADDRESS READY-START FETCH
Function B - INSTRUCTION READY
Function C - SET UP DATA AT PROCESSOR INPUT (EXCEPT READ M8-MO) Function C*- SET UP DATA AT PROCESSOR INPUT (READ M8-MO ONLY) E'unction D - PROCESSOR OUTPUT READY
When an instruction from the instruction PROM 124 is ready at TB, then that instruction is decoded in the time from TB to Tc. In the time from TC or Tc* to TD, the microprocessvr array 120 executes its command; and at TD, output data and status words from microprocessor array 120 are ready. In the time from TD
to TA, the sequence controller 122 determines the address for the next instruction to be executed. The instruction PROM 124 establishes the next instruction as ready during the time TA to TB.
The microprocessor includes sixteen 16-bit registers and each of these registers is assiyned a function in accordan~e with Table II:
~3~
1~ REGISTER 8 - SLOT NUMBER B
REGISTER 9 - TRANSMI~ SLOT N~MBER A
REGISTER A - SPACING PARAMETER A
REGISTER B - SLOT NUMBER A
REGISTER C - RETRANSMISSION PARAMETER
REGISTER D - CONTROL REGISTER
REGISTER E - TRANSMIT SLOT COUNTER
REGISTER F - RECEIVE SLOT COUNTER
Registers 6 through C are used for the transmit slot determination~ In the present embodiment, registers 7, 8, A, B
2n and C are preset to initial values at powe~ OIl, and may be up-dated by messages generated by a network controller. The retrans-mit parameter in register C is indicative oE a contention slot terminal and the desired mean time for retransmission of a slot signal following determination of a collision.
Register D has control information (e.g. synchroniza-tion).
Registers E and F maintain current slot counts. The value in register E is offset ~rom that in register F by a slot offset determined by the location of the particular BIU with respect to the Data Bus Repeater 26. Register E is used to determine transmit slot opportunit:ies and register F is used in the frame synchronization process.
Registers 0 through 4 are used as workîng registers by the microcontroller software. Register 5 holds the BIU address.
In addition to the sixteen general registers, the microprocessor array 120 includes a Q-register available to the software.
In operation of control logic S~, the message synchron-ization process is required to determine where the slots start lo and which bit is currently being receiYed. In achieving message synchronization, a continuousl~ runnin~ receive bit counter in MS~NC network 104 is reset by the first receive start-of-message signal (RSOM) after power on~ Control logic 56 is adapted so that a RSOM for every receive slot should occur in a six ~pro-grammable) bit window at the start of every slot as de-termined - by the receive bit counter. If three consecutive RSOM's occur when expected, then the message synchronization condition is established. In response to two missing RSOM's in sixteen con-secutive slots, network 104 establishes a loss of message synchro-nization condition and an interrupt is provided to microcontroller 112.
Following message synchronization, the frame synchron-ization process is initiated in order to determine the number of the slot being received and ide~tify transmit opportunities. In achieving frarne synchronization, the receive slo-t number is maintained by the microcontroller 112.
If the slot number from three consecutive frame syn-chronization messages matches with the receive slot number, then frame synchronization is estahlished and transmit is enabledO
3~ If the slot number from two-out-of si~teen consecutive 1 frame synchronization messayes does not match with the receive slot number, then a loss of frame synchronization is established and transmit is disabled.
Following the establishing of message synchronization condition, the control 56 then processes the slot signals received from the bus. Following the establishment of message synchronization, the control section 56 processes the data received from its associated subscriber terminals (through the interface provided by the I/O logic 58~.
1~ The slot formats for the present embodiment will now be described in detail in conjunction with Figs. llA-F. Fig. llA
shows the frame synchronization slot format. These slot siynals are generated by the data bus repeater 26 and are utilized by control logic 56 and the control to establish and maintain frame synchronization. Table III defines the words included for the frame synchronization slot forma~ of Fig. llA:
TABLE III
G = GUA~D BITS - ALL ZEROS
MS = MESSAGE SYNCHRONIZATION BITS = 10101011 MT = MESSAGE TYPE = 1016 SN = SLOT NUMBER
Fig. llB shows the broadest retransmission parameter (RTP~ slot format. These slot signals are generated by the network controller and are utili~ed by the control loyic 56 to update the retransmission parameter stored in the microprocessor array 120. This parameter is used in the retransmission process for contention slots. Table IV defines the words included for the RTP slot format of Fig. llB:
3~
G = GUARD BITS - ALL ZEROS
MS = MESSAGE SYNCHRONIZATION BITS = 00001011 MT = MESSA OE TYPE = 1116 OA = ORIGINATOR's ADDRESS
RTP = RETRANSMISSION PARAMETER
Fig. llC shows the transmit assignment slot format.
These slot signals are generated by the primary network con-troller or by a secondary network controller. When addressed to a BIU, the control logic 56 of that BIU updates the assigned transmit ; slot number, spacing parameter, and destination address currently i stored therein. Table V defines the words included in the transmit assignment slot format of Fig. llC:
TABLE V
G = ~UARD BITS - ALL ZEROS
MS = MESSAGE SYNCHRONIZATION BITS = 00001011 MT = MESSAGE TYPE = 416 FOR INDIVIDUAL STATUS SLOT ASSIGNMENT
= 4116 FOR CONTENTION STATUS SLOT ASSIG~ENT
= 4216 FOR INDIVIDUAL DATA SLOT ASSIGNMENT
. = 4316 EOR CONTENTION DATA SLOT ASSIGNMENT :
DA - DESTINATION ADD.RESS
OA = ORIGINATORIS ADDRESS
ASN = ASSIGNED SLOT NUMBER : :
ASP = ASSIGNED SLOT SPACING PARAMETER
ADA = ASSIGNED DESTINATION ADDRESS
Fig. llD shows the status slot format. These slot signals are generally generated by BIU's and addressed to BIIl's or a network controller. The status slot signals include data representative of the status of either the BIU or an associated subscriber terminal. Table VI defines the words included for ~he status slot format of Fig. llD:
~3~
TABLE VI
G - GUARD BITS - ALL ZEROS
MS = MESSAGE SYNCHRO~IZATION BITS = 00001011 MT -- MESSAGE TYPE = 316 DA = DESTINATION ADDRESS
OA = ORIGINATOR'S ADDRESS
DSN = ASSIGNED DATA SLOT NUMBER
DSP = ASSIGNED DATA SLOT SPACING PARAMETER
BSW = BIU STATUS WORD
IOS = I/O STATUS
A received status slot received at a BIU is made available to the I/O logic 58.
When a status slot is to be transmitted by a BIU, the control logic 56 generates the guard bits, the message synchron-ization code~ the twelve most significant bits of the oriyin~
tor's address, the assigned slot number, and the spacing para-meter for the transmit data 510ts and a 16-bit BIU status word.
The data portion of this slot is generated by the I/O and includes its status. The BIU status word (BSW) from the control 20 logic contains bit flags indicating frame and message synchron ization status, contention slot assignment or static (individual) slot assignment, and "waiting to retransmitl' flags.
Fig. llE shows the data slot ormat. These slot sig-nals are generally generated by BIU's and addressed to B~U's (either for a standard subscriber terminal or a network control-ler). These signals provide data messages. Table VII defines the words included for the data slot format o Fig, llE:
3~
~3~
G~ = GUARD BITS - ALL ZEROS
MS = MESSAGE SYNCHRONIZATION BITS = 00001011 MT = MESSAGE TYPE = 20 DA = DESTINATION ADDRE5S :~
OA = ORIGINATOR'S ADDRESS
When a received data slot signal is addressed to a BIUt the data portion is made ava:ilable to the associated sub-scxiber terminal by way of I/O logic 58. When a data slot sig-10 nal is to be transmitte~, the contro]. logic 56 will generate . :~
the guard bits, the message synchronization code, and the twel~e most significant bits of the originator's address. Other header fields may be generated by the control logic 56 or the I/O logic 58. The data portion of the slot is always generated by the I/O
logic 58.
The BIU checks the originator's address of everyreceived slot signal that corresponds to a slot signal transmitted by that BIU. If the originator's address in the received slot signal matches that of the BIU, then the transmission is-con-sidered successful~ If the-originator's address in tha received :
slot signal differs from that of the BIUI the retransmission pr~
cess is initiated for the slot signal. For a static slot assign-ment BIU, the retransmission process consists of determining the ne~t transmit opportunity and retransmitting the slot signal in an assigned slot. For a contention slot assignment BIU, the message is retransmitted in the next contention transmit slot for which the current pseudo-random number provided by generator 108 is less than the retransmission parameter (which corresponds to means retransmission probability in the present embodiment) s-tored in register C of microprocessor 120.
" , 1 The I/O logic 58 is shown in detailed block diagram form in ~ig. 12 for the BIU 20, together with eight clustered RS-232-C subscriber terminals (denoted T-l,...T-8 in Fig. 13).
I/O logic 58 includes central processing unit ~CPU) 140 (Yilog Type Z80), priority interrupt central unit (PICU) 142 (Intel Type 8214), receiver and transmitter direct memory access con-trollers 144 and 146 (Intel Type 8257), respectively, eight universal synchronous/asynchronous receiver-transmitters (USART I 5 ) 148A through 148H (Intel Type 8255), random access memory (R~M) 150, PROM 152, baud rate generator 154 and BIU regis~er contro 156. The PROM 152 is programmed in accordance wi-th Appendi~ II~
USART's 248-H provide the direct interface between the terminals T-l through T-8 and the l/O logic 58. The USART's are conven-tional software controlled devices which, in conjunction with the conventional baud rate generators and associated RS-232-C signal conversion logic accommodate asynchronous or synchronous terminal communications at up to 19.2 Kbps.
In the present embodiment, the I/O logic 58 is primarily interrupt driven and CPU 140 operates as a vectored interrupt ~ mechanism. PICU 142 provides arbitration simultaneous interrupt requests, and in addition, blocks interrupts below a predetermined priority level. Also, the PICU 142 encodes an accepted interrupt request into an 8-bit number which CPU 140 uses as part of its vector to the appropriate interrupt service routine.
Direct memory access channels are established by con-troller 144 and a received data bus 5RCVD DATA), and by control-ler 146 and a transmit data bus (TRANS DATA), thereby linking the logic bus of I/O logic 58 and memories 96 and 98 oE control logic 56. BIU control register 156 further interfaces control logic 56 and the remainder of I/O logic 58. Control lines from f.~
logic control 56 provide I/O logic 58 with signals representative of power reset condi.tion (PWR RESRT), achievement of message synchronization (MSG SYNC), the achievement of frame synchroni zation (FR SYNC), received timing (TIM), and a receive slot boundary pulse (RSBP) indicative of the commencement oE the received slot.
In addition, the input memory 96 is coupled to the BIU
control register 156 by the followi.ng control lines: RCV ADDR
(0-8), SLOT RCVD A, SLOT RCVD B, RCV SEL A/B, REL A, and REL B.
The received data bus (RCVD DATA) transfers a byte of data from the one of input memories A or B in memory 96 which is selected by the received select line ~RCV SEL A/B) at the location defined by the receive address lines (RCV ADDR). The slot received A
and B signal lines (SLOT RCVD A, SLOT RCVD B) provide signals representative of the condition that a received slot signal has passed the filtering provided by control logic 56 and that the a5sociated slot signal has been stored in the correspondi.ng A or B input memory. The slot received signals are provided by way of the control line from microcontroller 112. A release A or B
signal is provided (on the REL A or REL B lines) by the control register 156 when the data in the corresponding input memory section has been transferred to logic 58 and that memory section is available for storage of a subsequent slot signal.
The control register 156 is also coupled to the output memory 98 by the follo~i.ng control lines: TRANS ADDR, TR~NS SEL
A~ TRANS SEL B, SLOT RDY A, SLOT RDY B, HEADER A, HEADER B SLOT
XMTD A and SLOT ~TD B. The transmit data bus (TRANS DATA) provides a byte of transmit data to be stored in either the A
or the B output memory sections selected by a write pulse on the 3~ appropriate transmit select A or B line (TRANS SEL A or TRANS
1 SÆL B) at the location defined by the signal on the transmit address lines (TR~NS ADDR). The slot ready A or B lines (SLOT
RDY A or SLOT RDY B) provide an indication to the microprocessor 112 that the I/O logic 58 is ready to transmit a slot signal on the respective ones of channel A or B. The slot transmitted A or B lines ~SLOT XMTD A or SLOT XMTD B) provide signals initiated by the microcontroller 112 which are representative of the condition that a slot signal has been successfully trans-mitted from the respective A or B sections of memory 98 and has been received without collision in the corresponding slot from the outbound bus 12. The header A or B lines (HEADER A or HEADER B) provide signals indicating that the signals for the header fields of a slot signal have been provided to the corres-ponding A or B section of memory 98 by the I/O logic 58.
The invention may be embodied in other specific forms without departing from the spirit or essential characteris-tics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather 2~ than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are . therefore intended to be embraced therein.
3~
fP~O~.SS Ih'T~RUFi~E~t~ w~ INTE~RUiTErl A~ ;~LnT 8~lrD --~fOR SYSJEM ~ESE'r .. , . j . .... . . . . .. ... _ . . . _ _ _ .. , . . .. _ _ .. _ _ .. , . , . _ . .
~3~7 ~i~
1 The instruction execution time is 320 ~anoseconds.
This execution time is divided into eight periods of 40 nano-seconds (shown in Fig. 10) during which four functions are per-formed. The four functions are denoted A, B, C or C* and D and are shown in Table I:
TABLE I
Function A - NEXT INSTRUCTION ADDRESS READY-START FETCH
Function B - INSTRUCTION READY
Function C - SET UP DATA AT PROCESSOR INPUT (EXCEPT READ M8-MO) Function C*- SET UP DATA AT PROCESSOR INPUT (READ M8-MO ONLY) E'unction D - PROCESSOR OUTPUT READY
When an instruction from the instruction PROM 124 is ready at TB, then that instruction is decoded in the time from TB to Tc. In the time from TC or Tc* to TD, the microprocessvr array 120 executes its command; and at TD, output data and status words from microprocessor array 120 are ready. In the time from TD
to TA, the sequence controller 122 determines the address for the next instruction to be executed. The instruction PROM 124 establishes the next instruction as ready during the time TA to TB.
The microprocessor includes sixteen 16-bit registers and each of these registers is assiyned a function in accordan~e with Table II:
~3~
1~ REGISTER 8 - SLOT NUMBER B
REGISTER 9 - TRANSMI~ SLOT N~MBER A
REGISTER A - SPACING PARAMETER A
REGISTER B - SLOT NUMBER A
REGISTER C - RETRANSMISSION PARAMETER
REGISTER D - CONTROL REGISTER
REGISTER E - TRANSMIT SLOT COUNTER
REGISTER F - RECEIVE SLOT COUNTER
Registers 6 through C are used for the transmit slot determination~ In the present embodiment, registers 7, 8, A, B
2n and C are preset to initial values at powe~ OIl, and may be up-dated by messages generated by a network controller. The retrans-mit parameter in register C is indicative oE a contention slot terminal and the desired mean time for retransmission of a slot signal following determination of a collision.
Register D has control information (e.g. synchroniza-tion).
Registers E and F maintain current slot counts. The value in register E is offset ~rom that in register F by a slot offset determined by the location of the particular BIU with respect to the Data Bus Repeater 26. Register E is used to determine transmit slot opportunit:ies and register F is used in the frame synchronization process.
Registers 0 through 4 are used as workîng registers by the microcontroller software. Register 5 holds the BIU address.
In addition to the sixteen general registers, the microprocessor array 120 includes a Q-register available to the software.
In operation of control logic S~, the message synchron-ization process is required to determine where the slots start lo and which bit is currently being receiYed. In achieving message synchronization, a continuousl~ runnin~ receive bit counter in MS~NC network 104 is reset by the first receive start-of-message signal (RSOM) after power on~ Control logic 56 is adapted so that a RSOM for every receive slot should occur in a six ~pro-grammable) bit window at the start of every slot as de-termined - by the receive bit counter. If three consecutive RSOM's occur when expected, then the message synchronization condition is established. In response to two missing RSOM's in sixteen con-secutive slots, network 104 establishes a loss of message synchro-nization condition and an interrupt is provided to microcontroller 112.
Following message synchronization, the frame synchron-ization process is initiated in order to determine the number of the slot being received and ide~tify transmit opportunities. In achieving frarne synchronization, the receive slo-t number is maintained by the microcontroller 112.
If the slot number from three consecutive frame syn-chronization messages matches with the receive slot number, then frame synchronization is estahlished and transmit is enabledO
3~ If the slot number from two-out-of si~teen consecutive 1 frame synchronization messayes does not match with the receive slot number, then a loss of frame synchronization is established and transmit is disabled.
Following the establishing of message synchronization condition, the control 56 then processes the slot signals received from the bus. Following the establishment of message synchronization, the control section 56 processes the data received from its associated subscriber terminals (through the interface provided by the I/O logic 58~.
1~ The slot formats for the present embodiment will now be described in detail in conjunction with Figs. llA-F. Fig. llA
shows the frame synchronization slot format. These slot siynals are generated by the data bus repeater 26 and are utilized by control logic 56 and the control to establish and maintain frame synchronization. Table III defines the words included for the frame synchronization slot forma~ of Fig. llA:
TABLE III
G = GUA~D BITS - ALL ZEROS
MS = MESSAGE SYNCHRONIZATION BITS = 10101011 MT = MESSAGE TYPE = 1016 SN = SLOT NUMBER
Fig. llB shows the broadest retransmission parameter (RTP~ slot format. These slot signals are generated by the network controller and are utili~ed by the control loyic 56 to update the retransmission parameter stored in the microprocessor array 120. This parameter is used in the retransmission process for contention slots. Table IV defines the words included for the RTP slot format of Fig. llB:
3~
G = GUARD BITS - ALL ZEROS
MS = MESSAGE SYNCHRONIZATION BITS = 00001011 MT = MESSA OE TYPE = 1116 OA = ORIGINATOR's ADDRESS
RTP = RETRANSMISSION PARAMETER
Fig. llC shows the transmit assignment slot format.
These slot signals are generated by the primary network con-troller or by a secondary network controller. When addressed to a BIU, the control logic 56 of that BIU updates the assigned transmit ; slot number, spacing parameter, and destination address currently i stored therein. Table V defines the words included in the transmit assignment slot format of Fig. llC:
TABLE V
G = ~UARD BITS - ALL ZEROS
MS = MESSAGE SYNCHRONIZATION BITS = 00001011 MT = MESSAGE TYPE = 416 FOR INDIVIDUAL STATUS SLOT ASSIGNMENT
= 4116 FOR CONTENTION STATUS SLOT ASSIG~ENT
= 4216 FOR INDIVIDUAL DATA SLOT ASSIGNMENT
. = 4316 EOR CONTENTION DATA SLOT ASSIGNMENT :
DA - DESTINATION ADD.RESS
OA = ORIGINATORIS ADDRESS
ASN = ASSIGNED SLOT NUMBER : :
ASP = ASSIGNED SLOT SPACING PARAMETER
ADA = ASSIGNED DESTINATION ADDRESS
Fig. llD shows the status slot format. These slot signals are generally generated by BIU's and addressed to BIIl's or a network controller. The status slot signals include data representative of the status of either the BIU or an associated subscriber terminal. Table VI defines the words included for ~he status slot format of Fig. llD:
~3~
TABLE VI
G - GUARD BITS - ALL ZEROS
MS = MESSAGE SYNCHRO~IZATION BITS = 00001011 MT -- MESSAGE TYPE = 316 DA = DESTINATION ADDRESS
OA = ORIGINATOR'S ADDRESS
DSN = ASSIGNED DATA SLOT NUMBER
DSP = ASSIGNED DATA SLOT SPACING PARAMETER
BSW = BIU STATUS WORD
IOS = I/O STATUS
A received status slot received at a BIU is made available to the I/O logic 58.
When a status slot is to be transmitted by a BIU, the control logic 56 generates the guard bits, the message synchron-ization code~ the twelve most significant bits of the oriyin~
tor's address, the assigned slot number, and the spacing para-meter for the transmit data 510ts and a 16-bit BIU status word.
The data portion of this slot is generated by the I/O and includes its status. The BIU status word (BSW) from the control 20 logic contains bit flags indicating frame and message synchron ization status, contention slot assignment or static (individual) slot assignment, and "waiting to retransmitl' flags.
Fig. llE shows the data slot ormat. These slot sig-nals are generally generated by BIU's and addressed to B~U's (either for a standard subscriber terminal or a network control-ler). These signals provide data messages. Table VII defines the words included for the data slot format o Fig, llE:
3~
~3~
G~ = GUARD BITS - ALL ZEROS
MS = MESSAGE SYNCHRONIZATION BITS = 00001011 MT = MESSAGE TYPE = 20 DA = DESTINATION ADDRE5S :~
OA = ORIGINATOR'S ADDRESS
When a received data slot signal is addressed to a BIUt the data portion is made ava:ilable to the associated sub-scxiber terminal by way of I/O logic 58. When a data slot sig-10 nal is to be transmitte~, the contro]. logic 56 will generate . :~
the guard bits, the message synchronization code, and the twel~e most significant bits of the originator's address. Other header fields may be generated by the control logic 56 or the I/O logic 58. The data portion of the slot is always generated by the I/O
logic 58.
The BIU checks the originator's address of everyreceived slot signal that corresponds to a slot signal transmitted by that BIU. If the originator's address in the received slot signal matches that of the BIU, then the transmission is-con-sidered successful~ If the-originator's address in tha received :
slot signal differs from that of the BIUI the retransmission pr~
cess is initiated for the slot signal. For a static slot assign-ment BIU, the retransmission process consists of determining the ne~t transmit opportunity and retransmitting the slot signal in an assigned slot. For a contention slot assignment BIU, the message is retransmitted in the next contention transmit slot for which the current pseudo-random number provided by generator 108 is less than the retransmission parameter (which corresponds to means retransmission probability in the present embodiment) s-tored in register C of microprocessor 120.
" , 1 The I/O logic 58 is shown in detailed block diagram form in ~ig. 12 for the BIU 20, together with eight clustered RS-232-C subscriber terminals (denoted T-l,...T-8 in Fig. 13).
I/O logic 58 includes central processing unit ~CPU) 140 (Yilog Type Z80), priority interrupt central unit (PICU) 142 (Intel Type 8214), receiver and transmitter direct memory access con-trollers 144 and 146 (Intel Type 8257), respectively, eight universal synchronous/asynchronous receiver-transmitters (USART I 5 ) 148A through 148H (Intel Type 8255), random access memory (R~M) 150, PROM 152, baud rate generator 154 and BIU regis~er contro 156. The PROM 152 is programmed in accordance wi-th Appendi~ II~
USART's 248-H provide the direct interface between the terminals T-l through T-8 and the l/O logic 58. The USART's are conven-tional software controlled devices which, in conjunction with the conventional baud rate generators and associated RS-232-C signal conversion logic accommodate asynchronous or synchronous terminal communications at up to 19.2 Kbps.
In the present embodiment, the I/O logic 58 is primarily interrupt driven and CPU 140 operates as a vectored interrupt ~ mechanism. PICU 142 provides arbitration simultaneous interrupt requests, and in addition, blocks interrupts below a predetermined priority level. Also, the PICU 142 encodes an accepted interrupt request into an 8-bit number which CPU 140 uses as part of its vector to the appropriate interrupt service routine.
Direct memory access channels are established by con-troller 144 and a received data bus 5RCVD DATA), and by control-ler 146 and a transmit data bus (TRANS DATA), thereby linking the logic bus of I/O logic 58 and memories 96 and 98 oE control logic 56. BIU control register 156 further interfaces control logic 56 and the remainder of I/O logic 58. Control lines from f.~
logic control 56 provide I/O logic 58 with signals representative of power reset condi.tion (PWR RESRT), achievement of message synchronization (MSG SYNC), the achievement of frame synchroni zation (FR SYNC), received timing (TIM), and a receive slot boundary pulse (RSBP) indicative of the commencement oE the received slot.
In addition, the input memory 96 is coupled to the BIU
control register 156 by the followi.ng control lines: RCV ADDR
(0-8), SLOT RCVD A, SLOT RCVD B, RCV SEL A/B, REL A, and REL B.
The received data bus (RCVD DATA) transfers a byte of data from the one of input memories A or B in memory 96 which is selected by the received select line ~RCV SEL A/B) at the location defined by the receive address lines (RCV ADDR). The slot received A
and B signal lines (SLOT RCVD A, SLOT RCVD B) provide signals representative of the condition that a received slot signal has passed the filtering provided by control logic 56 and that the a5sociated slot signal has been stored in the correspondi.ng A or B input memory. The slot received signals are provided by way of the control line from microcontroller 112. A release A or B
signal is provided (on the REL A or REL B lines) by the control register 156 when the data in the corresponding input memory section has been transferred to logic 58 and that memory section is available for storage of a subsequent slot signal.
The control register 156 is also coupled to the output memory 98 by the follo~i.ng control lines: TRANS ADDR, TR~NS SEL
A~ TRANS SEL B, SLOT RDY A, SLOT RDY B, HEADER A, HEADER B SLOT
XMTD A and SLOT ~TD B. The transmit data bus (TRANS DATA) provides a byte of transmit data to be stored in either the A
or the B output memory sections selected by a write pulse on the 3~ appropriate transmit select A or B line (TRANS SEL A or TRANS
1 SÆL B) at the location defined by the signal on the transmit address lines (TR~NS ADDR). The slot ready A or B lines (SLOT
RDY A or SLOT RDY B) provide an indication to the microprocessor 112 that the I/O logic 58 is ready to transmit a slot signal on the respective ones of channel A or B. The slot transmitted A or B lines ~SLOT XMTD A or SLOT XMTD B) provide signals initiated by the microcontroller 112 which are representative of the condition that a slot signal has been successfully trans-mitted from the respective A or B sections of memory 98 and has been received without collision in the corresponding slot from the outbound bus 12. The header A or B lines (HEADER A or HEADER B) provide signals indicating that the signals for the header fields of a slot signal have been provided to the corres-ponding A or B section of memory 98 by the I/O logic 58.
The invention may be embodied in other specific forms without departing from the spirit or essential characteris-tics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather 2~ than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are . therefore intended to be embraced therein.
3~
fP~O~.SS Ih'T~RUFi~E~t~ w~ INTE~RUiTErl A~ ;~LnT 8~lrD --~fOR SYSJEM ~ESE'r .. , . j . .... . . . . .. ... _ . . . _ _ _ .. , . . .. _ _ .. _ _ .. , . , . _ . .
4~ iTS~V I(; REI ~RESET ~ TERRU~T ENA~LE
-- - ~ i 6f ~30~ 1 Rn ~4 RSTAT jWR4~SrATl~S ~ D
~~0~3 7~(I14i~/I2 RR~ ANU j~ ~e ~30 A4 E3Z P~RO
~ANCH IF PKOCGO IS NOT SE~
0U~4 ~F~4tA~fl Ri1 ~j ~STAT ~WR4~STATU.S ~Q
--~-U~36 7i;~4~B2 RR6~ Lf~ A~IP A~ NC ~ P4 ~Z j1SYNC~) AN~H I~ I~SYNI: IS I~Qt SF't --'-'`------'-'-`-'--' '-'-----'---'--`'--` i'~NTEi~- h~ F-- `M~-SA-Gi''E-~-NF'~S E~rA~L~si1F~
~3 0 0 7 6 ~` 8 ~ 0 V~ #
6 ~ ~ U ~ 7 ~ S ~ L ~ A ~ c 1~ [) A ~
~SEl' tlSG SYhC BIT Ot ~O~JTQ~l REG~BI r 3 OF ~E~ 1) ~xANcH Tt) ~ ESS ~LCIT ~30LIND~RY
fENTE~ ~IERE -T5~- tlS~ ~`NC IS ht~T ~STA~~ En~-~-~----``- - -------` --------3 31~i2c~ lSYi~~Ci~ IO RSYNC ;R~8E~YNC
: _ 0021 ~iFB~FFE3 I~ ?FFE~
010~2 7~ Rf~R ~B A!`iU AB NG BD A~ ~ WAITi ~R~s~r M~rh~ F~r~c AND TRANSI~)It ENABLE I~ITS llF ~nNtR~
-- ---` -------- - ` -- - --~EliIS~ER~`G~----~O`-~ -If 1 __ _ _ ~ __ . . .
_ . . _ . _ _. ._ .. _ _ . _ .. . ~. _ . ,. _ _ __, __ _ . _ _ _ _ ~. ._ _ _ ___ ___ _. __ ____ ~EI`I'rER HEf~E AT ~llE E~ID OF PRat E~35II`J5 FOR Tll~ SLIlT
:: ~ ~ -- . _ . _ _ _ _ .
00111 318~ 0 ~AI'rl IO SI ~SET I~TERRU~ NA~LE
00l1 ~UB~ 4 WA~T ~R~ ~ WdIt ~nAST HERE fOR INTER~JP~
_ .. _ . .. . .. ... .. . . . _ _ _ . _ . .. _ _ _ ..
* ~
_ _ , . _ . . .. _ . .. _ ... . _ . _ _ _ . _ . _ ... _ . _ _ _ ~PRr~ES~ PO~ER ON~EN~R F~ TIALIZA~InN O~3 SYSTE~ QF
7 ~
_ _ __ ~FI~E PARA~Eri~Q5_IN ~O _ R~GISTERS
~~~ ~ bi0~h ~ ~F~0Cj~2-E ~ -N I~ ~YI #la02E jL~TA ~;T~ PER ~L~1T
. _ . .. .. . . .. _ . _ . . .. .. .. _ _ _. . _ _ . __ ___ . _ __ _ .
j f~
~ .
-~ .
t~lt~l 2L)Al~ t~ ,r ~1~ WRt~PS J~RlrE PRl)~PS R~tiIS-rER
01~? ~F~t ~i7F I~ 17F JBITS PR SLQT
2DA~ q~ \kT 1~ h~PS /~RITE P~PS REGISTER
01~t4 6Ft~ F If3 t!lV! ~L~l~F JENo OF Tt!~ DATll 01~ i 2UAk'~ WT t3~ ~Eur~ RI7f PEQT~ REGIsTER
JINITIA~ TF~A~s~;if 4ssI~N~lF~NT VALIJE~S
6 F 8 21~' t~ 3 2 t~ ~) 0 w ti! / I G F l L 'r ~ R
tal~7 6F~3P~0L It3 ~3 ~G50C fMT FIL~R
6F~C~tY?~8 I~ #~ RAN~MISSIQN PAR~METEf;
0 1 t ~ 6 F t~ ~ t;~
01~A 6F~A~F I~ ~A ~3F ~SPA~ G PARAt'ETE~ A ~!r**~ b~
01r~ F~90U~ R ~ 05 ~SLOT NUMBER ~ ~*~ *~ *
~1~C 6F~FFFF I~ h~ ~FFFF /SPA~1NG PAR~ME:T~R F~ ~r*~ *
Q l i~ l3 6 F ~ h B ~ l h ~ B 2 E~ `' S Y N C ~ ~ R M S G T r P A
t 21~A~ t~ ~T ~ HBU~ A #~ /~RiTE t~3FP (~
1 F -6 F ~ Y) I3 ~ B 3 0- ~ ~ ~ y N l:: 0Q Qs ,M ~G T y e ~.~ 3 Q_ . ___ ,_ _ _ __ _ ___ L) A ~ A ~ U F ~ R I T ~ t H El F ~ t P! ~
~F~III ACIL`JRESS SHOIJLD HE DI~F~ltE~IT F~)R ~A~ l3ILI
0111 6F~51~ 5 ~ R5 ~ t~IU ADDQ~:S!; ~*~ *~
01i2 ?l:l~ei0RCB I~T ~5 ~ UFA J~ WRI'r~ THBFd~2 Clil3 52UA5R~ r E~5 hHE~llF~ ~2 ~ RITE T~F~2~
4 _ 21~ h C ~ W 'l ~ 5 h H B U f A_ ~ A ~ _E! I U~ A t) q i~ _ _ _ __ _ ___~ _ _ _ _ _ 011~5 6F~Ip~ h #1~ A~ l)R ~F NETI~RK cr~
~311~ 2 1~ A h ~ 4 ~I T B ~ W ~ P lJ F B ~ 1 . . _ - ------ - - - - - -Zi117 6F~ h~0 ~ LEAR ~E~;T OF TlYf HE4uER ~UFFER
8 ~ AURR~WT I~U WhBUEA ~4 ~ ~ ~ Y ~ U A ~ T h ~ W h ~ 4 0 1 1 A 2U A~ t?~ H~ IF A ~5 __ _ _ _ _ __ 21jAr,~ W~ l~U hH~UF~ ~5 01lL 2UA~CC ~T U~ U~ ~3 011U 2~A~ C W~ 6G1 ~W~lJF~ ~
01 1 E ~ T M A ~ R ~ ~ T ~ T h E Pi A
01 1 F ;~ ; i;1 14 U I O ~ T ~ B ~ T M T ~q E H f3 01?~ lq0~s2~ __ IO R11A ~I~ST A ~TD _ _ _ __ __ ____ ___ t~l21 3~ 2al~ ir~ Rl1~3 ~RST 8 TMTD
~d l 2 ~ o g l~J t~ ti p ~ S E T G o ~ I N ~ I v I D u~A L A B I ~ S
Q1~23 31~!e)1C~ In sP~
012 4 2 l) ~ 0 ~ ~ A 41 ~ A I T
~ ___ .. _ .. .. ., , _ .. _ _ . __ _ ._ _ _ _ _. _ . _ _~ _ _ ~ ~ _ t~ ~ 4 ~i iPIi~CESs SLO~ ~OUNDAI?YYIENTER A~ TtlE REC.I'iN!I~lG OF EVER~i __ _ /UPDATE R~C 5LOT COIINl'ER ANI~ ~MT S~OT Cn!lNTE?~nETER
~3PPnRTUNIT~
_.~
014$ 6P8~0~,10 S~T~ 0 __01~b ?~B~6~A R~R "H ~ND A~ hC ~ AD ~Z RECSLJ~
~B~ANCH IF FIRST FSYNC sLnT NQ~ RECEIVE!) ~147 61C~7C~ RRS LH A0~ Z~ C BF A~ ~INC REC SLT ~R _ ___ _ 01~ 6FH0~FFF ~ FFF ~Q~ ~Ln~S PE~ ME
014~_ ~4C~FFCJ __ RRS L~ ~UBSR ~ C B51 AF SP ~Na ~KIP _ AT F~A~E ~ND
014A 6FaF~ 3F #~0 i~sr R~C ~LT C~R
014~ 6F~004 IB ~e, ?~B~J04_ _ _ _ _ _ _ _ ___ _ _ 0 1 ~ 70~D66A RR~R L~ B NC B~ AD ~Z REC~T
J~hNC~ IF ~#~N8~IT I~ ND~ ~N~BLE~
014D 61CÉ0;C0 ~S LB ADD ZB C BE A~ ;INC T~~T ~T, TR
,~ 1 4 E _ 6 F 8 ,'~ ~1 F f F_ _ I E3 ~ F f F S ~3 ,'~ 1 S ,l O T S ,~ F R F- R A I~ E
0ii,~ ~C~E~C3 s?5~; ,3L~ S!,JBS,~ A9 C ~b AE ~P ~NO SYIP A~ F~A~'~ ,~
015,~ 6F8ot0,~ 3 8E J~00,a0 ,~RSt "rMT SE~ CTR
7ERMI~,~ TR,ANS'`lIT oPPORTU~;IT'l~ F~IR ASSI",,~ ENT A,t~ USI,~!
.. .. _ .. . , . .. _ . . . _ ... .. .... . . . . . . .. _ .. . . . . . .. . .. .. . . _ ... _ . .
r--~.
, ~ ~
~L~,lS~
.
Sl,QT C(~U~
~UIl l~!OT C~IECK ~OR A 7~1T OPP U~li E~S ThAa~
0151 6f`9~iGl4~ ~U t~d ~SIAT i~ sTAfUs ~O~D
__ ~ 1 5~ 6 ~- l3 0 ~h h ~ kt 0 i ~ ~ 7 ~ F ~ ~ R ~ S 1., ~ A hi L~ Ç ~ ~ A ~ S ~
~154 2L~BI~!0$8C Bl~ fl t:KBT~I ~rP~A ~ 3 ~ CHECK FOR ~ OPP
t~ E~C~ ~KAT\~lT ~RS ~H ~lR ZA ~ A~ TM~ ~T CT~
1~1$~ 7~A71:~ RRS ~13 Ahl~ A~ ~C U~ AA ~TSC AhlD SPACIhl~ PhRAi`~ R A
&3 1 5 7 6 4 C I~ G 2 R I~ S l, t~ S IJ 13 5 R ~ Pl C R Ql ~4 ~ S K I P I F ~ R I~ ,, P r ~ J ~ A
~ ?~ $~,C,_,~ C~,B,T~1g,~,NU A T,MT OPPO~,TyNI~Y,,_ ___ ,_ __ _ _ ~lg~ 6F8~ ilt,1 I~ 4~ /CHECK IF 7~1IS ~i RETMT
ia15A 7~1j5~9~i RF?~R LO ANU AE~ C t30 AO t~Z AT~T
~hIS I~ RETMt 0 i ~ 6 F 8 ~ i C H E C K F n R !: O N T i\1 T I Q N
_01~ 70~iOF5~ ~5 L~ Al`ll: AB_NIC ~0_AP SZ
1~ 1 5 U 2 D ti ~ A ~ I~ R ~ T ~1 i /~HIS I5 CONTE~TI~
6F~v~FfF I~ lilFFF ~Rt~AD l.S i~ BIYS QF P RA~
lalsl~ 7æsk^0~qGJ RRR~S LE~ ~NI) CIA hlC 13~ A0 Rt~AI~IU
0~ 6~F~C~ RR~ EI ~U~SR AB C ~ ~C F~P I~ECSLT
~161 ;~181!Gl~QI Ar~r In ~ 7TMT lli~M A PUL~E
iSAV~ J? OF sioi Ti~~r ;I~ID ~0 PRDCESS REC sLn~
~162 ~ h~l~ R~R l.f3 ~)R ~A l~lC B6 ~E ~5 ~ECSl,~
~n NnT ~ECK ~OR B 7!lT OPP Uh~ES~
T ~
1 6 3 ~ F ~ T M T ~ A # ~ 4 ~ M
~1~4 7~14FC2 i~2S Lt3 Ahl~ A~ NC ~ A4 ~Z
~1~$ 2O~6t;~` ` 8R `-f3~ R~CSL~ M~ ,~~ GB PRPC ~~~~~~~~-----~-----~~~----~-- -C ~U SLOT
~16~ ~E~1~E7CU R~S I~B 01~ Z~ B~ ~E /~lR~T~T ~sLT ~TR
01~7 7U~7t~vl R~S ~ At~l~ A~ hlC B~ A8 /TSC AhP SPACI~IG PA~AnETER
~lfi~ 641~CZ R~5 ~H Sl~SR AB C B~ 52 ~SKI~ IF WRU!-I~Ln~ NUMBE~ 1 ~165~ ~U~fifi~ BR B~ 1~ R~CSLT ~Jt~ ~ TM~ tlPPDR~JNIIr NrE~ ~Ff?~ FOF~ ~3 Tr~7 oFPnRiU~ITr ~116A blf`~ t~ IE3 t3GI $~2~Y~ ~C~lECK IF ~HIS IS RET~T
7 u h h L1~ L~ A f~ R L~ R L~ ld A i~ ~ A B ~ D ~ i 13 T M
~THIS I~ ~E7~1T
------ ~ ~F~a~s~ p ~ GHE;I~ IF T~IS IS CoNrNTID~ ~,,nt U~61~ 7~B~DF~2 __ ~RS LLj AND AB N~ AD _ SZ
~1 6 E 2 V~ Ei l3 5 C ~ ~ R ~ T M T
~THIs I~ C~NTENTION
016~ 15FB~FFF I~ ~~ #~FFF ~REI;D ~S 12 flITS DF P RA
la17~ 72gL?~t'~ S ~ AN~ DA N~ ~0 A~ RR~.N~
0 1 7 ~ Q ~ S lJ ~ S ~ A l~ C ~ C P j R E ~ S L ~
~172 21)AB~1~C 8~M~ WT ~ FB ff~ ~WRITE ~LT ~ A ~ 0 TA~r I~OR B
0i73 2i~AAS~ i^iT ~A ~jt31JF~ ~4 ~I~RITE SP FA~ â ~N T(~ TMT tl~
~17q 2V~VO11 14 W~ ~V ~11H~FB ~:$ ~WRIT~ CNTRL REG TO ~MT ~DR 8 0175 ;~iB~ Cl:~ IO TMh ~TMT hE~1 ~ PULSE
/S~V~ F SLGT T~IT AND GQ PRDCESS I~EG_S~,Dr 0ï76 6~;E~6~ R~l3R Ll3 OR ZA ~JI: ~7 ~É ~ RECSl~T
~ _ ___ __ ___ __ _____ __ __ __ _ ~19A
_ . . . . . . . _ _ . . . . . . . _ _ _ _ _ ..
~PROCESS R~CFIVE 8l.OT~CHECK IF _REC ENA~I.E I~_SET~W~T IJ
EC t~ HAS LEEI`I REtEI~/E~ tREC ~DR aF~ ~iAs ~EEI`~ RE~ET3 ~IF THIS IS ~iLOT TMrD ~Y RE~ VING ~_ C~ECI~ Tu~T
/TI~ AS ~liCCE~SFUL
~RAN~H T~ ~OUTINE 70 ~ROCESS REcD ~LnT ~)~PE~DI~IG O~l M~
. .
.....
~ ~L
,,, / .
~ . "
L~19A ~ 0~ tECS~ SI ~SET IN~ERRI,IPT ENa~LE:
~1~TER~UPT IS ENA~ D TO PREVE~ r)EFI~T~E l,~OP~G r~ljE
/tU S~ME Mh~F~I~C~
6F~rA~8~1 RE~EN QU ~4 RSI AT ~R~STATl~ WORL~
~ 1 9 ~ ~ F ~ C~ ~ r.1~
f/119~J j~h~!46fi~ RR~R Lli ANU AE~ NC l~ A4 BZ ~ECE~l ~3RANi.l~ R~C E~ABLE IS N(~T SET
h~4~r~ Rj1U~f~ R~ ~4 ~ST~T ~h~4~ STATUS WORP
01 ~F ~F ~ 0 I ~
~1A~ 7'~8f1~fC2 RR5 ~8 A~O ~B NC ~ 4 ~Z
~2 _b f R _11 ~ 5 R E E N R E C E I V E n f~11A1 2~ fi7~ E~R ~L~ ~ RHI)~FK ~YAI'r FO~ R~C H~ FF
~1A2 3~ A~ IO R~I ~RE~T IhTER~lJP7_ENA@~E _ _ _ _ _ ~CHf CK IP IHIS SLOt I~IAS ~n ~Y THIS ~IU
_ ~ 1 A ~ 6 l- 9 4 l'~ 4 ~ S T A T _ , . . . . . . . .
~1A4 ~4C6Ff C~ f~RS LN S1~SR A~ C B6 AF SZ
01 A b 6 F ~ ,L~ , ff ~ B fJI ;j1 ~1A7 7~t~6~ SR l~ ~ND AB N5 I~L~ A4 B~ C~S~REC , ,, ~IHIS IS AN ~Sl,OT TMTt) ~Y THIS 6lU
_ 01A8 ~I~L~h2~L-~I IO ~ffA ~FtES~T ~ Th~O
~:H~f.~K Tt~AT OA IN RI~Ç HDR E~1JF ~ ADI~R nF hIll _01ASI ti~ FFFQ I1~ F~E~ ~MS 12_i3I~'~_Q~LX.________.__. ------------------------01AA ~2~V;~ C WQWl15 l,.i~ A!~l~ I)A ~IC ~3~ A~! RH~3UF '~;~
f~1AI~ fi~1F~5h~3A RRE3R Ll~ SUI~SR f453 C f3~ A!5 a~ ~3 - - joA Ij~S NOT ~lATCH ~ IND RETMT REGti!~
UIAL. fi~E~Li4~QI,t It3 ijL;' Jt4fA~fA ~SEI ~IT 14 IN 1~ REB
IOlAlJ ~jL'~L)U~iFl.~ RRt~R LH l.lR ~13 NC ~l) AVI El PRnSL,T
~f~ Tl;HE~ ~ NO'r RET~lT f~EO ~ ~
i f~ ~ 31~ M A ~ R I: L E i S F T il T M E M A - -- - - - -- - - --- - - - -1a 1 A~ 61; ~ F~ ? bflFFF ~ AR B I T 1 d I N C'r~L REG , _ _ 7~BU~6F~ Re~R L~ Af~ A~ NC B~ A~ ~ P~t1SLT
fl~ 4C7~fC~ CK~jtEC RRS Ei~l 5U~SR AE~ C F~7 AF SZ
t3 1 l3 2_ 2 U B ~ F ~ P ~ t~
01H3 bF8U04t~ B ~t,~ ~4~
~l~4 7~ 46EA f~ L~ ) AB NC B~ A~, B~ PROSI~T _, . ..
~THIS I~ A B~SLOT TMTO B~ THIS ~IU
~1B~ 3l~V~t~124~ lO RMB ;RESE7 ~ TMTO . . ... -----.
~CH~Ct~ ~H~T 0~ E~ HDk ~UF ~ AODR QF
~1~6 _ 6F8~;f~f~ IB ~ ~F~f5 ~1~7 72~ C f~RRDS L~ ~ND DA NC ~~Z A9~ RH~UF ~~
_ 01B~ 64P~5~EE RR~R LB SlJ~SR A~ C ~ AS, ~Z O~3,, ,,, ,,,, , ,,,,__,, ,_ , ~OA r)~S ND~ A~CH ~ ~ND ~ET~T REQ~D
01139 ~t~8~12~1t~ IB ~t~ ~2~'~0 /SEt BIT ~ N ~TL RE~ _ 01t~A 6C~lJ06F~ F~F~ OR API NC I~D ~ ~ PR0sLrT
_____ __ _ _ _ ~OA MAtCHES _NQ RETI~ll _RE~ I V _ ~_ 180~140 IQ RTMli ~RELEASE TMT ME~I ~
0aHl; 6~DFFF IB 1~ tr)f;FF /CI,E~R Bl`r ~ IN CTl, REG _ _ ______ _ 01~v 7id~[)P76F~ RR~R L~ AhD Al~ t`lG ~P A~ B PR~SLT
01t3E ~U~IB~ PRtlSLT ~R ~ ~IO
- 7BR~I`IC~1 ~0 SERVICE ROUTINE nEPEi'lPING ~IN RE~EIVE~
~MEss~GE TYf'Eq~ ~RANCH ~O I ~O V~TOR
____ . _ _.__ _ _ _ _ _ . _, .. _ . .. . . _ _ _ _ _ . _ _ _ _ _ . __ _ _ _ .
~b*IMPORTAhlT~ ~LI. RECEIVE ~IL~S~G 5E~V~E ROUT~NES
751~0ULD STA~T WITIIIN 0P0 Al`l~ 0FF ___ _ _ _ _ __ _ _ ~TART~ O~TION MESS~GE TYPE MEssAGE TYPE~ COI~:
.. ... _ _ . _ . . . . .. . j _ . _ . . _ . . _ _ . _ . . _ _ . _ _ . _ _ _ _ _ _ _ _ _ _ _ _ _ 7 03~1 FSYI~c ~QI
... . .. .... .. . . . . . . . . . . . .. .. .. . _ .. _ .
J
t~
`...
T d 2 o ~ a I G :! I
__ ............... . . .. . _ ..... . . .. .. .. ..
~ ~A~ DATA ~SSIGN~9EN~ 4?/4~
QCH SI~TIJS ASSIG~ Nl 4 ~ q~a f Il.TER A~5Içr~MENl 4~
j ~F8 uh~u~FINEL) ALL R~ ING
/ IdFF ~ L~ 0~
. . . . .. . .
_ . _. . , _ ____. _ ._ __ _ . _ . _ __ . _ ~_ _.. _.. _ _ ... .. _ _ _ _ __ _ _ __ ____ .
tP~DCE~ fsrNc-~ Tl^IIS F~IUrIN~ ESTA13LISI-IES At`~r~ MdTN~A~NS
~FRil`~lE SYNCI~nNI~ATaON~ IT i1Ar~HES ~HE fiE~ SLT C~ ~ITI
~lllE SLOT NUI~lBER Il`~ THE FSYNC MS~ IF THI~ !~I OT ~ ~ 3 OhSF~CUTI~E ~S\~ S!_~TS MA~hEs THEN F5YNC IS E~iTA~i.Is ~IF T~IE SLOT ~ IN 2 OF l~ ~nNSFCUTIVE F~YNI~ SLr)~ t~nF!3 AtCH THl~iN FSil"C AND ~F~ANsl`lIT E~ RLE~ ARE RE~3E~
~3Q 6i~8~ ?1 F~YNC IB t~ 002i iC~lEl::K Ml' FII T~R ` --Q0;$1 7i~1BE~31iC2 f~RS L~ ~hi) a~ NC ~ ~3 5~
01~J32 31BQ~ IQ L)A~1 ~PdSS TQ IL1 I~ REQ~D
01!133 ejF~Q~10 Rl) t3!~ RH~UF ~t4 ~i~R~: RECI~_SLOT ~
i~U3S i~0~41:~112 ~ B t~`!l A13 I~,C ~ AD BZ FFSY~C
i~Ri~CH IF T~E RECD SLOr IS THE FIR~T FSY~G Sin~
64C~FC2 RRS L~ 5Ut~SR ~4H C i~ AF $Z
75KIP IF f~LGI~ SLnt # IS EQlJ41. TO f~ LT ~TR.~ I~tATcr Q037 2U~e~112;~ 1~# t~0 ~ I~S~ Q
13~;S9 7~B~Dla~ RRBR L13 A~C) A~ NC 1~ AD ~Z FF8Y~IC
~13Y~ TR~NS~lIr ENA~I.E IS NPT ~T
0~1;5A ;)ll~Q2~0 _ IO SYNt: ~SE~r Fsyr,~C ~L~G
Q10 3 ~ 6 F 8 L~ 21~ 2 ~1 Q~3C _ 7~ D~ RR~ LEI ANL) AB NC a~ Ab ~Z l!AIT1 iB~NcH IF Nb MAfi~ CONbITlOh hAS NO7 ()CC11~ E~i ~1031~ _ 61Cl~c0- -RRS l,.t~ A[~l~ ZB C B1 A~
1il~3F ts4cQlFc2 RRS ~ UHSR Al~ C f3C1 A1 ~
tSt(lP AT E~l) OF 16 CONsECiJ~IVE FE;iN~ SLnTS
0~40 21;)~i0~Q4P~ iAIT I
0 ~ 41 ~F 810~ 1 #~)~ R E SE T w R
0~2 6F8~FFDF _ IB ~0 ~F~PF
8~3 7~D0040 RRHR L8 ANU ~ NC bD A~ B ~l~aITi 0044 ~E~F~7~ FFSYNC R~5 E~ OR ~A NC_~F ~_/ENT~R F~ FtQsr F$r~c SLOT
0 0 4 b 6 F ~ 0 ~46 6FB~00ls ~ O ~ 1u 0~47 fi~BL~ RR~R L~ OR AH NC 13~ A~ ~ WAI~I
0~4B ~F8~20 RSNrJE~ 02~ ~ ~N~ER_IF NO MA~CH
0~49 70~bl 3A RR~R LB A~D AB ~c ~7 AD B2 FF~LOS
/~RANCH IF _ IT T~E FIRST NO M~C~
00~iA 6F~10~0 I~ Bl ~s~0 iRE~E~ WR1o E~ rER FOR L~i85 Df isY~c ~ ~~~~~~~~
~4~ 3l~2C0 IG ~8Y~C _ ~RESE~ FSY~C ~I.AG
b6~4c BF~FFC8 I~ -FFC~3 004U 70~U00~0 ~ ND_~B ~C ~D ~0 B WAIT
s~T FsiNc~ FI~S~ ~SYNC LDS~ TRANsMlT ~ LE ~IT~
~04E 6F~la00l _ Ff~LOS lH Bl ~000l OFIRST O~ _ 16 CO~SECUT~VE_ Sl.OTS
0~4F ~F~0~02~ IH ~ ~0020 0050 6C~DP~0 RR8R ~B_~R A~ NC 130 A0 B wA~T
oS~T FIRST ~SYNC l.OSS ~IT
~U51 ~lC107C0_~FSYNC_RR5 L~ ~DD _~8 C_~1 A~-/EN-~ER_ lrO E~l'Aa~I~H FSYNfC _ _ 0052 6F~0~0~3 IB R~ 03 ... . _ _ _ _ _ _ . _ , , ~ .
~i ~7 ~ ld ~. ~
S4~P!lFC2 ~h~ l t) ~UBSR A~3 C B0 A1 8 ~SISIP IF 3 ~OI~JSECUITVE MAT~i'`HI~G SLnT ~1UMBE~i?S RI~CEIV~
la ~ S 4 ~ l~ b ~ C ~ 4 r" ~ h A I I 1 010~5 3~ `h2~l~ 1D ~;Y~ SLT Fsr~C fL~
id056 Fl~l`0G.e;4 ~ 0 ~004 ~ VI 5 7 ~ 7 ~, ~ Ft f~ S . I ~ O R. A ~ I.C~ A 0J
01~ 6f~ . F I t~ #~ lF
1~5~ 729t~ 0 R~RI~S Li3 ANi~ i~A NC EIE ~ RSLOT ~Ri~ AC) Si 0-~ r~FFSE~T _ _ )aL~5A 6Fl~4tQl~ ~Z Ii3 1~4 ~ U,~2 01~5~ i;l q7 C~ S l i~ Ai~i? t B ~ E A 4 ~ I Ni" i3 Y 5! _ _ _ _ __ 005i; i50~i-F~A4~ Q~R Lt~ Al)l~ Ai~ i3E AF B l!i~ITl T ~1 1 S ~ t Ç T F~ G _ R E C S ~ ~_ C T 5~ ~ ~ L O T . O F F S i T _ _ _ _ ___ U ~
~P~[~t;~iS~ RTP~ ~EAO I~l AND STORE T~ E R~TR~S~ SS1nN
'PA~9~i Ti;R_ :1~ WRC___ _______ __ _ _ ___ ___ 6 ~ h ,A ~ R T P I B ~ 5 L~ I~ ~I l . . . . . .
0~l 7~ 3Fi.,2 ~i?S j~H ANU AB ~ 1 a3 SZ
2 ~ n 4 A~
~;3 ~F5~C~,t~ Ri) ~C i~HBUF ~$4 /~RCY RTP
0 i 6 4 2 I? B i ~ rA l;S 4 Ijl i3 R 1~ 3 b A I T 1 _ _ _ ____ _ _ _ _ - - - -- - - ------- --------- --- -~ Y ;f) 7 ~
.. .. .
~n~l'A M~ssAGE
~IF MT FIi TÇh SPi~CIFItS PASS ALL i~Oi'l~NiJl,~L_~l$G~ tlF?._ 7THi~ ST SI~NIFIi~ANT ~2 BITS OF
~Tt1E i~ST2~A`rli~N Ai~DRESS Of RECIVE~ SLnT ~ lE.5 ~i'`tJRi~i SPUNDI~G ~I)l)Ri..5S OF T~iE RIU T~lEN A ~E~T Ann~ MAT~
~P~JLSE IS GE~IERATED SO Ikl)IÇAt- REt~ SL~T R~DY ~O TilE
JI~o-SECTII~
. . . . .. . .. . . .. . . .. _ ... . . , , , , _ , , _ , , _ _, , _ _ , , _, , _, 0 i~l 7 1~ 6 f 8 Ç~ O A T ~ # P ~ C ~ E t ~ ~ T f ~ L T R
7 ~ . 7 ~ ~ 0 3 1 f) ~ t L FI I A N P ~ B I~I C B 71 A 3 P ~ O s f~ A M
l~07~ ~iF~7FlFFI,l IB E~ ~f FF~I
0U73 729l5l~0~ RRRDS 1,~ ANI~ C~A NC E3~ a~ RHi~U~
~WR0 ~ OEST Af~UR AND ~FF0 0~!174 _6~C05FCZ R~S 1 1~ SlJ~S~ ~B_C I~PS A5_Ei2 iS~IP IF DES~ AD~R llATCl~ S
0075 2UBk~Q~4it 13~ t~0 E~ AXT1 0~76 ~lf30~ PSl~A~ f)AM /DEsr ~C)bR M~7;~ PULSE
0077 2DB~lU04~1 B~ BU f3 WAIT1 _ _ .. . _ ______ __ . _ _ _ _ . . _ ~ _ . . . _ ~ . _ . ~ _ . . . _ . . _ ~#~flt7 ..... . . . .. . . . . . . ......... . _ . .... . _ . . . _ _ _ . _ _ . _ _ .
~INFO~ TION GRDUP MESSAGE
7IF ~T FIL'rf R SPECIFIgS PASS ALL No-N-~NuL-L M9G~S _ _ _ __ ~OR IG FTl.TER SPEC~FI~S PASS Tl`II~ ~G, C)E~T
_____________ _~ADV~ tl~T~H_PU~SE_IN GE~IERA~
/
0080 ~FR0~t04 ~ IG~P 1~ 001 ------ i i4~03F C2 I?RS L13 l iNb AE~ ~iC e 0 A3 S7.
0U~2 7;2902~ RR~i~S ~ AN~ A ~`JC E~l A2 R~IB0F ~2_~Z
0~3 3180~ t~ I~ bAM ~PASX T(J IG
__ 011~ 4 _ 2 ~ I 4 ~ _ 9 ~ H PJ ~ I I l_ _~ __ __ _ __ _ .. . . _ . . . . . . . . . ... _ . .
. . . _ _ . . _ . .
3 .~
~ # ~
. ............ ) jSTATU~ $SAr~
~IF ~T FILTE~ SPECI~IEs2 A3 PAS5 AL~ O~l\IUl L MSGS
~ ~3 PASS ~ S'rA~uS ~sr.s i C~ PASS t)lRECTEI;) STATUS ~1SG~
AN~ ES'r ~OOR h~TC~lES
5G IS PASSED ~0 USER ~)EvlcE
6F~11"1~0~ STA~uS I~ #~Qll ~ALL Sl,DTS OR A! ~ STATLJ9 01DS~1 7~ !3f CZ ~R5 L.~3 Ahil) A~ I~IC ~ A3 0~0264 ~R H~ StUAM
~ ~ g ~ h ~ 13 U ~ 9 J b ~ f~
~i~9~ 7~ Lh4Z RF1iR L~ Al`lli ~ Nt~ A~ ~Z ~AIT~
S 5F~JFFf~ IB ~ #f~F0 ~ ~~ ~~~ ~~~~~
7 2 5~ r,l ~ R I~ S L 8 A N ~ l) A N C ~ ~ ~I Q R I~ F~ U F ~ 2 LqH~7 fi41:;h!1iFC2 RRS L~ ~iUaSF~ A~ C 1~ A5 SX 7 ~4~1gA 2U~3~Q~4t3 i~k i~ WAIT~
3 ~ i L~ S T V ~ M f o ~ a M i P ~ S S ~ ~ J--~--~----~~~~ ~ ~ ~~~--~--~~ --0UgA 21~B,.i~ Bt~ ) B WAIrl .. ... .. . . . . . _ , , -- - ----- .- .. .. . ..
.. ... _ . _ . .. .. ..
/~4T4 S~Ot ASSIGNME?`IT MES~GE
jIF hSSI~NM~Nf IS A~ ESS~D ln THIS
~1U THEN ~ APPf?OPI~IE S~nT NUM~EQ~ SP4CI~IG P~RA~E~R
~AN~ IN~1VIUU~L/ CON~EhTION ~IT ~RE l;P~4rE~
- - - - - - - - - - - - - - -g3~A~ lFFF~ I~TASMT I~ #FFFPI
` ----5~-~A~ 72Q~ `L~1 Rf~PS l~B Ai`i~ ~A l'JC Ps~ A0 ~H~llF #~ -- -0~AA ~4C05F C'~ RRS LR SU~3S~ ~8 C El~ A5 SZ
~CM~L~ f~R DA MArC~l 0~A~_ ZD~ f4 ~R ts~ DTAS3Ql ~NU MATCH
~ O A h A T C i I A S S I G N M E I~ T ~ ~ R ~ H I S B I
0~bC hF~0L?FF I~ 0L FF ~ET ~iG ~YPE _ __,,, ,, ,, _,, _ ~
AD 72~ M~ R~0S L~ Aj~D DA NC B~, A0 RHRUF ~i ~~ ~ ~~~~~~ ~
~0Ae; 6F~4~42 I~ 4 ------0~AF- 6~f 4~J2L~2 R~ LH SU~SW AB C B4 A~ BZ D~ASI~
~CQ~IT~NTION ~ATA SLO7 A~S~NT
Oe~ 6F8~.EFFF I~ Bh ~EFFF J~ESEI INDIVIDUAL A BIT
0~l70~D0~C~ RRS L~ ANO ~ NC ~D A~ , ,_, _ _ _, ~___, _ _ ____ :
~B2 6F8~04~0 I~ 040~ ~SE7 ~IE~; ~5~t~iT I~IT
~0B3 6CaD02U~ RR~R L~ t~R A~ NC ~D A~ B OT~S20 /INl)IV14UAL DA~A Sl.nT A85MN~ ~
0~B4 ~F~0l~ OTAS1U_ IE3 ~ ~tl4~ SE~ lND A ~Ir AN~ NEW A ~S~S~
~l~ 6CbL~71:~ RRS LB ~R AB N~ ~D A0 f91~0~1~ UTA~0 R0 B~ RhBUF t~4 ~8LoT _ b A
0~i6F9b0~14 Rli ~A ~t~tiUF ~5 7S~CI~G PARAI~ A
0~86F9~0B18 Rl) a~ RH~uF ~6 ,~E~T 4DDR A
d~s~L~A~0~,C4 ~ 80 WHRUFA ~ t ~()E~ H~'TllER TO _ PASS ~lSG tDA M~YC!lES) 00HA6F~000~3 I~ 0~0~ ~LL SLOTS OR DAtA ~âlqNTS
7~0~0a2 ~R~R-L8 ANV A~ NC_~0_ ~3 ~2 ~ITI
00~C7VB0Ç~2FC B~i B0 B I~TAS40 ~ET wtlE~h~R TO PA5S ~SG ~r~4 ~OES NOT MATC
008D 6F~ 01 n7AS3~ IB ~0 #00~ A~S Al.L SL~TS ~NLi 0~B~ __ 7~3~4Z RR~R L~ _ ANt~ _ A13 _ ~C B0 A3 ~ iAIT1 b~HF 3l~0~i80 DTiS4~ IU L~AM ~PiSS MS~
~ 0 ~ 0 2 ~ 4 ~ 8 h A I 'r 1 .. _ _ _ _ _ . _ _ . _ . . . . . . . . . _ _ . _ _ _ . _ _ _ . _ . _ _ . . . . . . . . . . . .. . . ... . . _ ~ . . . . . _ _ _ . _ _ _ .
_ _ _ , , , , , , . . . -- -- -- --.... _ . .
~SrArUS Sl.~)T ASSIGNMI~`iT MESSAGE
_ _ /UPDA~A ST~TUSi ASSI~;N~!EN'r I~ I~A IN_$G I~ATGHFS__ _ ___ _ .
~IU Ar~DRtss ~PASS MSG to USER DEVICE IF M7 FILTE~ SPECIFIES
PASS ALL MSt~S OR PASS ~IREC~P ~TAIUS ~LQT
SSIG~ T MESSA~S A~l!) t)A MATCllES
la~C~ 6F4~'FFI~ ~TASI~lT I~ FFFX
0 L~ C g i 2 ~ B Fl ~ R D S L t~ A N r) l) A IY C ~ l? H ~ t 2 ~CHI~CI~ FtlR OA MATC~
0ilt:A~4C~5FC~ RRS L~ SUASR AR C ~0 A5 SZ
klUC~137 ~ S r AS;~
/I~A PIATCH~S ~ UPUATE ,~SS~1NT
C C _~ F ~ Pl F F_ _ I tl ~31A_# ~ ~ F F /.~ E T, ~ S G T, Y P F, _ , _, _ _ ,_ _ ,, _ _ _ _ _ _ _ ~ ,, ~ CU7~ Ifl~4 RI~K~S Lt~ A~iD IJA r~ a R~l~uF ~1 0 U C E 6 F ~ a ~s ~ a ~ T
0~CF64F4u3$2 ~R~ C~ SUB~R A~ ~ ~d A~ ~2 StASl'~
~COI~lTENrInN ~T~TlJS Sl OT ASSIGNM~hT
01al~F~F7~F I~ B~ F7Ff ~RES~-I INQ B ~3IT
~4 0-D l- _ 7 0 a l~ 0 7 ~ S L ~ A ~ ~_ A ~ N 1;~ L0____ _ _ _ _ . _ _ __ _ _ . .. _ ~_ i F B ~ z ~ $ 0 2 ~ 0 / S E T ~ E I'I P A S S ls h; l~ B I T
D3_6Ct~ 35~ RRI~R LB t~R Af3 NC e~u A57 P~ ST~s2~
IpuAL 5-ATUS ~LOT ~SS~G~lEl`!t b~uP4~F~ AH0~iTASl~ IP I~U st~A~?!0 ~S~ ~ip ~ ASS!1NT AN IE~ 13 ASS14l~T I~I . .
0~56~Du7~RR~ ~f~ QK A~ ~C ~ A~
6 F Y.~ S T A S ~ B ~ R h ~ u F ~ a __ _ _ ~7~F9~Q~ P ~ b~F ~5 B F 9 ~R ~ H ~ U F ~ fi 0~1)92UA~1fl4 h~ llF~ ~1 ~DEl-~RMI~ HEIHER tO PA~S M5rli . _ _ _ _ . _ . _ . ... ~ . . .. , _ . . . . .. _ . _ . . .. . . _ . _ _ _ _ . _ _ .. _ _ _ _ . _ _ _ . _ fOA ~A~C~ES~
_~Pa ~F~ 0~$ ~ALL SLO~iS pR ~)ATA ~SSMNT S~IlTS
0~L~ 7~ Z f~Rt~R ~ A~l~ A~ N~ H~ A3 BZ ~AIT1 __00UC_ ?D~L~037C t3R ~ sT~saQ! ,,, , , ,, . . ... , ._ .. .......
~PA 1)1~ NUT MATCHi, _ _ _ . _ . _ _ _ _ _ .. ... _ . __ ~ . .. _ . _ _ _ _ _ _ _ ___ . ._ _ _ ___ _ _ _.. . _ .. _ . __ __ _ __ _ __00DD 6F~00~1~1 S7~S;~I~ I13 ~ ~t0~01 JALI. ~l QTS Ol`Jl!!Y _ _ ~5! D~ 03~a2 R~t~R Ll~ l) A13 ~`IC ~al A3 ~Z ~ r1 ... . . - . .. .. - . - . .
F 31~ STAS~0 IU UA~ /PA8S ~SG
0 E 0_? QB 0 Ç~ Q _~ R_~ Q_ ~ W A ,I T I _~ _ ____ ___ __ /
~ILTER ~SSIGN~NT MES~A~
~I~ _ FILTER ASSIGN~ENT IS AD~QESSED TO RCEXVING ~TU, THEN U~ATE IG FIiTER d~ T FILTE~ FOR ~IU
O_ PA. S r~SG TO llSER DEV~CE IF UPDATED
9 MT jILTER SPECI~IES jASS F1LTER ASSMN~ ~SGS O~ PA~ jL
/_NON--hlJLL ~SGS
tIF f1L~ER ~IG~IMEN~ ~OT DtRECTED ro RE~C~tNr, B~ll9 ____ _ ~ PASS MSG_Tq USER_DEylCE JF CU~lREl'iT_~1T_F~L~ER-_ _______ _ ~ SPECIfIES 5~ASS ALL NoN~hluLL M~GS
00E~ 6F8~F~F0 Fi8S~T IB 1~0 ~fFF0 .. . . . ... . . . . . . . . . .. . . , . .. . . . . . .... . . .. _ . ..
r---~3 l.J
. . ~
7 2 ~ t~ r~ L t~ ~ N O D A N C B ~ P lJ F 1~ 2 ~h~A 64Ci/15~ C2 Ft~S ~t3 SUBSR ~B C t~ 5 SZ
~uE~ 2L)~ r~3C~ E~R l:~tc b ~SS10 / t)~ TC~ES
ril l Q R li E3 5~ R i1~ ll F ~ ~1 / U P I~ ~ T E I G ~ I L ~ E ~ ~ R E G 2 t ~I~El~) hl~S~3~Çi ~4 ~D ~ H~ 5 7UPI)AllE M7 ~IL~R (REG 3 u E ~ 4 ~ b i: !~3 4 -i j C ~l E C ~ P~ 'r F I L iir f~
F 7L~ 3FC2 R~S l~ t~ ANU a~ Nt: B~ ~3 SZ
F~ 31R~ 80 Itl I~h~; ~PASS hS~; IF F~EGIr) F I 2 D B ~ ~ k 4 0 B ~ ! t~ A I I I
~ DA LiUl~g ~IOl MATCH
0~F2 _ 6F~t~ 1 fAS51V! T~ 0~lQ!l /C~EC.K MT FILTE
0~F3 7~,~FC2 Rh~ Ll~ Ahb A~ hC IB~ A3 SZ
01~f4 31~l18~ It~ A~ ~PA$S P~SG I~ REQID
2D~ . W A I I 1 . _ _ _ _ .. .. . j . _ _ . .. _ .. . . _ . . ~ . _ . _ _ . _ _ _ _ _ _ .. . _ _ _ _ _ _ _ _ _ . _ . _ _ _ . _ ..
~F~
.. . . . .. . . . . . . .
~PRQCESS UNDEFINEI~ S~QTS
~PAS~ TO USER UEvIl:: IF ~lt ~iLTER ~PECIF~E.~
~PASS ALL NO~NULL ~G;S _ _ _ _ _ __ _ ___ .._. . _ 0~F~1 6iiiil~1k~il llh[j~F It~ t13it~
0ii~F5~ 7~03Fc~ R~S Lt~ AN~ Ae~ NC 13~ A3 S~
~FA 31~V~Ç11~0 J~) UAM
F ~ 2 U t~ri 0 tA ~ i 4 v~ f7 ~ ~, A I T l .. . .. . . . .. . . . . . .. . .. . . _ _ _ _ _ _ _ _ _ _ ; f - -- . . _ _ . .
~P~OCESS liu~L SLOT~ RANCIl Tl~ WAIt STATE
I~ ~ E F:i! U ~ 0! N li l, l f~ R E~ A I T i J l`I O P R Q ~ E '; S l h t~
~ _ _ . _ .. .. . . . . . . . . . . . . . _ _ . .... _ .. _ _ _ _ .
AIMr ~ T~T 1l172 CKATM~ 0155 Clsl~EL~ i CK~rMT 0i6;~ CiAT~ 007~1
-- - ~ i 6f ~30~ 1 Rn ~4 RSTAT jWR4~SrATl~S ~ D
~~0~3 7~(I14i~/I2 RR~ ANU j~ ~e ~30 A4 E3Z P~RO
~ANCH IF PKOCGO IS NOT SE~
0U~4 ~F~4tA~fl Ri1 ~j ~STAT ~WR4~STATU.S ~Q
--~-U~36 7i;~4~B2 RR6~ Lf~ A~IP A~ NC ~ P4 ~Z j1SYNC~) AN~H I~ I~SYNI: IS I~Qt SF't --'-'`------'-'-`-'--' '-'-----'---'--`'--` i'~NTEi~- h~ F-- `M~-SA-Gi''E-~-NF'~S E~rA~L~si1F~
~3 0 0 7 6 ~` 8 ~ 0 V~ #
6 ~ ~ U ~ 7 ~ S ~ L ~ A ~ c 1~ [) A ~
~SEl' tlSG SYhC BIT Ot ~O~JTQ~l REG~BI r 3 OF ~E~ 1) ~xANcH Tt) ~ ESS ~LCIT ~30LIND~RY
fENTE~ ~IERE -T5~- tlS~ ~`NC IS ht~T ~STA~~ En~-~-~----``- - -------` --------3 31~i2c~ lSYi~~Ci~ IO RSYNC ;R~8E~YNC
: _ 0021 ~iFB~FFE3 I~ ?FFE~
010~2 7~ Rf~R ~B A!`iU AB NG BD A~ ~ WAITi ~R~s~r M~rh~ F~r~c AND TRANSI~)It ENABLE I~ITS llF ~nNtR~
-- ---` -------- - ` -- - --~EliIS~ER~`G~----~O`-~ -If 1 __ _ _ ~ __ . . .
_ . . _ . _ _. ._ .. _ _ . _ .. . ~. _ . ,. _ _ __, __ _ . _ _ _ _ ~. ._ _ _ ___ ___ _. __ ____ ~EI`I'rER HEf~E AT ~llE E~ID OF PRat E~35II`J5 FOR Tll~ SLIlT
:: ~ ~ -- . _ . _ _ _ _ .
00111 318~ 0 ~AI'rl IO SI ~SET I~TERRU~ NA~LE
00l1 ~UB~ 4 WA~T ~R~ ~ WdIt ~nAST HERE fOR INTER~JP~
_ .. _ . .. . .. ... .. . . . _ _ _ . _ . .. _ _ _ ..
* ~
_ _ , . _ . . .. _ . .. _ ... . _ . _ _ _ . _ . _ ... _ . _ _ _ ~PRr~ES~ PO~ER ON~EN~R F~ TIALIZA~InN O~3 SYSTE~ QF
7 ~
_ _ __ ~FI~E PARA~Eri~Q5_IN ~O _ R~GISTERS
~~~ ~ bi0~h ~ ~F~0Cj~2-E ~ -N I~ ~YI #la02E jL~TA ~;T~ PER ~L~1T
. _ . .. .. . . .. _ . _ . . .. .. .. _ _ _. . _ _ . __ ___ . _ __ _ .
j f~
~ .
-~ .
t~lt~l 2L)Al~ t~ ,r ~1~ WRt~PS J~RlrE PRl)~PS R~tiIS-rER
01~? ~F~t ~i7F I~ 17F JBITS PR SLQT
2DA~ q~ \kT 1~ h~PS /~RITE P~PS REGISTER
01~t4 6Ft~ F If3 t!lV! ~L~l~F JENo OF Tt!~ DATll 01~ i 2UAk'~ WT t3~ ~Eur~ RI7f PEQT~ REGIsTER
JINITIA~ TF~A~s~;if 4ssI~N~lF~NT VALIJE~S
6 F 8 21~' t~ 3 2 t~ ~) 0 w ti! / I G F l L 'r ~ R
tal~7 6F~3P~0L It3 ~3 ~G50C fMT FIL~R
6F~C~tY?~8 I~ #~ RAN~MISSIQN PAR~METEf;
0 1 t ~ 6 F t~ ~ t;~
01~A 6F~A~F I~ ~A ~3F ~SPA~ G PARAt'ETE~ A ~!r**~ b~
01r~ F~90U~ R ~ 05 ~SLOT NUMBER ~ ~*~ *~ *
~1~C 6F~FFFF I~ h~ ~FFFF /SPA~1NG PAR~ME:T~R F~ ~r*~ *
Q l i~ l3 6 F ~ h B ~ l h ~ B 2 E~ `' S Y N C ~ ~ R M S G T r P A
t 21~A~ t~ ~T ~ HBU~ A #~ /~RiTE t~3FP (~
1 F -6 F ~ Y) I3 ~ B 3 0- ~ ~ ~ y N l:: 0Q Qs ,M ~G T y e ~.~ 3 Q_ . ___ ,_ _ _ __ _ ___ L) A ~ A ~ U F ~ R I T ~ t H El F ~ t P! ~
~F~III ACIL`JRESS SHOIJLD HE DI~F~ltE~IT F~)R ~A~ l3ILI
0111 6F~51~ 5 ~ R5 ~ t~IU ADDQ~:S!; ~*~ *~
01i2 ?l:l~ei0RCB I~T ~5 ~ UFA J~ WRI'r~ THBFd~2 Clil3 52UA5R~ r E~5 hHE~llF~ ~2 ~ RITE T~F~2~
4 _ 21~ h C ~ W 'l ~ 5 h H B U f A_ ~ A ~ _E! I U~ A t) q i~ _ _ _ __ _ ___~ _ _ _ _ _ 011~5 6F~Ip~ h #1~ A~ l)R ~F NETI~RK cr~
~311~ 2 1~ A h ~ 4 ~I T B ~ W ~ P lJ F B ~ 1 . . _ - ------ - - - - - -Zi117 6F~ h~0 ~ LEAR ~E~;T OF TlYf HE4uER ~UFFER
8 ~ AURR~WT I~U WhBUEA ~4 ~ ~ ~ Y ~ U A ~ T h ~ W h ~ 4 0 1 1 A 2U A~ t?~ H~ IF A ~5 __ _ _ _ _ __ 21jAr,~ W~ l~U hH~UF~ ~5 01lL 2UA~CC ~T U~ U~ ~3 011U 2~A~ C W~ 6G1 ~W~lJF~ ~
01 1 E ~ T M A ~ R ~ ~ T ~ T h E Pi A
01 1 F ;~ ; i;1 14 U I O ~ T ~ B ~ T M T ~q E H f3 01?~ lq0~s2~ __ IO R11A ~I~ST A ~TD _ _ _ __ __ ____ ___ t~l21 3~ 2al~ ir~ Rl1~3 ~RST 8 TMTD
~d l 2 ~ o g l~J t~ ti p ~ S E T G o ~ I N ~ I v I D u~A L A B I ~ S
Q1~23 31~!e)1C~ In sP~
012 4 2 l) ~ 0 ~ ~ A 41 ~ A I T
~ ___ .. _ .. .. ., , _ .. _ _ . __ _ ._ _ _ _ _. _ . _ _~ _ _ ~ ~ _ t~ ~ 4 ~i iPIi~CESs SLO~ ~OUNDAI?YYIENTER A~ TtlE REC.I'iN!I~lG OF EVER~i __ _ /UPDATE R~C 5LOT COIINl'ER ANI~ ~MT S~OT Cn!lNTE?~nETER
~3PPnRTUNIT~
_.~
014$ 6P8~0~,10 S~T~ 0 __01~b ?~B~6~A R~R "H ~ND A~ hC ~ AD ~Z RECSLJ~
~B~ANCH IF FIRST FSYNC sLnT NQ~ RECEIVE!) ~147 61C~7C~ RRS LH A0~ Z~ C BF A~ ~INC REC SLT ~R _ ___ _ 01~ 6FH0~FFF ~ FFF ~Q~ ~Ln~S PE~ ME
014~_ ~4C~FFCJ __ RRS L~ ~UBSR ~ C B51 AF SP ~Na ~KIP _ AT F~A~E ~ND
014A 6FaF~ 3F #~0 i~sr R~C ~LT C~R
014~ 6F~004 IB ~e, ?~B~J04_ _ _ _ _ _ _ _ ___ _ _ 0 1 ~ 70~D66A RR~R L~ B NC B~ AD ~Z REC~T
J~hNC~ IF ~#~N8~IT I~ ND~ ~N~BLE~
014D 61CÉ0;C0 ~S LB ADD ZB C BE A~ ;INC T~~T ~T, TR
,~ 1 4 E _ 6 F 8 ,'~ ~1 F f F_ _ I E3 ~ F f F S ~3 ,'~ 1 S ,l O T S ,~ F R F- R A I~ E
0ii,~ ~C~E~C3 s?5~; ,3L~ S!,JBS,~ A9 C ~b AE ~P ~NO SYIP A~ F~A~'~ ,~
015,~ 6F8ot0,~ 3 8E J~00,a0 ,~RSt "rMT SE~ CTR
7ERMI~,~ TR,ANS'`lIT oPPORTU~;IT'l~ F~IR ASSI",,~ ENT A,t~ USI,~!
.. .. _ .. . , . .. _ . . . _ ... .. .... . . . . . . .. _ .. . . . . . .. . .. .. . . _ ... _ . .
r--~.
, ~ ~
~L~,lS~
.
Sl,QT C(~U~
~UIl l~!OT C~IECK ~OR A 7~1T OPP U~li E~S ThAa~
0151 6f`9~iGl4~ ~U t~d ~SIAT i~ sTAfUs ~O~D
__ ~ 1 5~ 6 ~- l3 0 ~h h ~ kt 0 i ~ ~ 7 ~ F ~ ~ R ~ S 1., ~ A hi L~ Ç ~ ~ A ~ S ~
~154 2L~BI~!0$8C Bl~ fl t:KBT~I ~rP~A ~ 3 ~ CHECK FOR ~ OPP
t~ E~C~ ~KAT\~lT ~RS ~H ~lR ZA ~ A~ TM~ ~T CT~
1~1$~ 7~A71:~ RRS ~13 Ahl~ A~ ~C U~ AA ~TSC AhlD SPACIhl~ PhRAi`~ R A
&3 1 5 7 6 4 C I~ G 2 R I~ S l, t~ S IJ 13 5 R ~ Pl C R Ql ~4 ~ S K I P I F ~ R I~ ,, P r ~ J ~ A
~ ?~ $~,C,_,~ C~,B,T~1g,~,NU A T,MT OPPO~,TyNI~Y,,_ ___ ,_ __ _ _ ~lg~ 6F8~ ilt,1 I~ 4~ /CHECK IF 7~1IS ~i RETMT
ia15A 7~1j5~9~i RF?~R LO ANU AE~ C t30 AO t~Z AT~T
~hIS I~ RETMt 0 i ~ 6 F 8 ~ i C H E C K F n R !: O N T i\1 T I Q N
_01~ 70~iOF5~ ~5 L~ Al`ll: AB_NIC ~0_AP SZ
1~ 1 5 U 2 D ti ~ A ~ I~ R ~ T ~1 i /~HIS I5 CONTE~TI~
6F~v~FfF I~ lilFFF ~Rt~AD l.S i~ BIYS QF P RA~
lalsl~ 7æsk^0~qGJ RRR~S LE~ ~NI) CIA hlC 13~ A0 Rt~AI~IU
0~ 6~F~C~ RR~ EI ~U~SR AB C ~ ~C F~P I~ECSLT
~161 ;~181!Gl~QI Ar~r In ~ 7TMT lli~M A PUL~E
iSAV~ J? OF sioi Ti~~r ;I~ID ~0 PRDCESS REC sLn~
~162 ~ h~l~ R~R l.f3 ~)R ~A l~lC B6 ~E ~5 ~ECSl,~
~n NnT ~ECK ~OR B 7!lT OPP Uh~ES~
T ~
1 6 3 ~ F ~ T M T ~ A # ~ 4 ~ M
~1~4 7~14FC2 i~2S Lt3 Ahl~ A~ NC ~ A4 ~Z
~1~$ 2O~6t;~` ` 8R `-f3~ R~CSL~ M~ ,~~ GB PRPC ~~~~~~~~-----~-----~~~----~-- -C ~U SLOT
~16~ ~E~1~E7CU R~S I~B 01~ Z~ B~ ~E /~lR~T~T ~sLT ~TR
01~7 7U~7t~vl R~S ~ At~l~ A~ hlC B~ A8 /TSC AhP SPACI~IG PA~AnETER
~lfi~ 641~CZ R~5 ~H Sl~SR AB C B~ 52 ~SKI~ IF WRU!-I~Ln~ NUMBE~ 1 ~165~ ~U~fifi~ BR B~ 1~ R~CSLT ~Jt~ ~ TM~ tlPPDR~JNIIr NrE~ ~Ff?~ FOF~ ~3 Tr~7 oFPnRiU~ITr ~116A blf`~ t~ IE3 t3GI $~2~Y~ ~C~lECK IF ~HIS IS RET~T
7 u h h L1~ L~ A f~ R L~ R L~ ld A i~ ~ A B ~ D ~ i 13 T M
~THIS I~ ~E7~1T
------ ~ ~F~a~s~ p ~ GHE;I~ IF T~IS IS CoNrNTID~ ~,,nt U~61~ 7~B~DF~2 __ ~RS LLj AND AB N~ AD _ SZ
~1 6 E 2 V~ Ei l3 5 C ~ ~ R ~ T M T
~THIs I~ C~NTENTION
016~ 15FB~FFF I~ ~~ #~FFF ~REI;D ~S 12 flITS DF P RA
la17~ 72gL?~t'~ S ~ AN~ DA N~ ~0 A~ RR~.N~
0 1 7 ~ Q ~ S lJ ~ S ~ A l~ C ~ C P j R E ~ S L ~
~172 21)AB~1~C 8~M~ WT ~ FB ff~ ~WRITE ~LT ~ A ~ 0 TA~r I~OR B
0i73 2i~AAS~ i^iT ~A ~jt31JF~ ~4 ~I~RITE SP FA~ â ~N T(~ TMT tl~
~17q 2V~VO11 14 W~ ~V ~11H~FB ~:$ ~WRIT~ CNTRL REG TO ~MT ~DR 8 0175 ;~iB~ Cl:~ IO TMh ~TMT hE~1 ~ PULSE
/S~V~ F SLGT T~IT AND GQ PRDCESS I~EG_S~,Dr 0ï76 6~;E~6~ R~l3R Ll3 OR ZA ~JI: ~7 ~É ~ RECSl~T
~ _ ___ __ ___ __ _____ __ __ __ _ ~19A
_ . . . . . . . _ _ . . . . . . . _ _ _ _ _ ..
~PROCESS R~CFIVE 8l.OT~CHECK IF _REC ENA~I.E I~_SET~W~T IJ
EC t~ HAS LEEI`I REtEI~/E~ tREC ~DR aF~ ~iAs ~EEI`~ RE~ET3 ~IF THIS IS ~iLOT TMrD ~Y RE~ VING ~_ C~ECI~ Tu~T
/TI~ AS ~liCCE~SFUL
~RAN~H T~ ~OUTINE 70 ~ROCESS REcD ~LnT ~)~PE~DI~IG O~l M~
. .
.....
~ ~L
,,, / .
~ . "
L~19A ~ 0~ tECS~ SI ~SET IN~ERRI,IPT ENa~LE:
~1~TER~UPT IS ENA~ D TO PREVE~ r)EFI~T~E l,~OP~G r~ljE
/tU S~ME Mh~F~I~C~
6F~rA~8~1 RE~EN QU ~4 RSI AT ~R~STATl~ WORL~
~ 1 9 ~ ~ F ~ C~ ~ r.1~
f/119~J j~h~!46fi~ RR~R Lli ANU AE~ NC l~ A4 BZ ~ECE~l ~3RANi.l~ R~C E~ABLE IS N(~T SET
h~4~r~ Rj1U~f~ R~ ~4 ~ST~T ~h~4~ STATUS WORP
01 ~F ~F ~ 0 I ~
~1A~ 7'~8f1~fC2 RR5 ~8 A~O ~B NC ~ 4 ~Z
~2 _b f R _11 ~ 5 R E E N R E C E I V E n f~11A1 2~ fi7~ E~R ~L~ ~ RHI)~FK ~YAI'r FO~ R~C H~ FF
~1A2 3~ A~ IO R~I ~RE~T IhTER~lJP7_ENA@~E _ _ _ _ _ ~CHf CK IP IHIS SLOt I~IAS ~n ~Y THIS ~IU
_ ~ 1 A ~ 6 l- 9 4 l'~ 4 ~ S T A T _ , . . . . . . . .
~1A4 ~4C6Ff C~ f~RS LN S1~SR A~ C B6 AF SZ
01 A b 6 F ~ ,L~ , ff ~ B fJI ;j1 ~1A7 7~t~6~ SR l~ ~ND AB N5 I~L~ A4 B~ C~S~REC , ,, ~IHIS IS AN ~Sl,OT TMTt) ~Y THIS 6lU
_ 01A8 ~I~L~h2~L-~I IO ~ffA ~FtES~T ~ Th~O
~:H~f.~K Tt~AT OA IN RI~Ç HDR E~1JF ~ ADI~R nF hIll _01ASI ti~ FFFQ I1~ F~E~ ~MS 12_i3I~'~_Q~LX.________.__. ------------------------01AA ~2~V;~ C WQWl15 l,.i~ A!~l~ I)A ~IC ~3~ A~! RH~3UF '~;~
f~1AI~ fi~1F~5h~3A RRE3R Ll~ SUI~SR f453 C f3~ A!5 a~ ~3 - - joA Ij~S NOT ~lATCH ~ IND RETMT REGti!~
UIAL. fi~E~Li4~QI,t It3 ijL;' Jt4fA~fA ~SEI ~IT 14 IN 1~ REB
IOlAlJ ~jL'~L)U~iFl.~ RRt~R LH l.lR ~13 NC ~l) AVI El PRnSL,T
~f~ Tl;HE~ ~ NO'r RET~lT f~EO ~ ~
i f~ ~ 31~ M A ~ R I: L E i S F T il T M E M A - -- - - - -- - - --- - - - -1a 1 A~ 61; ~ F~ ? bflFFF ~ AR B I T 1 d I N C'r~L REG , _ _ 7~BU~6F~ Re~R L~ Af~ A~ NC B~ A~ ~ P~t1SLT
fl~ 4C7~fC~ CK~jtEC RRS Ei~l 5U~SR AE~ C F~7 AF SZ
t3 1 l3 2_ 2 U B ~ F ~ P ~ t~
01H3 bF8U04t~ B ~t,~ ~4~
~l~4 7~ 46EA f~ L~ ) AB NC B~ A~, B~ PROSI~T _, . ..
~THIS I~ A B~SLOT TMTO B~ THIS ~IU
~1B~ 3l~V~t~124~ lO RMB ;RESE7 ~ TMTO . . ... -----.
~CH~Ct~ ~H~T 0~ E~ HDk ~UF ~ AODR QF
~1~6 _ 6F8~;f~f~ IB ~ ~F~f5 ~1~7 72~ C f~RRDS L~ ~ND DA NC ~~Z A9~ RH~UF ~~
_ 01B~ 64P~5~EE RR~R LB SlJ~SR A~ C ~ AS, ~Z O~3,, ,,, ,,,, , ,,,,__,, ,_ , ~OA r)~S ND~ A~CH ~ ~ND ~ET~T REQ~D
01139 ~t~8~12~1t~ IB ~t~ ~2~'~0 /SEt BIT ~ N ~TL RE~ _ 01t~A 6C~lJ06F~ F~F~ OR API NC I~D ~ ~ PR0sLrT
_____ __ _ _ _ ~OA MAtCHES _NQ RETI~ll _RE~ I V _ ~_ 180~140 IQ RTMli ~RELEASE TMT ME~I ~
0aHl; 6~DFFF IB 1~ tr)f;FF /CI,E~R Bl`r ~ IN CTl, REG _ _ ______ _ 01~v 7id~[)P76F~ RR~R L~ AhD Al~ t`lG ~P A~ B PR~SLT
01t3E ~U~IB~ PRtlSLT ~R ~ ~IO
- 7BR~I`IC~1 ~0 SERVICE ROUTINE nEPEi'lPING ~IN RE~EIVE~
~MEss~GE TYf'Eq~ ~RANCH ~O I ~O V~TOR
____ . _ _.__ _ _ _ _ _ . _, .. _ . .. . . _ _ _ _ _ . _ _ _ _ _ . __ _ _ _ .
~b*IMPORTAhlT~ ~LI. RECEIVE ~IL~S~G 5E~V~E ROUT~NES
751~0ULD STA~T WITIIIN 0P0 Al`l~ 0FF ___ _ _ _ _ __ _ _ ~TART~ O~TION MESS~GE TYPE MEssAGE TYPE~ COI~:
.. ... _ _ . _ . . . . .. . j _ . _ . . _ . . _ _ . _ . . _ _ . _ _ . _ _ _ _ _ _ _ _ _ _ _ _ _ 7 03~1 FSYI~c ~QI
... . .. .... .. . . . . . . . . . . . .. .. .. . _ .. _ .
J
t~
`...
T d 2 o ~ a I G :! I
__ ............... . . .. . _ ..... . . .. .. .. ..
~ ~A~ DATA ~SSIGN~9EN~ 4?/4~
QCH SI~TIJS ASSIG~ Nl 4 ~ q~a f Il.TER A~5Içr~MENl 4~
j ~F8 uh~u~FINEL) ALL R~ ING
/ IdFF ~ L~ 0~
. . . . .. . .
_ . _. . , _ ____. _ ._ __ _ . _ . _ __ . _ ~_ _.. _.. _ _ ... .. _ _ _ _ __ _ _ __ ____ .
tP~DCE~ fsrNc-~ Tl^IIS F~IUrIN~ ESTA13LISI-IES At`~r~ MdTN~A~NS
~FRil`~lE SYNCI~nNI~ATaON~ IT i1Ar~HES ~HE fiE~ SLT C~ ~ITI
~lllE SLOT NUI~lBER Il`~ THE FSYNC MS~ IF THI~ !~I OT ~ ~ 3 OhSF~CUTI~E ~S\~ S!_~TS MA~hEs THEN F5YNC IS E~iTA~i.Is ~IF T~IE SLOT ~ IN 2 OF l~ ~nNSFCUTIVE F~YNI~ SLr)~ t~nF!3 AtCH THl~iN FSil"C AND ~F~ANsl`lIT E~ RLE~ ARE RE~3E~
~3Q 6i~8~ ?1 F~YNC IB t~ 002i iC~lEl::K Ml' FII T~R ` --Q0;$1 7i~1BE~31iC2 f~RS L~ ~hi) a~ NC ~ ~3 5~
01~J32 31BQ~ IQ L)A~1 ~PdSS TQ IL1 I~ REQ~D
01!133 ejF~Q~10 Rl) t3!~ RH~UF ~t4 ~i~R~: RECI~_SLOT ~
i~U3S i~0~41:~112 ~ B t~`!l A13 I~,C ~ AD BZ FFSY~C
i~Ri~CH IF T~E RECD SLOr IS THE FIR~T FSY~G Sin~
64C~FC2 RRS L~ 5Ut~SR ~4H C i~ AF $Z
75KIP IF f~LGI~ SLnt # IS EQlJ41. TO f~ LT ~TR.~ I~tATcr Q037 2U~e~112;~ 1~# t~0 ~ I~S~ Q
13~;S9 7~B~Dla~ RRBR L13 A~C) A~ NC 1~ AD ~Z FF8Y~IC
~13Y~ TR~NS~lIr ENA~I.E IS NPT ~T
0~1;5A ;)ll~Q2~0 _ IO SYNt: ~SE~r Fsyr,~C ~L~G
Q10 3 ~ 6 F 8 L~ 21~ 2 ~1 Q~3C _ 7~ D~ RR~ LEI ANL) AB NC a~ Ab ~Z l!AIT1 iB~NcH IF Nb MAfi~ CONbITlOh hAS NO7 ()CC11~ E~i ~1031~ _ 61Cl~c0- -RRS l,.t~ A[~l~ ZB C B1 A~
1il~3F ts4cQlFc2 RRS ~ UHSR Al~ C f3C1 A1 ~
tSt(lP AT E~l) OF 16 CONsECiJ~IVE FE;iN~ SLnTS
0~40 21;)~i0~Q4P~ iAIT I
0 ~ 41 ~F 810~ 1 #~)~ R E SE T w R
0~2 6F8~FFDF _ IB ~0 ~F~PF
8~3 7~D0040 RRHR L8 ANU ~ NC bD A~ B ~l~aITi 0044 ~E~F~7~ FFSYNC R~5 E~ OR ~A NC_~F ~_/ENT~R F~ FtQsr F$r~c SLOT
0 0 4 b 6 F ~ 0 ~46 6FB~00ls ~ O ~ 1u 0~47 fi~BL~ RR~R L~ OR AH NC 13~ A~ ~ WAI~I
0~4B ~F8~20 RSNrJE~ 02~ ~ ~N~ER_IF NO MA~CH
0~49 70~bl 3A RR~R LB A~D AB ~c ~7 AD B2 FF~LOS
/~RANCH IF _ IT T~E FIRST NO M~C~
00~iA 6F~10~0 I~ Bl ~s~0 iRE~E~ WR1o E~ rER FOR L~i85 Df isY~c ~ ~~~~~~~~
~4~ 3l~2C0 IG ~8Y~C _ ~RESE~ FSY~C ~I.AG
b6~4c BF~FFC8 I~ -FFC~3 004U 70~U00~0 ~ ND_~B ~C ~D ~0 B WAIT
s~T FsiNc~ FI~S~ ~SYNC LDS~ TRANsMlT ~ LE ~IT~
~04E 6F~la00l _ Ff~LOS lH Bl ~000l OFIRST O~ _ 16 CO~SECUT~VE_ Sl.OTS
0~4F ~F~0~02~ IH ~ ~0020 0050 6C~DP~0 RR8R ~B_~R A~ NC 130 A0 B wA~T
oS~T FIRST ~SYNC l.OSS ~IT
~U51 ~lC107C0_~FSYNC_RR5 L~ ~DD _~8 C_~1 A~-/EN-~ER_ lrO E~l'Aa~I~H FSYNfC _ _ 0052 6F~0~0~3 IB R~ 03 ... . _ _ _ _ _ _ . _ , , ~ .
~i ~7 ~ ld ~. ~
S4~P!lFC2 ~h~ l t) ~UBSR A~3 C B0 A1 8 ~SISIP IF 3 ~OI~JSECUITVE MAT~i'`HI~G SLnT ~1UMBE~i?S RI~CEIV~
la ~ S 4 ~ l~ b ~ C ~ 4 r" ~ h A I I 1 010~5 3~ `h2~l~ 1D ~;Y~ SLT Fsr~C fL~
id056 Fl~l`0G.e;4 ~ 0 ~004 ~ VI 5 7 ~ 7 ~, ~ Ft f~ S . I ~ O R. A ~ I.C~ A 0J
01~ 6f~ . F I t~ #~ lF
1~5~ 729t~ 0 R~RI~S Li3 ANi~ i~A NC EIE ~ RSLOT ~Ri~ AC) Si 0-~ r~FFSE~T _ _ )aL~5A 6Fl~4tQl~ ~Z Ii3 1~4 ~ U,~2 01~5~ i;l q7 C~ S l i~ Ai~i? t B ~ E A 4 ~ I Ni" i3 Y 5! _ _ _ _ __ 005i; i50~i-F~A4~ Q~R Lt~ Al)l~ Ai~ i3E AF B l!i~ITl T ~1 1 S ~ t Ç T F~ G _ R E C S ~ ~_ C T 5~ ~ ~ L O T . O F F S i T _ _ _ _ ___ U ~
~P~[~t;~iS~ RTP~ ~EAO I~l AND STORE T~ E R~TR~S~ SS1nN
'PA~9~i Ti;R_ :1~ WRC___ _______ __ _ _ ___ ___ 6 ~ h ,A ~ R T P I B ~ 5 L~ I~ ~I l . . . . . .
0~l 7~ 3Fi.,2 ~i?S j~H ANU AB ~ 1 a3 SZ
2 ~ n 4 A~
~;3 ~F5~C~,t~ Ri) ~C i~HBUF ~$4 /~RCY RTP
0 i 6 4 2 I? B i ~ rA l;S 4 Ijl i3 R 1~ 3 b A I T 1 _ _ _ ____ _ _ _ _ - - - -- - - ------- --------- --- -~ Y ;f) 7 ~
.. .. .
~n~l'A M~ssAGE
~IF MT FIi TÇh SPi~CIFItS PASS ALL i~Oi'l~NiJl,~L_~l$G~ tlF?._ 7THi~ ST SI~NIFIi~ANT ~2 BITS OF
~Tt1E i~ST2~A`rli~N Ai~DRESS Of RECIVE~ SLnT ~ lE.5 ~i'`tJRi~i SPUNDI~G ~I)l)Ri..5S OF T~iE RIU T~lEN A ~E~T Ann~ MAT~
~P~JLSE IS GE~IERATED SO Ikl)IÇAt- REt~ SL~T R~DY ~O TilE
JI~o-SECTII~
. . . . .. . .. . . .. . . .. _ ... . . , , , , _ , , _ , , _ _, , _ _ , , _, , _, 0 i~l 7 1~ 6 f 8 Ç~ O A T ~ # P ~ C ~ E t ~ ~ T f ~ L T R
7 ~ . 7 ~ ~ 0 3 1 f) ~ t L FI I A N P ~ B I~I C B 71 A 3 P ~ O s f~ A M
l~07~ ~iF~7FlFFI,l IB E~ ~f FF~I
0U73 729l5l~0~ RRRDS 1,~ ANI~ C~A NC E3~ a~ RHi~U~
~WR0 ~ OEST Af~UR AND ~FF0 0~!174 _6~C05FCZ R~S 1 1~ SlJ~S~ ~B_C I~PS A5_Ei2 iS~IP IF DES~ AD~R llATCl~ S
0075 2UBk~Q~4it 13~ t~0 E~ AXT1 0~76 ~lf30~ PSl~A~ f)AM /DEsr ~C)bR M~7;~ PULSE
0077 2DB~lU04~1 B~ BU f3 WAIT1 _ _ .. . _ ______ __ . _ _ _ _ . . _ ~ _ . . . _ ~ . _ . ~ _ . . . _ . . _ ~#~flt7 ..... . . . .. . . . . . . ......... . _ . .... . _ . . . _ _ _ . _ _ . _ _ .
~INFO~ TION GRDUP MESSAGE
7IF ~T FIL'rf R SPECIFIgS PASS ALL No-N-~NuL-L M9G~S _ _ _ __ ~OR IG FTl.TER SPEC~FI~S PASS Tl`II~ ~G, C)E~T
_____________ _~ADV~ tl~T~H_PU~SE_IN GE~IERA~
/
0080 ~FR0~t04 ~ IG~P 1~ 001 ------ i i4~03F C2 I?RS L13 l iNb AE~ ~iC e 0 A3 S7.
0U~2 7;2902~ RR~i~S ~ AN~ A ~`JC E~l A2 R~IB0F ~2_~Z
0~3 3180~ t~ I~ bAM ~PASX T(J IG
__ 011~ 4 _ 2 ~ I 4 ~ _ 9 ~ H PJ ~ I I l_ _~ __ __ _ __ _ .. . . _ . . . . . . . . . ... _ . .
. . . _ _ . . _ . .
3 .~
~ # ~
. ............ ) jSTATU~ $SAr~
~IF ~T FILTE~ SPECI~IEs2 A3 PAS5 AL~ O~l\IUl L MSGS
~ ~3 PASS ~ S'rA~uS ~sr.s i C~ PASS t)lRECTEI;) STATUS ~1SG~
AN~ ES'r ~OOR h~TC~lES
5G IS PASSED ~0 USER ~)EvlcE
6F~11"1~0~ STA~uS I~ #~Qll ~ALL Sl,DTS OR A! ~ STATLJ9 01DS~1 7~ !3f CZ ~R5 L.~3 Ahil) A~ I~IC ~ A3 0~0264 ~R H~ StUAM
~ ~ g ~ h ~ 13 U ~ 9 J b ~ f~
~i~9~ 7~ Lh4Z RF1iR L~ Al`lli ~ Nt~ A~ ~Z ~AIT~
S 5F~JFFf~ IB ~ #f~F0 ~ ~~ ~~~ ~~~~~
7 2 5~ r,l ~ R I~ S L 8 A N ~ l) A N C ~ ~ ~I Q R I~ F~ U F ~ 2 LqH~7 fi41:;h!1iFC2 RRS L~ ~iUaSF~ A~ C 1~ A5 SX 7 ~4~1gA 2U~3~Q~4t3 i~k i~ WAIT~
3 ~ i L~ S T V ~ M f o ~ a M i P ~ S S ~ ~ J--~--~----~~~~ ~ ~ ~~~--~--~~ --0UgA 21~B,.i~ Bt~ ) B WAIrl .. ... .. . . . . . _ , , -- - ----- .- .. .. . ..
.. ... _ . _ . .. .. ..
/~4T4 S~Ot ASSIGNME?`IT MES~GE
jIF hSSI~NM~Nf IS A~ ESS~D ln THIS
~1U THEN ~ APPf?OPI~IE S~nT NUM~EQ~ SP4CI~IG P~RA~E~R
~AN~ IN~1VIUU~L/ CON~EhTION ~IT ~RE l;P~4rE~
- - - - - - - - - - - - - - -g3~A~ lFFF~ I~TASMT I~ #FFFPI
` ----5~-~A~ 72Q~ `L~1 Rf~PS l~B Ai`i~ ~A l'JC Ps~ A0 ~H~llF #~ -- -0~AA ~4C05F C'~ RRS LR SU~3S~ ~8 C El~ A5 SZ
~CM~L~ f~R DA MArC~l 0~A~_ ZD~ f4 ~R ts~ DTAS3Ql ~NU MATCH
~ O A h A T C i I A S S I G N M E I~ T ~ ~ R ~ H I S B I
0~bC hF~0L?FF I~ 0L FF ~ET ~iG ~YPE _ __,,, ,, ,, _,, _ ~
AD 72~ M~ R~0S L~ Aj~D DA NC B~, A0 RHRUF ~i ~~ ~ ~~~~~~ ~
~0Ae; 6F~4~42 I~ 4 ------0~AF- 6~f 4~J2L~2 R~ LH SU~SW AB C B4 A~ BZ D~ASI~
~CQ~IT~NTION ~ATA SLO7 A~S~NT
Oe~ 6F8~.EFFF I~ Bh ~EFFF J~ESEI INDIVIDUAL A BIT
0~l70~D0~C~ RRS L~ ANO ~ NC ~D A~ , ,_, _ _ _, ~___, _ _ ____ :
~B2 6F8~04~0 I~ 040~ ~SE7 ~IE~; ~5~t~iT I~IT
~0B3 6CaD02U~ RR~R L~ t~R A~ NC ~D A~ B OT~S20 /INl)IV14UAL DA~A Sl.nT A85MN~ ~
0~B4 ~F~0l~ OTAS1U_ IE3 ~ ~tl4~ SE~ lND A ~Ir AN~ NEW A ~S~S~
~l~ 6CbL~71:~ RRS LB ~R AB N~ ~D A0 f91~0~1~ UTA~0 R0 B~ RhBUF t~4 ~8LoT _ b A
0~i6F9b0~14 Rli ~A ~t~tiUF ~5 7S~CI~G PARAI~ A
0~86F9~0B18 Rl) a~ RH~uF ~6 ,~E~T 4DDR A
d~s~L~A~0~,C4 ~ 80 WHRUFA ~ t ~()E~ H~'TllER TO _ PASS ~lSG tDA M~YC!lES) 00HA6F~000~3 I~ 0~0~ ~LL SLOTS OR DAtA ~âlqNTS
7~0~0a2 ~R~R-L8 ANV A~ NC_~0_ ~3 ~2 ~ITI
00~C7VB0Ç~2FC B~i B0 B I~TAS40 ~ET wtlE~h~R TO PA5S ~SG ~r~4 ~OES NOT MATC
008D 6F~ 01 n7AS3~ IB ~0 #00~ A~S Al.L SL~TS ~NLi 0~B~ __ 7~3~4Z RR~R L~ _ ANt~ _ A13 _ ~C B0 A3 ~ iAIT1 b~HF 3l~0~i80 DTiS4~ IU L~AM ~PiSS MS~
~ 0 ~ 0 2 ~ 4 ~ 8 h A I 'r 1 .. _ _ _ _ _ . _ _ . _ . . . . . . . . . _ _ . _ _ _ . _ _ _ . _ . _ _ . . . . . . . . . . . .. . . ... . . _ ~ . . . . . _ _ _ . _ _ _ .
_ _ _ , , , , , , . . . -- -- -- --.... _ . .
~SrArUS Sl.~)T ASSIGNMI~`iT MESSAGE
_ _ /UPDA~A ST~TUSi ASSI~;N~!EN'r I~ I~A IN_$G I~ATGHFS__ _ ___ _ .
~IU Ar~DRtss ~PASS MSG to USER DEVICE IF M7 FILTE~ SPECIFIES
PASS ALL MSt~S OR PASS ~IREC~P ~TAIUS ~LQT
SSIG~ T MESSA~S A~l!) t)A MATCllES
la~C~ 6F4~'FFI~ ~TASI~lT I~ FFFX
0 L~ C g i 2 ~ B Fl ~ R D S L t~ A N r) l) A IY C ~ l? H ~ t 2 ~CHI~CI~ FtlR OA MATC~
0ilt:A~4C~5FC~ RRS L~ SUASR AR C ~0 A5 SZ
klUC~137 ~ S r AS;~
/I~A PIATCH~S ~ UPUATE ,~SS~1NT
C C _~ F ~ Pl F F_ _ I tl ~31A_# ~ ~ F F /.~ E T, ~ S G T, Y P F, _ , _, _ _ ,_ _ ,, _ _ _ _ _ _ _ ~ ,, ~ CU7~ Ifl~4 RI~K~S Lt~ A~iD IJA r~ a R~l~uF ~1 0 U C E 6 F ~ a ~s ~ a ~ T
0~CF64F4u3$2 ~R~ C~ SUB~R A~ ~ ~d A~ ~2 StASl'~
~COI~lTENrInN ~T~TlJS Sl OT ASSIGNM~hT
01al~F~F7~F I~ B~ F7Ff ~RES~-I INQ B ~3IT
~4 0-D l- _ 7 0 a l~ 0 7 ~ S L ~ A ~ ~_ A ~ N 1;~ L0____ _ _ _ _ . _ _ __ _ _ . .. _ ~_ i F B ~ z ~ $ 0 2 ~ 0 / S E T ~ E I'I P A S S ls h; l~ B I T
D3_6Ct~ 35~ RRI~R LB t~R Af3 NC e~u A57 P~ ST~s2~
IpuAL 5-ATUS ~LOT ~SS~G~lEl`!t b~uP4~F~ AH0~iTASl~ IP I~U st~A~?!0 ~S~ ~ip ~ ASS!1NT AN IE~ 13 ASS14l~T I~I . .
0~56~Du7~RR~ ~f~ QK A~ ~C ~ A~
6 F Y.~ S T A S ~ B ~ R h ~ u F ~ a __ _ _ ~7~F9~Q~ P ~ b~F ~5 B F 9 ~R ~ H ~ U F ~ fi 0~1)92UA~1fl4 h~ llF~ ~1 ~DEl-~RMI~ HEIHER tO PA~S M5rli . _ _ _ _ . _ . _ . ... ~ . . .. , _ . . . . .. _ . _ . . .. . . _ . _ _ _ _ . _ _ .. _ _ _ _ . _ _ _ . _ fOA ~A~C~ES~
_~Pa ~F~ 0~$ ~ALL SLO~iS pR ~)ATA ~SSMNT S~IlTS
0~L~ 7~ Z f~Rt~R ~ A~l~ A~ N~ H~ A3 BZ ~AIT1 __00UC_ ?D~L~037C t3R ~ sT~saQ! ,,, , , ,, . . ... , ._ .. .......
~PA 1)1~ NUT MATCHi, _ _ _ . _ . _ _ _ _ _ .. ... _ . __ ~ . .. _ . _ _ _ _ _ _ _ ___ . ._ _ _ ___ _ _ _.. . _ .. _ . __ __ _ __ _ __00DD 6F~00~1~1 S7~S;~I~ I13 ~ ~t0~01 JALI. ~l QTS Ol`Jl!!Y _ _ ~5! D~ 03~a2 R~t~R Ll~ l) A13 ~`IC ~al A3 ~Z ~ r1 ... . . - . .. .. - . - . .
F 31~ STAS~0 IU UA~ /PA8S ~SG
0 E 0_? QB 0 Ç~ Q _~ R_~ Q_ ~ W A ,I T I _~ _ ____ ___ __ /
~ILTER ~SSIGN~NT MES~A~
~I~ _ FILTER ASSIGN~ENT IS AD~QESSED TO RCEXVING ~TU, THEN U~ATE IG FIiTER d~ T FILTE~ FOR ~IU
O_ PA. S r~SG TO llSER DEV~CE IF UPDATED
9 MT jILTER SPECI~IES jASS F1LTER ASSMN~ ~SGS O~ PA~ jL
/_NON--hlJLL ~SGS
tIF f1L~ER ~IG~IMEN~ ~OT DtRECTED ro RE~C~tNr, B~ll9 ____ _ ~ PASS MSG_Tq USER_DEylCE JF CU~lREl'iT_~1T_F~L~ER-_ _______ _ ~ SPECIfIES 5~ASS ALL NoN~hluLL M~GS
00E~ 6F8~F~F0 Fi8S~T IB 1~0 ~fFF0 .. . . . ... . . . . . . . . . .. . . , . .. . . . . . .... . . .. _ . ..
r---~3 l.J
. . ~
7 2 ~ t~ r~ L t~ ~ N O D A N C B ~ P lJ F 1~ 2 ~h~A 64Ci/15~ C2 Ft~S ~t3 SUBSR ~B C t~ 5 SZ
~uE~ 2L)~ r~3C~ E~R l:~tc b ~SS10 / t)~ TC~ES
ril l Q R li E3 5~ R i1~ ll F ~ ~1 / U P I~ ~ T E I G ~ I L ~ E ~ ~ R E G 2 t ~I~El~) hl~S~3~Çi ~4 ~D ~ H~ 5 7UPI)AllE M7 ~IL~R (REG 3 u E ~ 4 ~ b i: !~3 4 -i j C ~l E C ~ P~ 'r F I L iir f~
F 7L~ 3FC2 R~S l~ t~ ANU a~ Nt: B~ ~3 SZ
F~ 31R~ 80 Itl I~h~; ~PASS hS~; IF F~EGIr) F I 2 D B ~ ~ k 4 0 B ~ ! t~ A I I I
~ DA LiUl~g ~IOl MATCH
0~F2 _ 6F~t~ 1 fAS51V! T~ 0~lQ!l /C~EC.K MT FILTE
0~F3 7~,~FC2 Rh~ Ll~ Ahb A~ hC IB~ A3 SZ
01~f4 31~l18~ It~ A~ ~PA$S P~SG I~ REQID
2D~ . W A I I 1 . _ _ _ _ .. .. . j . _ _ . .. _ .. . . _ . . ~ . _ . _ _ . _ _ _ _ _ _ .. . _ _ _ _ _ _ _ _ _ . _ . _ _ _ . _ ..
~F~
.. . . . .. . . . . . . .
~PRQCESS UNDEFINEI~ S~QTS
~PAS~ TO USER UEvIl:: IF ~lt ~iLTER ~PECIF~E.~
~PASS ALL NO~NULL ~G;S _ _ _ _ _ __ _ ___ .._. . _ 0~F~1 6iiiil~1k~il llh[j~F It~ t13it~
0ii~F5~ 7~03Fc~ R~S Lt~ AN~ Ae~ NC 13~ A3 S~
~FA 31~V~Ç11~0 J~) UAM
F ~ 2 U t~ri 0 tA ~ i 4 v~ f7 ~ ~, A I T l .. . .. . . . .. . . . . . .. . .. . . _ _ _ _ _ _ _ _ _ _ ; f - -- . . _ _ . .
~P~OCESS liu~L SLOT~ RANCIl Tl~ WAIt STATE
I~ ~ E F:i! U ~ 0! N li l, l f~ R E~ A I T i J l`I O P R Q ~ E '; S l h t~
~ _ _ . _ .. .. . . . . . . . . . . . . . _ _ . .... _ .. _ _ _ _ .
AIMr ~ T~T 1l172 CKATM~ 0155 Clsl~EL~ i CK~rMT 0i6;~ CiAT~ 007~1
5 D A ~7 k __ U ~ A S l Çl ~ 4 ~ T ~
Diis3i~~ BD I~Ti~ Bf b~AS~T ~B
EFsYhl;0~51 fASS1~ F2 fASS~'rolflEq F F S L O ~ 1 i E F F S ~ N C ~ F S Y N ~ 0 I~RP ~ INTSRV ~ _PlSYNC0~Q2 NUI,~ Ff P~O~LT~llBE ~wRC~N0iPI~
R~C;EN ~ REI::SL`I _ ~119~ _ RHU~FR01QE
~sNIJELJ1~4E~ RTP ~6~ SiLI13t)014!!i 5TASl~~r3a STA~;2Ç~ D6 ~ 53~ a0Dp S T ~ S ~ A ~ M T ~ A T U S~ ~ 9 ~
~i T D A ~ $ 0 5 ~ _ _ U N O E ~ I T
__ _ _ _ _. _ _ _ _ . _. _ _ _ _ .. . _ .. . . _ _ . _ .. __ . . _ __ _ _ _ _ _ _ _ '~ '` I
r ~ , APPENDIX II
CLUSTER CONTROLLER ASSEMBLER LISTI~G
= LD @PAADD,DE
ORG 0,6000H LD HL,8402H
LD SP,6FF~H LD @DMAMAD,HL
JP START CALL DMAP
LD A,01000pl~7 ORG 4~H,6040H LD @8400H,A
START:DI LD A3~1000001B
IM 2 LD @8408H,A
;5ET START STATE LD HL,BDMAC
LD A,llll~lllB;TEMP SET 0, ~HL
LD @HLATCH,A SET l,@HL
LD @CTRLATCH 7 A LD IY,BPNTR~
LD A,01101110B LD HL95LOTSZ
LD @MODE,A LD DE,4 LD A,00100111B ADD HL~DE
LD @COMMAND D A PUSH HL
XOR A POP DE
LD @TXINTENM,A LD B,8 LD @ACTIVE,A INITl:XOR A
LD ~BDMAC,A PUSH IY
LD @WFORT,A POP EL
~D @DMAMSK,A PUSH DE
LD @8408H,A . . LD DE,15 LD DE,VTABLE ADD RL,D~
LD A9D . LD @IY+~,L
LD I,A LD @IY~l,H
LD I~L,84~}l - POP DE
LD @DMAMAD,HL XOR A
LD DEjDMAA LD @IY-~2,A
LD ~PAADD,DE . LD ~IY+3~A
LD DE,50 LD @IY~4,2pH
~ET 7,D. ADD IY,DE
LD @PACNT,DE DJNZ,INITl CALL DMAP LD B,8 LD DE,DMAB LD HL,~8~1H
, '~
, - ( r~
LD DE,400H LD @D~AMSK,A
URTLP:ID A,@MODE . LD IX,SLOTB
LD @HL,A . LD HL,8402H
LD A,@COM~IAND LD @DMAMAD,HL
LD @HL,A LD DE 9 DMAB
ADD HL,DE LD @PAADD,DE
DJNZ,VRTLP LD DE,50 LD HL,MSG0 . SET 7,D
LD DE,SONM LD @PACNT,DE
LD BC,23 CALI, DMAP
LDIR LD HL,BDMAC
LD @83FEH,A SET l;@HL
JP BREAK JP SERVERX
~ =
BREAK:DI
NOP SERVERX:LD A,@HLATCH
EI LD ~CTRLATCH,A
JP BREAK LD A,20H
= CP @IXt~
= JP Z,DATA
SERRECA:LD @83FEHtA LD A,40H
LD A,~0000001B CP @IX+4 LD @D~AMSK,A 3P Z,STATASS
LD IX,SLOTA LD A,41H
LD HL,8400X CP @IX+0 LD @DMAMAD,HL JP Z,STATASS .
LD DE,DMAA JP EXIT
LD @PAADD,DE
LD DE,50 SET 7,D . DATA:LD A,@IX+2 LD @PACNT 9 DE CALL LTDATA
CALL DMAP LD HL,@TCTLADD
LD HL,BDMAC LD A,@COMMAND
SET 0,@HL RES 5,A
JP SERVERX CALL WCMD
= ` LD ~IX~42,0 SERRECB:LD @83FEH,A ~OR A
LD A,00000010B PUSH:IX
(' . s~.?
POP HL EXIT:NOP
ADD HL,DE RET
LD @MSGB~FF,HL
CALL TXBUFFER
LD HL,@TCTLADD - SERXMITA:LD A,00000100B
LD A,~CONMAND I.D @DMAMSK,A
SET 5,A LD HL,8404~
CALL WCMD LD @DM~IAD,HL
JP EXIT JP SERVETX
=
STATASS:LD HL,BDMAC SERXMITB:LD A5000O1000B
SET 3,@HL LD @DMAMSK~A
JP EXIT LD HL,8406E
= LD @DMAMAD,HL
DMAP:LD HL,@DMU~D JP GETSTAT
LD DE,@PAADD
LD @HL,E SERVETX:PUSH AF
LD @HL,D LD @83FEH,A
INC HL CPL
LD DE,~PACNT LD HL,BDMAC
LD @HL,E AND @HL
LD @HL,D LD @HL,A
RET POP AF
- LD HL,WFORT
ARMDMA:LD A,0 AND @HL
LD @8408H,A RET
LD A,@8408H LD A,@DMAMSK
CPL PUSH AF
LD HL,BDMAC AND @HL
AND @HL LD @HL,A
LD HL,DMAMSK LD HL,BD~AC
OR @HL POP AP
OR 40H OR @HL
LD @8408H,A LD @HL,A
RET CALL DMAP
= CALL A~MD~
~: }
.~ ~
RET LD HL,BPNTRl :: = LD @PNTRADD,HL
GETSTAT:LD HL,98~1H LD HL,SBVFFl `~ LD @83FEH,A DEC HL
~- LD B,8 LD @DMAST,HL
~ LD DE,STATUS~12 - JP RECC~R :~
i" GSl:LD A,~HL
LD @DE,A RECCH2:LD A,2 INC DE CALL LTDATA
PUSH BC LD HL,BPNTR2 LD BC,4~0H LD @PNTRADD,HL
ADD HL,BC LD HL,SBUFF2 : POP BC DEC HL
DJN~,GSl LD @DMAST,HL
LD HL,STATUS JP ~ECCHAR
LD @PAADD,HL
LD HL,50 RECCH3-LD A,3 SET 7,H CALL LTDATA
LD @PACNT 9 HL LD HLjBPNTR3 LD HT"BDMAC LD @PNTRADD,HL
SET 3,@HL LD HL,SBUFF3 `~
CALL DMAP DEC HL : ~;
CALL ARMDMA LD @DMAST,HL
RET . JP RECCHAR
gINITIAL USART INT. ROUTINES RECCH4:LD A,4 _ CALL L~DATA
RECCH0:LD A,0 . LD HL,BPNTR4 CALL LTDATA LD @PNTRADD,HL
LD HL,BPNTR0 LD HL,SBUFF4 LD @PNTRADD,HL DEC HL
LD HL,SBUFF0 LD @DMAST,HL
DEC HL JP RECCHAR
LD @D~ST,HL . = S
JP RECCHAR RECCH5:LD A,5 = CALL LTDATA
RECCHl:LD A,l LD HL,BPNTR5 CALL LTDATA LD @PNTRADD,HL
. -- .
LD HL,SBVFF5 LD E,@HL
D~C HL ~ INC HL
LD @DMAST,HL LD D,@HL
JP RECCHAR LD @DE,A
= PVSH AF
RECCH6:LD A,6 CALL TXCHAR
CALL LTDATA POP AF
LD HL,BPNTR6 INC DE
LD @PNTRADD,HL LD HL,@PNTRhDD
LD HL,SBUFF6 LD @HL,E
DEC HL INC HL
LD @DMAST,}IL LD @HL,D
JP RECCHAR INC HL
= PUSH AF -RECCH7:LD A,7 LD A,@HL
LD HL,BPNTR7 JP Z,SEND
LD @PNTRADD,HL INC @HL
LD HL,SBUFF7 POP AF
DEC HL PUSH AF
LD @D~ST,HL CP CR
JP RECCHAR JP Z,SEND
POP AF
= . PUSH AF
RECCH~R:LD HL,@TCTLADD CP ESC
LD A t @co~ND JP Z,ESCAPE
RES 5,A - POP AF
CALL WCMD JP TEXI~
LD HL,@TDATADD
LD A,@HL SEND:LD HL,@DMAST
RES 7,A I.D DR,12 PUSH AF ADD HL,DE
LD HL,ACTIVE PUSH HL
LD A,@TXINTENM POP DE
AND @}IL ID HL,@PNTRADD
JP Z,NEWUSER LD @HL~E
INC HL
POP AF
LD HL,@PNTRADD LD @HL,D
. -~ :3 INC HL LD IY,@PNTRADD
XOR A LD A~@IY+3 LD @HL,A CP 0 LD A,00000100B JP NZ 9 INPDA
LD @DMAMSK~A POP AF
POP AF LD IY~@DMAST
LD HL~BDMAC XOR A
BIT 2~@HL LD @IY+2~A
JP NZ~LMB LD @IY~3~A
LD HL,8404H LD A~@CTERM
LD @D~LMMAD,HL ADD 30H
LD HL,@DMAST LD @USRN,A
LD @PAADD~HL LD ~L~SOMM
LD HL~50 LD @MSGBUFF,HL
SET 6~H CALL TXBUFFER
LD @PACNT~HL LD HL~MSGl LD HLlBDMAC LD @MSGBUFF~HL
SET 2~@HL CALL TXBUFFER
CALL D~P LD IY,@PNTRADD
CALL AR~mMA LD A~@IY~3 LD HL~@PNTRADD INC A
INC HL LD @IY+3~A
INC HL JP TEXIT
XOR A INPDA:POP AF
LD @HL,A LD HL 9 @TDATADD
JP TEXIT LD @HL~A
LMB:LD HL~8404H CALL ATOBIN
LD @D~kAD~HL - PUSH AF
LD }IL~@DMAST LD HL~@DMAST
LD @PAADD~HL INC HL
LD HL,50 INC HL
SET 6~H LD IY~@PNTRADD
LD @PACNT~HL LD A~@IY+3 LD HL,WFORT CP 3 SET 2~@HL JP CY~HI
JP TEXIT INC HL
= HI:POP AF
N~WUSER:NOP OR @HL
lr;~
~ - - . - - - -~ 3L~L3 3~5~
BIT 0,@IY~3 AND 0FH
JP Z,NOSHFT ADD 9 SLA A RET
SLA A
SLA A LTDATA:AND 0FH
SLA A LD @CTERM,R
NOSHFT:LD @HL,A SLA A
INC @IY~3 XOR B
LD R,@IY+3 LD C,A
CP 5 LD HL,TDATTBL
JP NZ,TEXIT ADD HL,BC
LD HL,ACTIVE LD E,@HL
LD A,@TXINTENM . INC HL
OR @HL LD D,@HL
LD @HL,A PUSH DE
LD UL,TXINTENM POP HL
LD B,@HL LD @TDATADD,HL
LD C,~ INC HL
DEC C LD @TCTLADD,HL
XOR A SRL A
CNREP:RR B LD B,A
INC C INC B
JP NCY,CNREP LD A,1 LD ~,C ~ DLP1:RL A
LD IY,@DMAST DJNZ~DLP1 LD @IY~5,A RR A
LD A,CR LD ~TXINTENM,A
C~LL TXCHAR ~ET
LD A,LF ~ -CALL TXCHAR
JP TEYIT TXBUFFER:LD DE,@MSGBUFF
ATOBIN:PUSH AF LP3:LD A,@DE
cr 5~11 - CP 0 . JP NCY,LET JR Z,DONE
POP AF LD A,@DE
AND 0F}I CALL TXCHAR
RET CP CR
LET:POP AF JR Z,DONE
3~L5~ . f ~
INC DE LD A,@CO~AND
JR LP3 SET 5,A
DONE:RET LD HL,@TCTLADD
RET . CALL WCMD
= RET
TXCHAR:PUSH AF
LD H~,-@TCTLADD ESCAPE:XOR A
TXC1:~D A,@HL LD IY,@PNTRADD
BIT 0,A LD @IY~6,A
JR Z,TXC1 LD ~IY+5,A
POP AF LD @IY~3,A
LD HL,@TDATADD LD @IY~2,A
LD @HL,A LD HL9ACTIVE
PUSH AF LD A9@TXINTEN~
CP CR CPL
JR NZ,NOLF- AND @HL
PUSH HL ~D @HL,A
LD HL,@TCTLADD LD HL,@DMAST
TXC2:LD A,@HL LD DE,12 BIT 0,A ADD HL,DE
JR Z TXC2 LD @IY+0~L
POP HL LD @IY~1,H
LD A,LF JP NEWUSER
LD @HL,A
POP AF
RET ORG 600H,6600H
- NOLF:POP AF TDATTBL-DW 98~0H
R~T DW 9C00H
= DW 0A000H
WCMD:PUSH AF DW 0A400H
WCLP1:LD A,@HL DW 0A800H
BIT 0,A DW 0AC00H
JR Z,WCLP1 DW 0B000H
LD @HL,A DW 0B40~H
RET MSGO~DS 'GOOD DAY, USER' = RS 1 TEXIT:LD @83FEH,A DS ' , , . , ( DB CR
DB 0 ;USART RW BUFF'S
MSGl:DS 'ENTER DESTINATION(HF~):' BPNTR~:RS 2 = RS 1 RESPONSE CNT
ORG 6000H -- WORKING STORE(RA~I~ SBUFF0:RS 100 DMAMk~: RS 2 PAADD:RS 2 BPNTRl: RS 2 PACNT:RS 2 RS l TXINTENM:RS 1 -RS 1 ACTIVE:RS 1 SBUFFl:RS 100 MODE:RS 1 COM~AND . RS 1 BPNTR2ORS 2 DMAMSK:RS 1 RS 1 BDMAC:RS 1 RS 1 MSGBUFF:RS 2 . SBUFF2:BS 100 WFORT:RS 1 PNTRADD:RS 2 BPNTR3:RS 2 DMAST:RS 2 RS 1 TCTLADD: RS 2 RS
TDATADD:RS 2 SBUFF3:RS 100 HLATCH:RS 1 CTERM:R5 1 BPNTR4:RS 2 SONM:RS 15 RS 1 USRN: RS l RS 1 R S 1 SBUFF4: RS 100 = BPNTR5:RS 2 - = . RS 1 ;RECEIVE SBUFF5:RS 100 DMAA:RS 2 SioTA:RS 100 BPNTR6:RS 2 DMAB: RS 2 RS
SLOTB: RS 100 RS l = SBUFF6:RS 100 BB-TS BUFF
STATUS: RS 100 - BPNTR7:RS 2 ~33~S~
SBUFF7:RS lP0 ORG 700H,6700H PIC VECTOR TBL
VTAB~E:DW SERRECA
DN S ~ RECB
DN SERXPIIl'A
DN SERXMITB
DW RECCHl DW RECCH2 .
Dl~ RECCH7 EQUATES
SLOTSZ:EQV 100 DB:EQU 6600H
ESC:EQU 0330 LF:EQU 0120 BS:EQU 0100 CTRLATCH:EQU 8800H
END
Diis3i~~ BD I~Ti~ Bf b~AS~T ~B
EFsYhl;0~51 fASS1~ F2 fASS~'rolflEq F F S L O ~ 1 i E F F S ~ N C ~ F S Y N ~ 0 I~RP ~ INTSRV ~ _PlSYNC0~Q2 NUI,~ Ff P~O~LT~llBE ~wRC~N0iPI~
R~C;EN ~ REI::SL`I _ ~119~ _ RHU~FR01QE
~sNIJELJ1~4E~ RTP ~6~ SiLI13t)014!!i 5TASl~~r3a STA~;2Ç~ D6 ~ 53~ a0Dp S T ~ S ~ A ~ M T ~ A T U S~ ~ 9 ~
~i T D A ~ $ 0 5 ~ _ _ U N O E ~ I T
__ _ _ _ _. _ _ _ _ . _. _ _ _ _ .. . _ .. . . _ _ . _ .. __ . . _ __ _ _ _ _ _ _ _ '~ '` I
r ~ , APPENDIX II
CLUSTER CONTROLLER ASSEMBLER LISTI~G
= LD @PAADD,DE
ORG 0,6000H LD HL,8402H
LD SP,6FF~H LD @DMAMAD,HL
JP START CALL DMAP
LD A,01000pl~7 ORG 4~H,6040H LD @8400H,A
START:DI LD A3~1000001B
IM 2 LD @8408H,A
;5ET START STATE LD HL,BDMAC
LD A,llll~lllB;TEMP SET 0, ~HL
LD @HLATCH,A SET l,@HL
LD @CTRLATCH 7 A LD IY,BPNTR~
LD A,01101110B LD HL95LOTSZ
LD @MODE,A LD DE,4 LD A,00100111B ADD HL~DE
LD @COMMAND D A PUSH HL
XOR A POP DE
LD @TXINTENM,A LD B,8 LD @ACTIVE,A INITl:XOR A
LD ~BDMAC,A PUSH IY
LD @WFORT,A POP EL
~D @DMAMSK,A PUSH DE
LD @8408H,A . . LD DE,15 LD DE,VTABLE ADD RL,D~
LD A9D . LD @IY+~,L
LD I,A LD @IY~l,H
LD I~L,84~}l - POP DE
LD @DMAMAD,HL XOR A
LD DEjDMAA LD @IY-~2,A
LD ~PAADD,DE . LD ~IY+3~A
LD DE,50 LD @IY~4,2pH
~ET 7,D. ADD IY,DE
LD @PACNT,DE DJNZ,INITl CALL DMAP LD B,8 LD DE,DMAB LD HL,~8~1H
, '~
, - ( r~
LD DE,400H LD @D~AMSK,A
URTLP:ID A,@MODE . LD IX,SLOTB
LD @HL,A . LD HL,8402H
LD A,@COM~IAND LD @DMAMAD,HL
LD @HL,A LD DE 9 DMAB
ADD HL,DE LD @PAADD,DE
DJNZ,VRTLP LD DE,50 LD HL,MSG0 . SET 7,D
LD DE,SONM LD @PACNT,DE
LD BC,23 CALI, DMAP
LDIR LD HL,BDMAC
LD @83FEH,A SET l;@HL
JP BREAK JP SERVERX
~ =
BREAK:DI
NOP SERVERX:LD A,@HLATCH
EI LD ~CTRLATCH,A
JP BREAK LD A,20H
= CP @IXt~
= JP Z,DATA
SERRECA:LD @83FEHtA LD A,40H
LD A,~0000001B CP @IX+4 LD @D~AMSK,A 3P Z,STATASS
LD IX,SLOTA LD A,41H
LD HL,8400X CP @IX+0 LD @DMAMAD,HL JP Z,STATASS .
LD DE,DMAA JP EXIT
LD @PAADD,DE
LD DE,50 SET 7,D . DATA:LD A,@IX+2 LD @PACNT 9 DE CALL LTDATA
CALL DMAP LD HL,@TCTLADD
LD HL,BDMAC LD A,@COMMAND
SET 0,@HL RES 5,A
JP SERVERX CALL WCMD
= ` LD ~IX~42,0 SERRECB:LD @83FEH,A ~OR A
LD A,00000010B PUSH:IX
(' . s~.?
POP HL EXIT:NOP
ADD HL,DE RET
LD @MSGB~FF,HL
CALL TXBUFFER
LD HL,@TCTLADD - SERXMITA:LD A,00000100B
LD A,~CONMAND I.D @DMAMSK,A
SET 5,A LD HL,8404~
CALL WCMD LD @DM~IAD,HL
JP EXIT JP SERVETX
=
STATASS:LD HL,BDMAC SERXMITB:LD A5000O1000B
SET 3,@HL LD @DMAMSK~A
JP EXIT LD HL,8406E
= LD @DMAMAD,HL
DMAP:LD HL,@DMU~D JP GETSTAT
LD DE,@PAADD
LD @HL,E SERVETX:PUSH AF
LD @HL,D LD @83FEH,A
INC HL CPL
LD DE,~PACNT LD HL,BDMAC
LD @HL,E AND @HL
LD @HL,D LD @HL,A
RET POP AF
- LD HL,WFORT
ARMDMA:LD A,0 AND @HL
LD @8408H,A RET
LD A,@8408H LD A,@DMAMSK
CPL PUSH AF
LD HL,BDMAC AND @HL
AND @HL LD @HL,A
LD HL,DMAMSK LD HL,BD~AC
OR @HL POP AP
OR 40H OR @HL
LD @8408H,A LD @HL,A
RET CALL DMAP
= CALL A~MD~
~: }
.~ ~
RET LD HL,BPNTRl :: = LD @PNTRADD,HL
GETSTAT:LD HL,98~1H LD HL,SBVFFl `~ LD @83FEH,A DEC HL
~- LD B,8 LD @DMAST,HL
~ LD DE,STATUS~12 - JP RECC~R :~
i" GSl:LD A,~HL
LD @DE,A RECCH2:LD A,2 INC DE CALL LTDATA
PUSH BC LD HL,BPNTR2 LD BC,4~0H LD @PNTRADD,HL
ADD HL,BC LD HL,SBUFF2 : POP BC DEC HL
DJN~,GSl LD @DMAST,HL
LD HL,STATUS JP ~ECCHAR
LD @PAADD,HL
LD HL,50 RECCH3-LD A,3 SET 7,H CALL LTDATA
LD @PACNT 9 HL LD HLjBPNTR3 LD HT"BDMAC LD @PNTRADD,HL
SET 3,@HL LD HL,SBUFF3 `~
CALL DMAP DEC HL : ~;
CALL ARMDMA LD @DMAST,HL
RET . JP RECCHAR
gINITIAL USART INT. ROUTINES RECCH4:LD A,4 _ CALL L~DATA
RECCH0:LD A,0 . LD HL,BPNTR4 CALL LTDATA LD @PNTRADD,HL
LD HL,BPNTR0 LD HL,SBUFF4 LD @PNTRADD,HL DEC HL
LD HL,SBUFF0 LD @DMAST,HL
DEC HL JP RECCHAR
LD @D~ST,HL . = S
JP RECCHAR RECCH5:LD A,5 = CALL LTDATA
RECCHl:LD A,l LD HL,BPNTR5 CALL LTDATA LD @PNTRADD,HL
. -- .
LD HL,SBVFF5 LD E,@HL
D~C HL ~ INC HL
LD @DMAST,HL LD D,@HL
JP RECCHAR LD @DE,A
= PVSH AF
RECCH6:LD A,6 CALL TXCHAR
CALL LTDATA POP AF
LD HL,BPNTR6 INC DE
LD @PNTRADD,HL LD HL,@PNTRhDD
LD HL,SBUFF6 LD @HL,E
DEC HL INC HL
LD @DMAST,}IL LD @HL,D
JP RECCHAR INC HL
= PUSH AF -RECCH7:LD A,7 LD A,@HL
LD HL,BPNTR7 JP Z,SEND
LD @PNTRADD,HL INC @HL
LD HL,SBUFF7 POP AF
DEC HL PUSH AF
LD @D~ST,HL CP CR
JP RECCHAR JP Z,SEND
POP AF
= . PUSH AF
RECCH~R:LD HL,@TCTLADD CP ESC
LD A t @co~ND JP Z,ESCAPE
RES 5,A - POP AF
CALL WCMD JP TEXI~
LD HL,@TDATADD
LD A,@HL SEND:LD HL,@DMAST
RES 7,A I.D DR,12 PUSH AF ADD HL,DE
LD HL,ACTIVE PUSH HL
LD A,@TXINTENM POP DE
AND @}IL ID HL,@PNTRADD
JP Z,NEWUSER LD @HL~E
INC HL
POP AF
LD HL,@PNTRADD LD @HL,D
. -~ :3 INC HL LD IY,@PNTRADD
XOR A LD A~@IY+3 LD @HL,A CP 0 LD A,00000100B JP NZ 9 INPDA
LD @DMAMSK~A POP AF
POP AF LD IY~@DMAST
LD HL~BDMAC XOR A
BIT 2~@HL LD @IY+2~A
JP NZ~LMB LD @IY~3~A
LD HL,8404H LD A~@CTERM
LD @D~LMMAD,HL ADD 30H
LD HL,@DMAST LD @USRN,A
LD @PAADD~HL LD ~L~SOMM
LD HL~50 LD @MSGBUFF,HL
SET 6~H CALL TXBUFFER
LD @PACNT~HL LD HL~MSGl LD HLlBDMAC LD @MSGBUFF~HL
SET 2~@HL CALL TXBUFFER
CALL D~P LD IY,@PNTRADD
CALL AR~mMA LD A~@IY~3 LD HL~@PNTRADD INC A
INC HL LD @IY+3~A
INC HL JP TEXIT
XOR A INPDA:POP AF
LD @HL,A LD HL 9 @TDATADD
JP TEXIT LD @HL~A
LMB:LD HL~8404H CALL ATOBIN
LD @D~kAD~HL - PUSH AF
LD }IL~@DMAST LD HL~@DMAST
LD @PAADD~HL INC HL
LD HL,50 INC HL
SET 6~H LD IY~@PNTRADD
LD @PACNT~HL LD A~@IY+3 LD HL,WFORT CP 3 SET 2~@HL JP CY~HI
JP TEXIT INC HL
= HI:POP AF
N~WUSER:NOP OR @HL
lr;~
~ - - . - - - -~ 3L~L3 3~5~
BIT 0,@IY~3 AND 0FH
JP Z,NOSHFT ADD 9 SLA A RET
SLA A
SLA A LTDATA:AND 0FH
SLA A LD @CTERM,R
NOSHFT:LD @HL,A SLA A
INC @IY~3 XOR B
LD R,@IY+3 LD C,A
CP 5 LD HL,TDATTBL
JP NZ,TEXIT ADD HL,BC
LD HL,ACTIVE LD E,@HL
LD A,@TXINTENM . INC HL
OR @HL LD D,@HL
LD @HL,A PUSH DE
LD UL,TXINTENM POP HL
LD B,@HL LD @TDATADD,HL
LD C,~ INC HL
DEC C LD @TCTLADD,HL
XOR A SRL A
CNREP:RR B LD B,A
INC C INC B
JP NCY,CNREP LD A,1 LD ~,C ~ DLP1:RL A
LD IY,@DMAST DJNZ~DLP1 LD @IY~5,A RR A
LD A,CR LD ~TXINTENM,A
C~LL TXCHAR ~ET
LD A,LF ~ -CALL TXCHAR
JP TEYIT TXBUFFER:LD DE,@MSGBUFF
ATOBIN:PUSH AF LP3:LD A,@DE
cr 5~11 - CP 0 . JP NCY,LET JR Z,DONE
POP AF LD A,@DE
AND 0F}I CALL TXCHAR
RET CP CR
LET:POP AF JR Z,DONE
3~L5~ . f ~
INC DE LD A,@CO~AND
JR LP3 SET 5,A
DONE:RET LD HL,@TCTLADD
RET . CALL WCMD
= RET
TXCHAR:PUSH AF
LD H~,-@TCTLADD ESCAPE:XOR A
TXC1:~D A,@HL LD IY,@PNTRADD
BIT 0,A LD @IY~6,A
JR Z,TXC1 LD ~IY+5,A
POP AF LD @IY~3,A
LD HL,@TDATADD LD @IY~2,A
LD @HL,A LD HL9ACTIVE
PUSH AF LD A9@TXINTEN~
CP CR CPL
JR NZ,NOLF- AND @HL
PUSH HL ~D @HL,A
LD HL,@TCTLADD LD HL,@DMAST
TXC2:LD A,@HL LD DE,12 BIT 0,A ADD HL,DE
JR Z TXC2 LD @IY+0~L
POP HL LD @IY~1,H
LD A,LF JP NEWUSER
LD @HL,A
POP AF
RET ORG 600H,6600H
- NOLF:POP AF TDATTBL-DW 98~0H
R~T DW 9C00H
= DW 0A000H
WCMD:PUSH AF DW 0A400H
WCLP1:LD A,@HL DW 0A800H
BIT 0,A DW 0AC00H
JR Z,WCLP1 DW 0B000H
LD @HL,A DW 0B40~H
RET MSGO~DS 'GOOD DAY, USER' = RS 1 TEXIT:LD @83FEH,A DS ' , , . , ( DB CR
DB 0 ;USART RW BUFF'S
MSGl:DS 'ENTER DESTINATION(HF~):' BPNTR~:RS 2 = RS 1 RESPONSE CNT
ORG 6000H -- WORKING STORE(RA~I~ SBUFF0:RS 100 DMAMk~: RS 2 PAADD:RS 2 BPNTRl: RS 2 PACNT:RS 2 RS l TXINTENM:RS 1 -RS 1 ACTIVE:RS 1 SBUFFl:RS 100 MODE:RS 1 COM~AND . RS 1 BPNTR2ORS 2 DMAMSK:RS 1 RS 1 BDMAC:RS 1 RS 1 MSGBUFF:RS 2 . SBUFF2:BS 100 WFORT:RS 1 PNTRADD:RS 2 BPNTR3:RS 2 DMAST:RS 2 RS 1 TCTLADD: RS 2 RS
TDATADD:RS 2 SBUFF3:RS 100 HLATCH:RS 1 CTERM:R5 1 BPNTR4:RS 2 SONM:RS 15 RS 1 USRN: RS l RS 1 R S 1 SBUFF4: RS 100 = BPNTR5:RS 2 - = . RS 1 ;RECEIVE SBUFF5:RS 100 DMAA:RS 2 SioTA:RS 100 BPNTR6:RS 2 DMAB: RS 2 RS
SLOTB: RS 100 RS l = SBUFF6:RS 100 BB-TS BUFF
STATUS: RS 100 - BPNTR7:RS 2 ~33~S~
SBUFF7:RS lP0 ORG 700H,6700H PIC VECTOR TBL
VTAB~E:DW SERRECA
DN S ~ RECB
DN SERXPIIl'A
DN SERXMITB
DW RECCHl DW RECCH2 .
Dl~ RECCH7 EQUATES
SLOTSZ:EQV 100 DB:EQU 6600H
ESC:EQU 0330 LF:EQU 0120 BS:EQU 0100 CTRLATCH:EQU 8800H
END
Claims (46)
1. A time division multiple access communications system comprising:
a common signal path and a set of terminals coupled to said path, said set including means for establishing one or more communication links over said path between one or more of said terminals, and means for transferring digital signals between linked terminals in one or more time slots associated with said links, said time slots being in a repetitive framed sequence, each of said terminals having an associated address and including means to identify and receive correspondingly addressed digital signals on said path, wherein at least one terminal further includes means for transmitting an addressed primary slot allocation signal on said signal path in at least one of said time slots, said primary slot allocation signal being addressed to one or more other terminals and including data representative of the identity of an allocated one or more of said time slots in which said other terminals may transmit addressed signals on said path.
a common signal path and a set of terminals coupled to said path, said set including means for establishing one or more communication links over said path between one or more of said terminals, and means for transferring digital signals between linked terminals in one or more time slots associated with said links, said time slots being in a repetitive framed sequence, each of said terminals having an associated address and including means to identify and receive correspondingly addressed digital signals on said path, wherein at least one terminal further includes means for transmitting an addressed primary slot allocation signal on said signal path in at least one of said time slots, said primary slot allocation signal being addressed to one or more other terminals and including data representative of the identity of an allocated one or more of said time slots in which said other terminals may transmit addressed signals on said path.
2. A system according to claim 1 wherein said one terminal includes means to command one or more of said other terminals to transmit an addressed signal over said path in one of said allocated time slots.
3. A system according to claim 1 wherein at least one of said other terminals further includes means for transmitting an addressed secondary slot allocation signal on said signal path in at least one of said allocated time slots, said secondary slot allocation signal being addressed to one or more of said
3. A system according to claim 1 wherein at least one of said other terminals further includes means for transmitting an addressed secondary slot allocation signal on said signal path in at least one of said allocated time slots, said secondary slot allocation signal being addressed to one or more of said
Claim 3 continued remaining other terminals and including data representative of the identity of one or more of said allocated time slots in which said remaining other terminals may transmit addressed signals on said path.
4. A system according to claim 3 wherein said one terminal includes means to command one or more of said other terminals to transmit an addressed signal over said path in one of said allocated time slots.
5. A system according to claim 4 wherein said one other terminal includes means to command one or more of said remaining other terminals to transmit an addressed signal over said path in one of said allocated time slots.
6. A system according to claim 1 wherein said one terminal includes means for allocating predetermined numbers of time slots to selected ones of said other terminals during each of said framed sequences, said predetermined number of slots being for transmission of digital sign-on request signals by the respective ones of said selected terminals to direct said one terminal to link the requesting terminal to said signal path, said predetermined number of slots for providing said one terminal to be responsive to said sign-on request signals of the respective ones of said selected terminals during a predetermined proportion of each of said framed sequences, whereby said allocation or said predetermined number of time slots provides the respective ones of said selected terminals with a predetermined mean time for access to said signal path.
7. A system according to claim 1 wherein said other terminals include:
a service request means for transmitting a digital sign-on request signal on said path to request a communication link, said link having a requested rate, and wherein said one terminal includes:
means for receiving from requesting terminals said transmitted sign-on request signals, and for allocating to the respective ones of said requesting terminals a selected number of time slots during each of said framed sequences to form a communication link between the ones of said requesting terminals and other terminals connected to said path, said selected number of slots for the respective ones of said requesting remote terminals being determined in response to said requested data rate, whereby the information capacity of said signal path is allocated to the respective ones of said requesting remote terminals in accordance with the various sign-on request signals.
8. A time division multiple access digital communications system as defined in claim 1 wherein each of said terminals include:
means for identifying a subset of time slots from a set having 2n sequentially numbered time slots in a repetitive framed time sequence, where n is an integer, said subset of slots being uniquely defined by a reference slot number, fsn, which is representative of a numbered member of said subset in said framed sequence, and a slot spacing number, m, where m is an integer less than or equal to n and is representative of the spacing between members of said subset in said framed sequence, said spacing being equal to 2m slots, said identifying means comprising:
a service request means for transmitting a digital sign-on request signal on said path to request a communication link, said link having a requested rate, and wherein said one terminal includes:
means for receiving from requesting terminals said transmitted sign-on request signals, and for allocating to the respective ones of said requesting terminals a selected number of time slots during each of said framed sequences to form a communication link between the ones of said requesting terminals and other terminals connected to said path, said selected number of slots for the respective ones of said requesting remote terminals being determined in response to said requested data rate, whereby the information capacity of said signal path is allocated to the respective ones of said requesting remote terminals in accordance with the various sign-on request signals.
8. A time division multiple access digital communications system as defined in claim 1 wherein each of said terminals include:
means for identifying a subset of time slots from a set having 2n sequentially numbered time slots in a repetitive framed time sequence, where n is an integer, said subset of slots being uniquely defined by a reference slot number, fsn, which is representative of a numbered member of said subset in said framed sequence, and a slot spacing number, m, where m is an integer less than or equal to n and is representative of the spacing between members of said subset in said framed sequence, said spacing being equal to 2m slots, said identifying means comprising:
Claim 8 continued a. means for generating a binary coded digital fsn signal representative of said reference slot number, fsn, b. a reference means for identifying the various ones of said set of 2n sequentially numbered time slots in a repetitive framed time sequence, and for generating said sequential binary coded reference signal associated with each of the successively identified time slots, c. for comparing the m least significant bits of said successively generated reference signals with the m least significant bits of said digital fsn signal representative of said reference slot number, fsn, d. means for generating a control signal when said m least significant bits of said compared signals exactly match, and for generating no such control signal otherwise, said control signal being coincident with and identifying the members of said subset of time slots.
9. A system according to claim 3 wherein said one other terminal includes means for allocating predetermined numbers of time slots to selected ones of said other remaining terminals during each of said framed sequences, said predetermined number of slots being for transmission of digital sign on request signals by the respective ones of said selected terminals to direct said one other terminal to link the requesting terminal to said signal path, said predetermined number of slots for providing said one other terminal to be responsive to said sign on request signals of the respective ones of said selected terminals during a predetermined proportion of each of said framed sequences, whereby said allocation of said predetermined number of
9. A system according to claim 3 wherein said one other terminal includes means for allocating predetermined numbers of time slots to selected ones of said other remaining terminals during each of said framed sequences, said predetermined number of slots being for transmission of digital sign on request signals by the respective ones of said selected terminals to direct said one other terminal to link the requesting terminal to said signal path, said predetermined number of slots for providing said one other terminal to be responsive to said sign on request signals of the respective ones of said selected terminals during a predetermined proportion of each of said framed sequences, whereby said allocation of said predetermined number of
Claim 9 continued time slots provides the respective ones of said selected terminals with a predetermined mean time for access to said signal path.
10. A system according to claim 3 wherein said remaining other terminals include:
a service request means for transmitting a digital sign-on request signal on said path to request a communication link, said link having a requested data rate, and wherein said one other terminal includes:
means for receiving from requesting terminals said transmitted sign-on request signals, and for allocating to the respective ones of said requesting terminals a selected number of time slots during each of said framed sequences to form a commun-ication link between the ones of said requesting terminals and other terminals connected to said path, said selected number of slots for the respective ones of said requesting remote terminals being determined in response to said requested data rate, whereby the information capacity of said signal path is allocated to the respective ones of said requesting remote terminals in accordance with the various sign-on request signals.
11. A time division multiple access communications system, comprising:
a. a digital bus including a pair of oppositely-directed unidirectional digital signal paths interconnecting a common location with one or more remote locations, b. a connector network at said common location and adapted to receive digital signals in one or more uniform time slots associated with the inbound path, said time slots being in
a service request means for transmitting a digital sign-on request signal on said path to request a communication link, said link having a requested data rate, and wherein said one other terminal includes:
means for receiving from requesting terminals said transmitted sign-on request signals, and for allocating to the respective ones of said requesting terminals a selected number of time slots during each of said framed sequences to form a commun-ication link between the ones of said requesting terminals and other terminals connected to said path, said selected number of slots for the respective ones of said requesting remote terminals being determined in response to said requested data rate, whereby the information capacity of said signal path is allocated to the respective ones of said requesting remote terminals in accordance with the various sign-on request signals.
11. A time division multiple access communications system, comprising:
a. a digital bus including a pair of oppositely-directed unidirectional digital signal paths interconnecting a common location with one or more remote locations, b. a connector network at said common location and adapted to receive digital signals in one or more uniform time slots associated with the inbound path, said time slots being in
Claim 11 continued:
a repetitive framed sequence, and further adapted to transmit corresponding digital signals in one or more corresponding time slots associated with the outbound path, c. a plurality of terminals, each terminal being coupled to the inbound and outbound paths at one of said remote locations, and having an associated address and wherein each terminal includes means to identify and receive correspondingly addressed digital signals in contention ones of time slots on said outbound path, and wherein each terminal of a first set of said terminals includes contention transmission means for transmitting addressed digital signals in contention time slots on said inbound path, and d. signal collision detection means including at each first set terminal:
i. monitoring means operative following trans-mission of a message signal by said terminal in a contention time slot to monitor the corresponding contention time slot on said outbound path to detect the presence of a signal corresponding only to said transmitted message signal, ii. re-transmission means responsive to said monitoring means to re-transmit said message signal in a sub-sequent contention time slot only when said monitoring means fails to detect the presence of said corresponding message signal in said corresponding contention slot.
12. A system according to claim 11 wherein said signal collision detection means further includes at said connector network means to identify collision-free contention time slots on said inbound path, said collision-free time slots being
a repetitive framed sequence, and further adapted to transmit corresponding digital signals in one or more corresponding time slots associated with the outbound path, c. a plurality of terminals, each terminal being coupled to the inbound and outbound paths at one of said remote locations, and having an associated address and wherein each terminal includes means to identify and receive correspondingly addressed digital signals in contention ones of time slots on said outbound path, and wherein each terminal of a first set of said terminals includes contention transmission means for transmitting addressed digital signals in contention time slots on said inbound path, and d. signal collision detection means including at each first set terminal:
i. monitoring means operative following trans-mission of a message signal by said terminal in a contention time slot to monitor the corresponding contention time slot on said outbound path to detect the presence of a signal corresponding only to said transmitted message signal, ii. re-transmission means responsive to said monitoring means to re-transmit said message signal in a sub-sequent contention time slot only when said monitoring means fails to detect the presence of said corresponding message signal in said corresponding contention slot.
12. A system according to claim 11 wherein said signal collision detection means further includes at said connector network means to identify collision-free contention time slots on said inbound path, said collision-free time slots being
Claim 12 continued:
characterized by the presence of a digital signal from only one first set terminal therein, and means to identify collision time slots on said inbound path, said collision time slots being characterized by the presence of a digital signal from two or more first set terminals therein.
characterized by the presence of a digital signal from only one first set terminal therein, and means to identify collision time slots on said inbound path, said collision time slots being characterized by the presence of a digital signal from two or more first set terminals therein.
13. A system according to claim 12 wherein said signal collision detection means further includes means to transmit corresponding digital signals on said outbound path only in response to said collision-free time slot identification.
14. A system according to claim 12 wherein said re-trans-mission means is operative to select said subsequent contention time slot to be separated from the original transmission time slot by a random number of time slots.
15. A system according to claim 12 wherein said signal collision detection means includes at said connector network:
means to periodically generate and transmit re-transmit message signals on said outbound path, said re-transmit message signals being addressed to respective ones of said first set terminals, and being representative of a selected re-transmission delay for the respective first set terminals, said re-transmission delay being a multiple of the slot period, and wherein said re-transmission means at said respective first set terminals are responsive to the respective ones of said addressed re-transmit message signals to select said subsequent contention time slots for re-transmission of said message signal, said selected contention time slots being separated from the original transmission time slots by said selected re-transmission delay.
means to periodically generate and transmit re-transmit message signals on said outbound path, said re-transmit message signals being addressed to respective ones of said first set terminals, and being representative of a selected re-transmission delay for the respective first set terminals, said re-transmission delay being a multiple of the slot period, and wherein said re-transmission means at said respective first set terminals are responsive to the respective ones of said addressed re-transmit message signals to select said subsequent contention time slots for re-transmission of said message signal, said selected contention time slots being separated from the original transmission time slots by said selected re-transmission delay.
16. A system according to claim 15 wherein said re-transmit message signal generation means is responsive to said collision time slot identifying means to adaptively vary said re-transmit message signal for the respective ones of said first said termi-nals as a function of the rate of identified collision time slots for said respective terminals.
17. A system according to claim 16 wherein said re-transmit message signal is representative of a mean of a set of random numbers and wherein said selected re-transmission delay is pro-portional to a member of said set of random numbers.
18. A system according to claim 11 wherein said re-trans-mission means is operative to select said subsequent contention time slot to be separated from the original transmission time slot by a random number of time slots.
19. A system according to claim 11 wherein said signal collision detection means includes at said connector network:
means to periodically generate and transmit re-transmit message signals on said outbound path, said re-transmit message signals being addressed to respective ones of said first set terminals, and being representative of a selected re-transmission delay for the respective first set terminals, said selected re-transmission delay being a multiple of the slot period, and wherein said re-transmission means at said respective first set terminals are responsive to the respective ones of said re-transmit message signals to select said subsequent contention time slots for re-transmission of said message signal, said selected contention time slots being separated from the original transmission time slots by said selected re-transmission delay.
means to periodically generate and transmit re-transmit message signals on said outbound path, said re-transmit message signals being addressed to respective ones of said first set terminals, and being representative of a selected re-transmission delay for the respective first set terminals, said selected re-transmission delay being a multiple of the slot period, and wherein said re-transmission means at said respective first set terminals are responsive to the respective ones of said re-transmit message signals to select said subsequent contention time slots for re-transmission of said message signal, said selected contention time slots being separated from the original transmission time slots by said selected re-transmission delay.
20. A system according to claim 19 wherein said re-transmit message signal is representative of a mean of a set of random numbers and wherein said selected re-transmission delay is proportional to a member of said set of random numbers.
21. A system according to claim 11 wherein said repetitive framed sequence includes contention time slots and allocation time slots, wherein a second set of said terminals include means for establishing one or more communication links over said bus between one or more of said second set terminals, and means for transferring digital signals between linked second set terminals by way of inbound and outbound paths and said connector network in one or more allocation time slots associated with said link, and wherein at least one second set terminal further includes allocation transmission means for transmitting an addressed primary slot allocation signal on said inbound path in at least one of said allocation time slots, said primary slot allocation signal briny addressed to one or more other second set terminals and including data representative of the identity of an allocated one or more of said allocation time slots in which said other second set terminals may transmit addressed signals on said inbound path.
22. A system according to calim 21 wherein the sum of the number of said contention time slots and the number of said allocation time slots is a predetermined constant.
23. A system according to claim 21 further comprising means to dynamically control the number of said contention time slots and the number of said allocation time slots.
24. A system according to claim 23 wherein said dynamic control means includes means to monitor collisions in contention time slots and to transmit adjustment signals in response to changes in the ratio of said collision, and wherein each terminal includes means responsive to said adjustment signals to redefine said contention and alloca-tion time slots in accordance therewith.
25. A system according to claim 23 wherein said dynamic control means includes means to monitor the utilization of said allocation time slots and to transmit adjustment signals in response to changes in said utilization, and wherein each terminal includes means responsive to said adjustment signals to redefine said contention and alloca-tion time slots in accordance therewith.
26. A system according to claim 21 further comprising means to dynamically control the number of said terminals in said first and second sets.
27. A system according to claim 26 wherein said dynamic control means includes means to monitor collisions in contention time slots and to transmit adjustment signals in response to changes in the rate of said collisions, and wherein each terminal includes means responsive to said adjustment signals to redefine said terminal as a first or second set terminal in accordance therewith.
28. A system according to claim 26 wherein said dynamic control means includes means to monitor the utilization of said allocation time slots and to transmit adjustment signals in response to changes in said utilization, and
28. A system according to claim 26 wherein said dynamic control means includes means to monitor the utilization of said allocation time slots and to transmit adjustment signals in response to changes in said utilization, and
Claim 28 continued:
wherein each terminal includes means responsive to said adjustment signals to redefine said terminal as a first or second terminal in accordance therewith.
wherein each terminal includes means responsive to said adjustment signals to redefine said terminal as a first or second terminal in accordance therewith.
29. A system according to claim 21 wherein said one terminal includes means to command one or more of said other terminals to transmit an addressed signal over said path in one of said allocated time slots.
30. A system according to claim 21 wherein at least one of said other terminals further includes means for transmitting an addressed secondary slot allocation signal on said signal path in at least one of said allocated time slots, said secondary slot allocation signal being addressed to one or more of said remaining other terminals and including data representative of the identity of one or more of said allocated time slots in which said remaining other terminals may transmit addressed signals on said path.
31. A system according to claim 30 wherein said one terminal includes means to command one or more of said other terminals to transmit an addressed signal over said path in one of said allocated time slots.
32. A system according to claim 31 wherein said one other terminal includes means to command one or more of said remaining other terminals to transmit an addressed signal over said path in one of said allocated time slots.
33. A system according to claim 21 wherein said one terminal includes means for allocating predetermined numbers of time slots to selected ones of said other terminals during each of
33. A system according to claim 21 wherein said one terminal includes means for allocating predetermined numbers of time slots to selected ones of said other terminals during each of
Claim 33 continued:
said framed sequences, said predetermined number of slots being for transmission of digital sign-on request signals by the respective ones of said selected terminals to direct said one terminal to link the requesting terminal to said signal path, said predetermined number of slots for providing said one terminal to be responsive to said sign-on request signals of the respective ones of said selected terminals during a pre-determined proportion of each of said framed sequences, whereby said allocation of said predetermined number of time slots provides the respective ones of said selected terminals with a predetermined mean time for access to said signal path.
said framed sequences, said predetermined number of slots being for transmission of digital sign-on request signals by the respective ones of said selected terminals to direct said one terminal to link the requesting terminal to said signal path, said predetermined number of slots for providing said one terminal to be responsive to said sign-on request signals of the respective ones of said selected terminals during a pre-determined proportion of each of said framed sequences, whereby said allocation of said predetermined number of time slots provides the respective ones of said selected terminals with a predetermined mean time for access to said signal path.
34. A system according to claim 21 wherein said other terminals include:
a service request means for transmitting a digital sign-on request signal on said path to request a communication link, said link having a requested rate, and wherein said one terminal includes:
means for receiving from requesting terminals said transmitted sign-on request signals, and for allocating to the respective ones of said requesting terminals a selected number of time slots during each of said framed sequences to form a communication link between the ones of said requesting terminals and other terminals connected to said path, said selected number of slots for the respective ones of said requesting remote terminals being determined in response to said requested data rate, whereby the information capacity of said signal path is allocated to the respective ones of said requesting remote terminals in accordance with the various sign-on request signals.
a service request means for transmitting a digital sign-on request signal on said path to request a communication link, said link having a requested rate, and wherein said one terminal includes:
means for receiving from requesting terminals said transmitted sign-on request signals, and for allocating to the respective ones of said requesting terminals a selected number of time slots during each of said framed sequences to form a communication link between the ones of said requesting terminals and other terminals connected to said path, said selected number of slots for the respective ones of said requesting remote terminals being determined in response to said requested data rate, whereby the information capacity of said signal path is allocated to the respective ones of said requesting remote terminals in accordance with the various sign-on request signals.
35. A time division multiple access digital communications system as defined in claim 21 wherein each of said terminals include:
means for identifying a subset of time slots from a set having 2n sequentially numbered time slots in a repetitive framed time sequence, where n is an integer, said subset of slots being uniquely defined by a reference slot number, fsn, which is representative of a numbered member of said subset in said framed sequence, and a slot spacing number, m, where m is an integer less than or equal to n and is representative of the spacing between members of said subset in said framed sequence, said spacing being equal to 2m slots, said identifying means comprising:
a. means for generating a binary coded digital fsn signal representative of said reference slot number, fsn, b. a reference means for identifying the various ones of said set of 2n sequentially numbered time slots in a repetitive framed time sequence, and for generating said sequential binary coded reference signal associated with each of the successively identified time slots, c. for comparing the m least significant bits of said successively generated reference signals with the m least significant bits of said digital fsn signal representative of said reference slot number, fsn, d. means for generating a control signal when said m least significant bits of said compared signals exactly match, and for generating no such control signal otherwise, said control signal being coincident with and identifying the members of said subset of time slots.
means for identifying a subset of time slots from a set having 2n sequentially numbered time slots in a repetitive framed time sequence, where n is an integer, said subset of slots being uniquely defined by a reference slot number, fsn, which is representative of a numbered member of said subset in said framed sequence, and a slot spacing number, m, where m is an integer less than or equal to n and is representative of the spacing between members of said subset in said framed sequence, said spacing being equal to 2m slots, said identifying means comprising:
a. means for generating a binary coded digital fsn signal representative of said reference slot number, fsn, b. a reference means for identifying the various ones of said set of 2n sequentially numbered time slots in a repetitive framed time sequence, and for generating said sequential binary coded reference signal associated with each of the successively identified time slots, c. for comparing the m least significant bits of said successively generated reference signals with the m least significant bits of said digital fsn signal representative of said reference slot number, fsn, d. means for generating a control signal when said m least significant bits of said compared signals exactly match, and for generating no such control signal otherwise, said control signal being coincident with and identifying the members of said subset of time slots.
36. A system according to claim 30 wherein said one other terminal includes means for allocating predetermined numbers of time slots to selected ones of said other remaining terminals during each of said framed sequences, said predetermined number of slots being for transmission of digital sign-on request signals by the respective ones of said selected terminals to direct said one other terminal to link the requesting terminal to said signal path, said predetermined number of slots for providing said one other terminal to be responsive to said sign-on request signals of the respective ones of said selected terminals during a predetermined proportion of each of said framed sequences, whereby said allocation of said predetermined number of time slots provides the respective ones of said selected terminals with a predetermined mean time for access to said signal path.
37. A system according to claim 30 wherein said remaining other terminals include:
a service request means for transmitting a digital sign-on request signal on said path to request a communication link, said link having a requested data rate, and wherein said one other terminal includes:
means for receiving from requesting terminals said transmitted sign-on request signals, and for allocating to the respective ones of said requesting terminals a selected number of time slots during each of said framed sequences to form a communication link between the ones of said requesting terminals and other terminals connected to said path, said selected number of slots for the respective ones of said requesting remote terminals being determined in response to said requested
37. A system according to claim 30 wherein said remaining other terminals include:
a service request means for transmitting a digital sign-on request signal on said path to request a communication link, said link having a requested data rate, and wherein said one other terminal includes:
means for receiving from requesting terminals said transmitted sign-on request signals, and for allocating to the respective ones of said requesting terminals a selected number of time slots during each of said framed sequences to form a communication link between the ones of said requesting terminals and other terminals connected to said path, said selected number of slots for the respective ones of said requesting remote terminals being determined in response to said requested
Claim 37 continued:
data rate, whereby the information capacity of said signal path is allocated to the respective ones of said requesting remote terminals in accordance with the various sign-on request signals.
data rate, whereby the information capacity of said signal path is allocated to the respective ones of said requesting remote terminals in accordance with the various sign-on request signals.
38. A system according to claim 21 wherein said signal collision detection means further includes at said connector network means to identify collision-free contention time slots on said inbound path, said collision-free lime slots being characterized by the presence of a digital signal from only one first set terminal therein, and means to identify collision time slots on said inbound path, said collision time slots being characterized by the presence of a digital signal from two or more first set terminals therein.
39. A system according to claim 38 wherein said signal collision detection means further includes means to transmit corresponding digital signals on said outbound path only in response to said collision-free lime slot identification.
40. A system according to claim 38 wherein said re-trans-mission means is operative to select said subsequent contention time slot to be separated from the original transmission time slot by a random number of time slots.
41. A system according to claim 38 wherein said signal collision detection means includes at said connector network:
means to periodically generate and transmit re-transmit message signals on said outbound path, said re-transmit message signals being addressed to respective ones of said first set terminals, and being representative of a selected re-transmission
41. A system according to claim 38 wherein said signal collision detection means includes at said connector network:
means to periodically generate and transmit re-transmit message signals on said outbound path, said re-transmit message signals being addressed to respective ones of said first set terminals, and being representative of a selected re-transmission
Claim 41 continued:
delay for the respective first set terminals, said re-transmission delay being a multiple of the slot period, and wherein said re-transmission means at said respective first set terminals are responsive to the respective ones of said addressed re-transmit message signals to select said subsequent contention time slots for re-transmission of said message signal, said selected contention time slots being separated from the original transmission time slots by said selected re-transmission delay.
delay for the respective first set terminals, said re-transmission delay being a multiple of the slot period, and wherein said re-transmission means at said respective first set terminals are responsive to the respective ones of said addressed re-transmit message signals to select said subsequent contention time slots for re-transmission of said message signal, said selected contention time slots being separated from the original transmission time slots by said selected re-transmission delay.
42. A system according to claim 41 wherein said re-transmit message signal generation means is responsive to said collision time slot identifying means to adaptively vary said re-transmit message signal for the respective ones of said first said terminals as a function of the rate of identified collision time slots for said respective terminals.
43. A system according to claim 42 wherein said re-transmit message signal is representative of a mean of a set of random numbers and wherein said selected re-transmission delay is proportional to a member of said set of random numbers.
44. A system according to claim 21 wherein said re-trans-mission means is operative to select said subsequent contention time slot to be separated from the original transmission time slot by a random number of time slots.
45. A system according to claim 21 wherein said signal collision detection means includes at said connector network:
means to periodically generate and transmit re-transmit message signals on said outbound path, said re-transmit message
45. A system according to claim 21 wherein said signal collision detection means includes at said connector network:
means to periodically generate and transmit re-transmit message signals on said outbound path, said re-transmit message
Claim 45 continued:
signals being addressed to respective ones of said first set terminals, and being representative of a selected re-transmission delay for the respective first set terminals, said selected re-transmission delay being a multiple of the slot period, and wherein said re-transmission means at said respective first set terminals are responsive to the respective ones of said re-transmit message signals to select said subsequent contention time slots for re-transmission of said message signal, said selected contention time slots being separated from the original transmission time slots by said selected re-trans-mission delay.
signals being addressed to respective ones of said first set terminals, and being representative of a selected re-transmission delay for the respective first set terminals, said selected re-transmission delay being a multiple of the slot period, and wherein said re-transmission means at said respective first set terminals are responsive to the respective ones of said re-transmit message signals to select said subsequent contention time slots for re-transmission of said message signal, said selected contention time slots being separated from the original transmission time slots by said selected re-trans-mission delay.
46. A system according to claim 45 wherein said re-transmit message signal is representative of a mean of a set of random numbers and wherein said selected re-transmission delay is proportional to a member of said set of random numbers.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/881,704 US4161786A (en) | 1978-02-27 | 1978-02-27 | Digital bus communications system |
| US881,704 | 1978-02-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1133154A true CA1133154A (en) | 1982-10-05 |
Family
ID=25379020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA322,336A Expired CA1133154A (en) | 1978-02-27 | 1979-02-26 | Digital bus communications system |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4161786A (en) |
| EP (1) | EP0003849A3 (en) |
| JP (1) | JPS5530291A (en) |
| CA (1) | CA1133154A (en) |
Families Citing this family (109)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2406916A1 (en) * | 1977-10-18 | 1979-05-18 | Ibm France | DECENTRALIZED DATA TRANSMISSION SYSTEM |
| DE2917675A1 (en) * | 1979-04-27 | 1980-11-06 | Hertz Inst Heinrich | DIGITAL TIME MULTIPLEX MESSAGE SYSTEM |
| US4271507A (en) * | 1979-06-07 | 1981-06-02 | Ford Motor Company | Communication broadcast channel interface |
| US4234952A (en) * | 1979-06-07 | 1980-11-18 | Ford Motor Company | Conflict resolution by retransmission delay on shared communication medium |
| US4514728A (en) * | 1980-02-25 | 1985-04-30 | At&T Bell Laboratories | Store group bus allocation system |
| US4340961A (en) * | 1980-03-06 | 1982-07-20 | Atomic Energy Of Canada Limited | Distributed multi-port communications system |
| US4379294A (en) * | 1981-02-12 | 1983-04-05 | Electric Power Research Institute, Inc. | Data highway access control system |
| US4491946A (en) * | 1981-03-09 | 1985-01-01 | Gould Inc. | Multi-station token pass communication system |
| JPS57154956A (en) * | 1981-03-19 | 1982-09-24 | Fuji Xerox Co Ltd | Transmitting system of digital signal |
| WO1982003931A1 (en) * | 1981-04-27 | 1982-11-11 | Kris Bryan | Multi-master processor bus |
| US4415896A (en) * | 1981-06-09 | 1983-11-15 | Adec, Inc. | Computer controlled energy monitoring system |
| US4608560A (en) * | 1981-06-09 | 1986-08-26 | Adec, Inc. | Computer controlled energy monitoring system |
| US4484328A (en) * | 1981-08-03 | 1984-11-20 | Schlafly Hubert J | Television line multiplexed data communication system |
| US4456956A (en) * | 1981-08-24 | 1984-06-26 | Data General Corp. | Method and apparatus for controlling access of a network transmission bus between a plurality of spaced apart computer stations |
| US4439763A (en) * | 1981-09-03 | 1984-03-27 | Bell Telephone Laboratories, Incorporated | Collision avoiding system and protocol for a multiple access digital communications system |
| US4481572A (en) * | 1981-10-13 | 1984-11-06 | Teledyne Industries, Inc. | Multiconfigural computers utilizing a time-shared bus |
| JPS5875350A (en) * | 1981-10-30 | 1983-05-07 | Fuji Xerox Co Ltd | Transmitting system of digital signal |
| US4531238A (en) * | 1981-12-03 | 1985-07-23 | Xerox Corporation | Statistical contention control for star configured communication networks |
| US4472712A (en) * | 1982-03-05 | 1984-09-18 | At&T Bell Laboratories | Multipoint data communication system with local arbitration |
| US4464658A (en) * | 1982-03-05 | 1984-08-07 | At&T Laboratories | Multipoint data communication system with collision detection |
| US4630256A (en) * | 1982-03-12 | 1986-12-16 | At&T Bell Laboratories | Bidirectional dual network |
| GB2117939A (en) * | 1982-03-29 | 1983-10-19 | Ncr Co | Data communication network and method of communication |
| JPS58201494A (en) * | 1982-05-20 | 1983-11-24 | Sharp Corp | Emergency accessing system in centralized supervisory system |
| US4574378A (en) * | 1982-06-14 | 1986-03-04 | Nec Corporation | Multiple access system and method |
| EP0096097B1 (en) * | 1982-06-15 | 1985-12-27 | International Business Machines Corporation | Method and apparatus for controlling access to a communication network |
| US4532626A (en) * | 1982-07-19 | 1985-07-30 | At&T Bell Laboratories | Collision avoiding system and protocol for a two path multiple access digital communications system |
| JPS5925536A (en) * | 1982-07-30 | 1984-02-09 | シャープ株式会社 | Power line data transmission system |
| FR2531297A1 (en) * | 1982-07-30 | 1984-02-03 | Telic Alcatel Telephonie Indle | Method of autoallocation of broad band digital data transmission channel for a network for time switching of autodirector words, with bus links. |
| US4500989A (en) * | 1982-08-02 | 1985-02-19 | Dahod Ashraf M | Digital communication system |
| US4744024A (en) * | 1982-08-27 | 1988-05-10 | Burroughs Corporation | Method of operating a bus in a data processing system via a repetitive three stage signal sequence |
| US4493074A (en) * | 1982-11-03 | 1985-01-08 | The Bendix Corporation | Content induced transaction overlap communication system |
| JPS59101943A (en) * | 1982-12-03 | 1984-06-12 | Fuji Xerox Co Ltd | Digital signal transmitting system |
| CA1219091A (en) * | 1983-01-10 | 1987-03-10 | Ulrich Killat | Method of and arrangement for controlling access to a time-division multiplex message transmission path |
| JPS59127133A (en) * | 1983-01-11 | 1984-07-21 | Minolta Camera Co Ltd | Data transmitting system |
| US4528661A (en) * | 1983-02-14 | 1985-07-09 | Prime Computer, Inc. | Ring communications system |
| EP0121410B1 (en) * | 1983-03-31 | 1987-06-10 | Kabushiki Kaisha Toshiba | Bus-configured local area network with data exchange capability |
| US4530092A (en) * | 1983-03-31 | 1985-07-16 | At&T Bell Laboratories | Distributed switching system having multiple time slot interchanger nodes |
| US4510599A (en) * | 1983-04-04 | 1985-04-09 | General Electric Company | Prioritized unidirectional distributed bus accessing system |
| US4511969A (en) * | 1983-05-20 | 1985-04-16 | At&T Information Systems Inc. | Control channel interface circuit |
| US4581735A (en) * | 1983-05-31 | 1986-04-08 | At&T Bell Laboratories | Local area network packet protocol for combined voice and data transmission |
| US4517670A (en) * | 1983-06-15 | 1985-05-14 | General Electric Company | Preemptive bid communication system |
| US4603418A (en) * | 1983-07-07 | 1986-07-29 | Motorola, Inc. | Multiple access data communications controller for a time-division multiplex bus |
| US4630263A (en) * | 1983-07-07 | 1986-12-16 | Motorola, Inc. | Time-division multiplex communications control system |
| US4554658A (en) * | 1983-07-07 | 1985-11-19 | Motorola, Inc. | System for producing encoded and decoded voice, internal audio tones, and data communication within a time division multiplex network |
| US4633462A (en) * | 1983-07-18 | 1986-12-30 | The Board Of Trustees Of The University Of Illinois | Multiple access communication on a CATV reverse channel |
| JPH0630485B2 (en) * | 1983-08-16 | 1994-04-20 | 日本電気株式会社 | Time division bidirectional transmission method |
| US4626843A (en) * | 1983-09-27 | 1986-12-02 | Trw Inc. | Multi-master communication bus system with parallel bus request arbitration |
| FR2554294B1 (en) * | 1983-10-28 | 1990-03-16 | Dassault Electronique | DEVICE FOR THE EXCHANGE OF DIGITAL INFORMATION BETWEEN SEVERAL STATIONS |
| US4550402A (en) * | 1983-12-22 | 1985-10-29 | Ford Motor Company | Data communication system |
| US4542502A (en) * | 1983-12-30 | 1985-09-17 | At&T Bell Laboratories | Reconfigurable collision avoiding system, station and protocol for a two path multiple access digital communications system |
| US4560984A (en) * | 1984-02-15 | 1985-12-24 | Codenoll Technology Corporation | Method and apparatus for detecting the collision of data packets |
| US4627050A (en) * | 1984-05-22 | 1986-12-02 | Rolm Corporation | Time division multiplexed computerized branch exchange |
| CA1246677A (en) * | 1984-07-25 | 1988-12-13 | Akihiro Okada | Optical communication system |
| US4638311A (en) * | 1984-11-13 | 1987-01-20 | Itt Corporation | Apparatus for providing masterless collision detection |
| ATE82097T1 (en) * | 1984-12-03 | 1992-11-15 | Univ Western Australia | LOG FOR QUEUE. |
| DE3675819D1 (en) * | 1985-06-05 | 1991-01-10 | Nec Corp | TIME MULTIPLEXING SYSTEM WITH PRIORITY SELECTOR RESPECTING TO REQUIREMENTS OF SENDING REQUESTS. |
| US4715031A (en) * | 1985-09-23 | 1987-12-22 | Ford Motor Company | Vehicular data transfer communication system |
| GB2182227A (en) * | 1985-10-25 | 1987-05-07 | Int Standard Electric Corp | Multi-drop digital subscriber loop |
| US4751701A (en) * | 1985-11-14 | 1988-06-14 | Hughes Network Systems, Inc. | TDM collision detector |
| US4858112A (en) * | 1985-12-17 | 1989-08-15 | General Electric Company | Interface comprising message and protocol processors for interfacing digital data with a bus network |
| DE3604966C1 (en) * | 1986-02-17 | 1987-04-09 | Nixdorf Computer Ag | Circuit arrangement for switching binary signals, in particular PCM signals |
| US5062035A (en) * | 1986-06-24 | 1991-10-29 | Kabushiki Kaisha Toshiba | Time slot allocation for loop networks |
| US4750171A (en) * | 1986-07-11 | 1988-06-07 | Tadiran Electronics Industries Ltd. | Data switching system and method |
| US4754452A (en) * | 1986-09-11 | 1988-06-28 | American Telephone And Telegraph Company, At&T Bell Laboratories | Optical local area network using a common optical carrier with separate user angle modulation |
| US4701911A (en) * | 1986-09-15 | 1987-10-20 | General Electric Company | Media accessing apparatus and method for communication system |
| US5008877A (en) * | 1986-11-25 | 1991-04-16 | Raychem Corp. | Optical signal recovery for distribution communication system |
| US4847690A (en) * | 1987-02-19 | 1989-07-11 | Isix, Inc. | Interleaved video system, method and apparatus |
| US4821101A (en) * | 1987-02-19 | 1989-04-11 | Isix, Inc. | Video system, method and apparatus |
| US5111424A (en) * | 1987-05-01 | 1992-05-05 | Digital Equipment Corporation | Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfer |
| US4980854A (en) * | 1987-05-01 | 1990-12-25 | Digital Equipment Corporation | Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers |
| US5034883A (en) * | 1987-05-01 | 1991-07-23 | Digital Equipment Corporation | Lockhead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers |
| US4947368A (en) * | 1987-05-01 | 1990-08-07 | Digital Equipment Corporation | Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers |
| US5010480A (en) * | 1987-07-21 | 1991-04-23 | Dsp Technology | Communication interface for interfacing a data bus of a computer to a high speed bipolar communication system |
| US4945355A (en) * | 1988-10-27 | 1990-07-31 | Motorola, Inc. | System for cooperatively reassigning duties in a multiple controller environment |
| FR2638591B1 (en) * | 1988-11-03 | 1990-11-30 | Telephonie Ind Commerciale | SYNCHRONIZATION ARRANGEMENT FOR A PRIVATE DIGITAL AUTOMATIC SWITCH CONNECTED TO AN ISDN NETWORK |
| EP0381868B1 (en) * | 1989-01-17 | 1994-09-07 | Koninklijke Philips Electronics N.V. | Method and system for transmitting buffered data packets on a communications network |
| US4894826A (en) * | 1989-01-30 | 1990-01-16 | Honeywell, Inc. | Message generating communication apparatus having a message preamble format allowing parts of certain messages to be ignored |
| DE68916231T2 (en) * | 1989-03-23 | 1995-02-02 | Ibm | Method and device for multiple access with distributed queues in a communication system. |
| EP0413066B1 (en) * | 1989-08-16 | 1994-06-15 | Hewlett-Packard Company | Communications system |
| US5459836A (en) * | 1990-02-09 | 1995-10-17 | Unisys Corporation | Inter-processor communication net |
| US5265123A (en) * | 1990-02-15 | 1993-11-23 | Advanced Micro Devices, Inc. | Expandable repeater |
| WO1991016775A1 (en) * | 1990-04-25 | 1991-10-31 | Telxon Corporation | Communication system with adaptive media access control |
| US5307348A (en) * | 1990-11-05 | 1994-04-26 | Motorola, Inc. | Scheduling in a communication system |
| US5123029A (en) * | 1991-06-21 | 1992-06-16 | International Business Machines Corporation | Broadcast-initiated bipartite frame multi-access protocol |
| US5202593A (en) * | 1991-10-30 | 1993-04-13 | I-Cube Design Systems Inc. | Bi-directional bus repeater |
| US5276703A (en) * | 1992-01-13 | 1994-01-04 | Windata, Inc. | Wireless local area network communications system |
| EP0559214A1 (en) * | 1992-03-06 | 1993-09-08 | Pitney Bowes Inc. | Event driven commnication network |
| US5343474A (en) * | 1993-03-31 | 1994-08-30 | Honeywell Inc. | Slotted arbitration without time jitter in a table driven protocol |
| US5586150A (en) * | 1993-11-24 | 1996-12-17 | Rajupandaram K. Balasubramaniam | Method and apparatus for symbol synchronization in multi-level digital FM radio |
| US6334219B1 (en) | 1994-09-26 | 2001-12-25 | Adc Telecommunications Inc. | Channel selection for a hybrid fiber coax network |
| US5717932A (en) * | 1994-11-04 | 1998-02-10 | Texas Instruments Incorporated | Data transfer interrupt pacing |
| USRE42236E1 (en) | 1995-02-06 | 2011-03-22 | Adc Telecommunications, Inc. | Multiuse subcarriers in multipoint-to-point communication using orthogonal frequency division multiplexing |
| US7280564B1 (en) | 1995-02-06 | 2007-10-09 | Adc Telecommunications, Inc. | Synchronization techniques in multipoint-to-point communication using orthgonal frequency division multiplexing |
| AU5550896A (en) * | 1995-04-21 | 1996-11-07 | Illinois Institute Of Technology | Method and apparatus for distributed queue digital data tran smission employing variable length data slots |
| DE19620137C2 (en) * | 1996-05-07 | 2000-08-24 | Daimler Chrysler Ag | Protocol for security-critical applications |
| JP3526153B2 (en) * | 1996-11-19 | 2004-05-10 | ソニー株式会社 | Data recording / reproducing device |
| US5940402A (en) * | 1997-06-06 | 1999-08-17 | Timeplex, Inc. | Method and apparatus for TDM interrupt transmissions between multiple devices and a processor |
| US6370123B1 (en) | 1998-01-21 | 2002-04-09 | Lucent Technologies, Inc. | Method and system for half-duplex wireless communication |
| GB2356325B (en) * | 1999-11-11 | 2003-01-08 | Motorola Israel Ltd | Optimized random access scheme for a shared resource |
| US7283554B2 (en) * | 2001-02-12 | 2007-10-16 | Texas Instruments Incorporated | Network manager for a hybrid network environment |
| ATE313195T1 (en) * | 2002-04-16 | 2005-12-15 | Bosch Gmbh Robert | METHOD FOR SYNCHRONIZING CLOCKS IN A DISTRIBUTED COMMUNICATIONS SYSTEM |
| EP1355456A1 (en) * | 2002-04-16 | 2003-10-22 | Robert Bosch Gmbh | FlexRay communication protocol |
| US7756077B2 (en) * | 2007-02-06 | 2010-07-13 | Viasat, Inc. | Request signal designs for multiple service types |
| US20080273527A1 (en) * | 2007-05-03 | 2008-11-06 | The University Of Leicester | Distributed system |
| US7953060B2 (en) * | 2007-06-11 | 2011-05-31 | Viasat, Inc. | Quasisynchronous reservation requests |
| US8144680B2 (en) * | 2007-11-30 | 2012-03-27 | Viasat, Inc. | Contention-based communications |
| US20090167947A1 (en) * | 2007-12-27 | 2009-07-02 | Naoko Satoh | Video data processor and data bus management method thereof |
| EP3119112B1 (en) * | 2015-07-13 | 2020-01-15 | Volvo Car Corporation | Method and system for minimizing the required bandwidth for a cloud based unicast communication with a vehicle |
| DE112019007281T5 (en) * | 2019-05-03 | 2022-02-10 | Microchip Technology Incorporated | Media access for packets of time sensitive and best efforts data and related systems, methods and devices |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3710324A (en) * | 1970-04-01 | 1973-01-09 | Digital Equipment Corp | Data processing system |
| US3665404A (en) * | 1970-04-09 | 1972-05-23 | Burroughs Corp | Multi-processor processing system having interprocessor interrupt apparatus |
| US3851104A (en) * | 1973-04-11 | 1974-11-26 | Mitre Corp | Digital communications system |
| IT1012440B (en) * | 1974-05-16 | 1977-03-10 | Honeywell Inf Systems | APPARATUS FOR CONTROL OF THE INPUT AND OUTPUT CHANNELS OF A COMPUTER INFORMATION |
| US4038644A (en) * | 1975-11-19 | 1977-07-26 | Ncr Corporation | Destination selection apparatus for a bus oriented computer system |
| GB1538996A (en) * | 1976-03-10 | 1979-01-24 | Chestel Inc | Communication switching system |
| US4038642A (en) * | 1976-04-30 | 1977-07-26 | International Business Machines Corporation | Input/output interface logic for concurrent operations |
-
1978
- 1978-02-27 US US05/881,704 patent/US4161786A/en not_active Expired - Lifetime
-
1979
- 1979-02-26 CA CA322,336A patent/CA1133154A/en not_active Expired
- 1979-02-27 JP JP2146179A patent/JPS5530291A/en active Pending
- 1979-02-27 EP EP79100581A patent/EP0003849A3/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US4161786A (en) | 1979-07-17 |
| JPS5530291A (en) | 1980-03-04 |
| EP0003849A3 (en) | 1980-05-28 |
| EP0003849A2 (en) | 1979-09-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1133154A (en) | Digital bus communications system | |
| EP0100662B1 (en) | Digital communication system | |
| EP0138365B1 (en) | Communications network having a single node and a plurality of outstations | |
| AU712580B2 (en) | Method, device and data communication system for multilink polling | |
| US6097707A (en) | Adaptive digital wireless communications network apparatus and process | |
| US4937819A (en) | Time orthogonal multiple virtual dce for use in analog and digital networks | |
| FI98430C (en) | Base station for wireless digital telephone system | |
| GB2232041A (en) | Multichannel multipoint polling network using time-division mutliplexing | |
| IE54315B1 (en) | Synchronization apparatus in transmitting information on a simplex bus | |
| JPH0630485B2 (en) | Time division bidirectional transmission method | |
| JP3172937B2 (en) | Frame synchronization method between mobile stations | |
| US20060234738A1 (en) | Method for synchronisation of a radio communication system divided into radio cells a base station and a mobile station in such system | |
| CN107113754B (en) | Method for transmitting data between network devices via a non-deterministic network | |
| EP1297647A1 (en) | System and method for communicating between a plurality of asynchronous systems | |
| JP3052828B2 (en) | Multi-way time division multiplex wireless data communication method | |
| JP2000324535A (en) | Frame synchronizing device in mobile communication system | |
| US7620014B1 (en) | Radio communication method between a base station and mobile terminals | |
| US7260359B2 (en) | Method for transmission of data between a master station and a slave station, and a data transmission system | |
| JP3749907B2 (en) | Method for establishing synchronization between base stations and communication system | |
| JP2795179B2 (en) | Dynamic interrupt slot reservation method by PAMA method | |
| JPS6322745B2 (en) | ||
| US20230171718A1 (en) | Method and apparatus for synchronizing timeslot in wireless local area network system | |
| JPH1028098A (en) | Circuit access method | |
| JP2504457B2 (en) | Random access communication method | |
| JP2019004516A (en) | Radio communication control method and sensor accommodation terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |