CA1132234A - Distributed control digital switching system - Google Patents

Abstract

Alan James Lawrence, et. al.

DISTRIBUTED CONTROL DIGITAL SWITCHING SYSTEM

Abstract of the Disclosure A distributed control digital switching system is described in which a plurality of subscriber lines and trunks are provided with a switched access to various processing functions shared over a plurality of time shared multiplexed lines. Each processor of a first group of processors is dedicated to a group of terminals such as subscriber lines or trunks, and communicate with processors in a second group to provide pooled processing functions to one or more of said groups of terminals through a digital switching matrix. Processors in the first group perform a first set of processing functions, such as path set up and processors of the second group perform a second set of processing functions, such as call control.
A multistage switching network provides a modularly expandable digital group switch, the operation of which is controlled externally from the terminals to which it is connected and provides rate synchronous, phase (bit) asynchronous interconnection among the terminals which are interfaced and switched. Each processor of the first group is the shared over a security block of lines or trunks providing hardware interface therebetween while each processor of the second group provides pooled functions for a plurality of security blocks of lines and trunks. All data, speech and control signals are coupled over common transmission paths.

Description

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DISTRIBUTED CONTROL DIGITAI SWITCHING SYSTEM
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Cross Reference to Related Applications Alan J. Lawrence, et. al. Canadian Patent Ap-plication Serial No. 323,261, Expandable Digital Switching Network, filed on March 9, 1979.
Alan J. Lawrence, et. al. Canadian Patent Appli-cation Serial No. 323,260, Multiport Digital Switching Eleme~
filed on March 9, 1979.
Background of the Invention 1. Field of the Invention The present invention relates generally to distri-buted control digital communication and computer systems, to digital switching networks and to telephone exehangers for providing expandable subscriber line-trunk traffic capacity for toll, tandem, rural, localr concentration and expansion applieations. The present invention also relates to multi-processor or multicomputer communications systems in which certain of the data processing functions or other terminal processing functions are provided by one yroup of processors or computers while other processing funetions associated with different and larger groups of the termina~sare provided in-dependently by a second pooled group of processors, while com-munication and data exehanged between the two groups of pro-cessors or eomputers is provided over eommon transmission paths thru a digital switching network. The present invention also relates to multi-port switching elements eharaeterized in that the ports thereof funetion either as inlets or outlets depend-ing only upon the network application requirements for pro-viding one-sided, two-sided or multisided switches in the network.

2. Description of the Prior ~rt In modern telephone switching systems, it is present--2- ~

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ly required that data representative oE the status of the subscriber lines and trunks served by such a switching system, together with required actions by the switch in response to various lines and trunks status conditlons be stored. Repre-sentative data is path set-up through the network, subscriber class of service, trunk class of call, directory number of equipment number translations, equip--2a-J~

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~ lan J~;mes Lawxe~ce, et t 31.

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ment number to dire~:Xory number. translations, et~ n prior art centralized control ~;ys~ems, this data is avail- ~
~ le i~ a common m~mo~ which i~ duplicated for securit~
a~d ~eliability purposes aDd i~s accessible by common con-trol computers for se~ial opera~ior~s upo~ ~he extra ::t~d data. Multiproca~sins camrnc)n c:ontrol sy~ l:ems o~ the p~ior art :requi.:re ~o~e than one proce~ssox to ac:c~ss the c~on me~ory to obt ~ data a~ the ~ame time, re~lting in ~
te:~:Eerence p~o~ d . a~ ei~f e~::ti~e loss of ~hroughput, which increaseq a~ the ~er o~ proce~sor~ lncreases.
Dece~allzatio~ of control an~ distribu~ed data processir~g. ha~ evol~red in light of the problems ~ ent in a csnt~ally coll~xolled system. A prior art swi~chirlg system wherein stored program controllers are ~ist~ibuted throughou~ the systE3m i described by U ~. S . Pat~nt No .
3,974,34~. Ano.~her prior a~ progreesi~ely cor~trolled distribu~ed control switchlng syst~ is descri~ed by U~S.
Pat~t No. 3,86~,761.
Prior art ~y5'tem~3 have o~ce~ntra~edu~a~ ob~aining a high e~icie~cy for the proce~3~g fu~ctic~n, with multi-proc ssing pro~id~g inG~-eased processi~g c:apability;
- howe~er, with resllltant u:nde irable i~eractian betw~e~
s~ftwa~e pa~ag~s where~ ~he modi~icatiorl or additior~
oi~ eatu~es co~d lnt~rfer2 with the current wor}cins of o~er fea~u~res i~ a~ u~predictable ~nanner. A major reaso:n ~or the probLems o~ prior ar~ ~om~non control architec~e, w~et4he~ or rlot mult~ple processors are us~d, is that ctored. pro~ram c~n~:o~ proces~ing fur~ct~o~s a~e s~ared. ~n time }:et~e~ a pluralt.~y of t~sks ~hich randomly occur on d~mand of t~e origtna~ng and te~m~nat~llg traffic, whic~ does not provide or an effic~ent operation of the stored .softwa:re pac~cage~.
In accora~nce with t.~e pre ent invention, therP is no separ~e1y identii2~1e control or ce~tralized comput~r complex, si~c~ the con~ro1 ror t~e swi~ching net~or}c is distributed ~n th fo~ o mllltiple processors ~hroughout t~e suE~systems~ w~.th SUC}l di st:ribu~ed procPssor~; providing groups of necessary processing funct~ons for t~e subsystems .

- ~3~3 ~an James Lawr~nce r et. al .
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sen~icad. Thus, groups of coll~rol ~unctions for certain ystems æe p~r ormed by processor~ dedicated to those subsyst~msi however, other proce~sing ~unctio~s of th~
~ame ~u~sys~ems wh:Lch may be more e~icie~tly per~o~ned by other processt~rs are perfo~ned by suc:h other procPssors.
A1SQ ~ i~ acu~danc~ with t~ae present i~en~io~, a ~itch~g ~etwork a~c:hitec~ure i~3 pro~rided ~erein ~ot only ar~ multicha~n~l digitized PC~ ~peech sa~pl~ or data bete~leen one tel:minal and aIloth~:~ car~ied by ~he ne~wo~k, but the sam~3 channels al~o cont;~i~ ~e path selectio~ a~d other ct~ oL ~i~al~ fo~ t:he distri bnted control, whic~ a~e : ~
car~ied on the same ~sIaission path~ thru the netwGr}c.
E~ery te~minal, whe~her carryi~g dat~ f~om a line or trunk or o~heE aata source is servici~d by a ~erminal unit which cor~ta~ a~l o~ the facilities and control logic to c~ icate with ot}le:r t~ ls via oth~r terminal u~its . and to es~l~s~, mai~tain and t~ at~ paths thru th~
switrhing networ~c to o1:her ter~inal units. All inter-- p2:ocessor cc~unicat:Ltsn is routed ~ the switching net-2~ wc~r}c~ A group switch ~o~taining switchi~g elem~ts ~sro-~iding bo~ ti~e ana spac:s swi~chi~g is provided which is modularly exparlda~le wlthout disruptio~ of sentice or rearra~ge~en~ o existing interc~r~ec~ion~; to prov~ae a ~owth i~rom appro2imately ~20 to 128,0~Q or ~re ta}:~nals, to acc~modate incxeasing traffic load while pe~fo~ ig as- a~ e ~ecti~ly non-~loc~ing networ~c. A
failed switch ele~e~t i easily and auto~atically ide~ti~ied, isolated a~d bypasse~L by traf fic .
ac ::ordar~ with the pse~e:rLt ~ ion a group swits:h ~a is pro~ided in wh?ch multiport ~i~gle s1ded switchi~g ele-ments are ar~aagea}: le in any inlet~outlet co~figura~ion .
for example, as 8X~ switch ~ cor~tai~ing spacP.and ti~e switching in a ST co~figura~ionO The path sel~ction throu~hout the ne~or~ o~ swi~ching eleme~ts is pe:~formed 3 s by control co~ands carried by ~he speech channels .
Furthe:~, reflection switc~ing facllities r~ ided so ~at a ~at~
set up, for exa~nple, in a s .age ~wo swit ::h ~ when no s~age three is yet proYided, wil 1 be re~lected bac~ ~ria the speech ~32Z3~

path to form a folded network, while the outlets of the stage two switch remain available for future connection for network expansion. The expansion to a third stage would then require connection of the available outlets of sta~e two to the inlets of the future stage three switch.
Summary of the Invention A distributed control di~ital switching system is described in which a plurality of subscriber lines and trunks are provided with a switched access to various processing functions shared over a plurality of time shared mulitplexed ~lines. Each processor of a firstgroup bf processors is dedi-cated to a group of terminals such as subscriber lines or trunks, and communicate with processors in a second group to provide pooled processing functions to one or more of said groups of terminals through a digital switching matrix.
Processors in the first group perform a first set up processing functions, such as path set up and processors of the second group perform a second set of processing functions, such as call control.
A multistage switching network provides a modularly expandable di~gital group switch, the operation of which is controlled externally from the terminals to which it is con-nected, and provides rate synchronous, phase (bit) asychronous interconnectïon among the terminals which are interfaced and switched. Each processor of the first group is time shared over a security block of lines or trunks providing hardware interface therebetween while each processor of the second group provides pooled functions for a plurality of security blocks of lines and trunks. All data, speech and control signals are coupled over common transmission paths.

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~3~'~3~a According to a broad aspect of the present invention, there is provided a distributed control digital communication system for selectively interconnecting a plurality of groups of terminals through a digital switch-ing network having an access switching stage and one or more other switching stages comprising: a first group of data processing means for providing a first set of pooled processing functions for said groups of terminals~ each of said processing means being associated with one of said groups of terminals;
a second group of data processing means for providing a second set of pooled processing functions for one or more of said groups of terminals such that said second processing functions are provided independently of the processing functions provided by said first group of processing means; and digital switching network means coupled to said first and second groups of processing means by one or more multiplexed transmission paths over which data and at least path selection control signals are transmitted in frames containing a plurality of channels of said data, such that said path selection control signals established communication over said multiplexed transmission paths thru said digital switching network means between said first and second groups of data processing means with said path selection control signals preceding said data on said multiplexed transmission paths in the same channels and selectively interconnected said terminals over transmission paths thru said switching network in channels designated by said path selection control signals.
According to another broad aspect of the present invention there is provided a method of communicating between a plurality of terminals having data in frames containing a plurality of channels of said data coupled there-to, wherein a plurality of groups o said terminals are selectively inter-connected thru a digital switching network in response to in-channel path selection commands, comprising the steps of: deriving a first set of pro-cessing functions including said in-channel path selection commands for said groups of terminals, said processing functions being derived by a first plura-lity of processors in a first group of said processors; deriving a second --5a-' ~.3'~3~

set of processing functions by a second plurality of processors in a second group of processors for one or more of said groups of terminals such that said second set of processing functions are derived independently of the first set of processing functions;
and interconnecting said first and second pluralities of proces-sors thru a digital switching network coupled to the first and second pluralities of processors by one or more multiplexed bidirectional transmission links over which data and at least path selection control signals are bit-asynchronously transmitted to provide interconnection between said first and second plural-ities of processors in channels designated by said co~mands and selective interconnection of said data in said channels between said terminals over common transmission paths thru said switching network established by said path selection control signals.
According to a further broad aspect of the present inventi.on there is provided a distributed control digital com-munication system comprising a plurality of terminal units for interfacing a plurality of PCM communication terminals carry-ing digitized speech in frames containing a plurality of chan-nels of said digitized speech to a common communications path upon which said frames and in-channel path selection control sig-nals are multiplexed, and comprising: means for deriving at least digital path selection control signals for each PCM ter-minal interfaced thereto; a digital switching network coupled to said communication path for bit asynchronously interconnecting said PCM terminals through paths established thru said switching network in response to said in--5b- ~:

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channel path selection control signals, and; means at each of said terminal units for selectively multiplexing said diyitized speech and said in-channel path selection control signals on said common communications path such that said digital path selection control signals precede said digitized speech in chan-nels designated by said path selection control signals on said common communcations path.
The invenbion will now be described in more detail with reference to the accompanying drawings.

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. Alan Jam~ Lawx~nce, et. al.

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Fi~e 1 is a block diagram o a distri}: uted co~trol syst~m ~ accorda~ee with the in~ent:ion., Fi~e 2 illustrate~ the modular e~pandability oi~ the ;~' switching netw~rk o~ the in~ention. ., Pigu:ce 3 is a ~implified bloc3c diag::a~ of a ~ ipo:~t h~g ~iemeslt or the inve~ti~n.
Figure 4 il~trate~ one plane of a s~itch~g 3~e~wor}~
of t~e ~venti~n Figu~e-~ 5 (a), 5 ~b), 5 (c) ana s ~a) illu~;tr ta the ~an sior~ o~ the switc~ag ~etwor}~ of.t~e i~ent~on.
Pigu::~ 6 i~ a bloc~c diagram o~ a l~é te~inal su~ O ~.
- Figure 7 i a bloc:~ diagram o~ a ~ te~m~al ~ubunit.
Pigu:re 8 is a simpli~ied illustra~io~ of the ~DM bus o:~ the multiport switchi~g el~aent o~ the irl~elltion.
Pigu:re 9 is a bloc~c diagxa~n of the logic of one por.' of th~.Dn~tipo~t switch~} elem~t of ~e i~re~ti~n.
~i~e~ 10 (a~, 10 ~bl, LO (c), 10 (d) a~d 10 (e) illustrate ~an~el ~rd fo~:mats ~sed ~ the i~ention.
E'~ 13 11 ~a), 1~ b), ll ~c) aa~d ll (d) illustxat~
additio~al chan~el wora fo~at~ u~;ed i~ 'che invention.
Pigure 12 illustxates a typical co~ctio~ }:etwee~
te~inals thru the swit~:L2~g ne~o3:3c o~ ~he i3nren~cion~
s 13 ~ ) ;.13 (b), i3 tc) ~ 13 (d), 13 ~e~, i3 (f), 13 ~g), and 1 3 ~h) are t~ins diagr=~ ill~s~ative of the op~ration o~ t:he switch~g elements a~ ~e ila~eQtion.
Figura 14 ~a), 14 ~ 4 (c), 14 (d) a~ 14 te) are more detailed ~ g. diagram~ illu~trati~e o~E the opera~io~ o~
the switchi~g el~sents o~ ~e in~ io~.
~o ~igure 15 illustrate. the ~DM bus lir~es of a switching element o~ the~ entioa.

Alar~ Ja :aes ~wrence, et ,, al .

~5~ g~ferred Embodiment .
____ R~ferri~g to Figure 1, a sy~ te~ ~lock diagram o~
a di ~ ibut:ed contr:31 digita~ switch~g system comprising a g~:oup s~itch 10 ~w whic~ ~ pluxalit~ of colmectio~s S betwe~ te~:minal ll~ 3 are ~witched to pro~ide tra~s~
~issia~ pat~s ~o~ coupl:Lng data betw~en ~e~minal~ serviced by ~a ter~al u~its.
~ A~ used here~ a tersni~al unit is a subsy3te~ ~o~
ser~ic~ a group o~ t~ als which ter~i~ate or~ oné
f~rst ~taqe s,witch ~n every pla~e o~ the grQUp switch.
Eac~ tg~mi2~al ~it include~ eight acce~s switches through whic~ da~a ~rom ~he ~als is coupl~d to and ~rom the gxoup ~itch 10.
A~ used hes:f~in7 a te~al su~u~it is a su~syste~n o a termi :nal u~it or s~rvici~g a group o~ te2minals which ~=~inate on ona ~e~ y pair o~ a~cess swltches. /

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~JL~ d~3 Each terminal uni-t contains ~our security ~airs of access switches. The PCM data at each terminal is deri~ed, for e~ample, from telephone line circuits of the type described in detail in Canadian Patent nu~ber 1,096,522 which issued on February 24, 1981 -to Interna-tional S-tandard Elec-tric Corp.
Terminal units 12, 14 and 16 are representatively shown; however up to 128 terminal units or more may be switched by the group switch 10;
hence terminal units 12, 14 and 16 are illustrative only. Each terminal unit has the capability of in-terfacing, for example, 1920 subscriber line terminals or 480 trunks to four terminal subunits, with terminal subunits 18, 20, 22 and 24 illustrated for terminal unit 12.
Thirty-two channel PCM mul-tiplexed digital lines having multi-plexed thereon thirty bidirectional subscriber lines are coupled to the ter-minal units.
Each terminal unit such as terminal unit 12 is coupled to group switch 10 by a plurality of multiplexed transmission links, each of which transmission links comprises two unidirectional transmission paths. Each terminal subunit 18, 20, 22 and 24 of terminal unit 12 is coupled to each plane of the group switch 10 by two such transmission links, thus for ter-minal subunit 18, transmission links 26 and 28 are illustrated as coupling terminal subunit 18 to plane 0 of group switch 10 and transmission links 30 and 32 couple terminal subunit 18 to plane 3 of group switch 10. Simil-arly, terminal subunit 18 is coupled to planesl and 2 of the group switch 10 by similar transmission links. Subunits 20, 22 and 24 are also coupled to every plane of the group switch in like manner as is terminal subunit 18.
Each transmission link 26, 28, 30 and 32 shown for terminal sub-unit 18 is bidirectional in that it includes a pair of unidirectional trans-mission paths, each path being dedicated to one direction of data flow.
Each lmidi~ectional transmission path carries thirty-two channels of digital information time division multiplexed (TDM) thereon in bit-serial format.
Each frame of TDM format is comprised of the thirty-two channels with each channel having 16-bits of information, and at a bit transmission ra-te of .

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4.og6 ~b/s. This transmission rate is cloc~.ed throughout the system, hence, the system may be charactcri~e~ as rate synchronous.
Since, as will be explained hereinaf-ter, the system is also phase asynchronous, such -that there is no required phase relationship as to which data bits in a frame are received by dif~erent switching elements or by the different ports in a single switching element. This rate synchronous and phase asynchronous switching system is implemented in the group switch and in the access switches by a plurali-ty of multi--port switching elements.
When digital speech sarnples are transmitted anywhere within the system to or from a particular terminal, the digital speech samples must be time multi-plexed into the correct channels on the transmission links between switching elements used to connect the terminals. Time slot interchange is provided by each switching element, since the channels used -to interconnect the ter-minals may vary.
Time slot interchange, i.e. the transposition of data on one channel to another channel is well known and described, for example, in Canadian Patent number 1,101,531 which issued on May 19, 1981 to Internat-ional Standard Electric Corporation. As wil~ be described, a unique multi-port switching mechanism, which may comprise a 16-port switching element operative as a thirty-two channel time switch and a sixteen port space switch in typically less than a single frame time for all inputs thereto is provided.
The digital speech samples may comprise up to 14-bits of the 16-bit channel word with the two remaining bits being used as protocol bits (to identify the data type in the other 14-bits of the channel word). Thus the 16-port switching element can be used to switch, for example, 14-bit linear PCM
samples, 13-bit linear PCM samples, 3-bit companded PCM samples, 8-bit data bytes, etc.

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Alan ~ame3 I~awr~c~, et. al.

rwo groupof processors are included within each .
te~al subunit, such aS te~ nal suE~unit. 18, the first group c~ proc~ass~r~, ~how:r~ as processar~ , Al, ..~7, z~e ea~ ded:i at~d to a 5epa~ate group o ~E3r~nals, c~lled

5: a termi~al cl~ste~, z!md per:~o~m Z!~ speci~ic group oi~ procsq-2i~g ~unctions, such a-~ path ~t-up t}~rough the group s~i tch lo a~a th~ pro~i~io~ of an i~te~:~ace~ to the te~
al~ with:Ln . the te:emiD,~l clu~3te~ o ' ' }~igh t:raff~c cluster~, . such a~ t~leph~e ~ line.~ may i:~clu~e up to thir~y 1~ te~ al~ wh~re2~ w trai~f ic clusters, such as ~elephone su}~scs~ber line~ ~ay c~n~ai~ ~ap to s~x~y tarm~als. Each - te3~al subu~it ~ay ~erface with up to ~o~: high ~a-fic cluste:rs; he~c~ contai s four A-type proc:essoæs, where-as a. lcw ~af:Eic su}~u~it may ~te~ ce wit~ e:Lgh~ lo~ ~af-fic s:lusters a~d hens:e con~n~ eight A ~ pxocessor .
Ea~ A-pfflcs~or may irl~lud~ ~or 3x~Lmple, a~ I;ntel Corp.
Model 8085 microproc:E~s~c~r :Lnterface a~d associated R~ . .
and RC~ m~no~ ~s, e~ach te:c~inal u~2it may co~t aI~, ..
for exa~pl~, up to 1~20 low ~a~ic ~e~als (~or ~ .
sc~iber ~nes) or 480 high ~a~ic t~c t2~minals. Eaeh t~al ~lu~te~, such as teD.~al cluster 3 6 ~ s~u~it .
13 ~cl~de~ one A-proce or a~d its as~ociate~ clu ter te~i~al ~erfac~. ~is ~luster t~nal irlterface is ct~upled by a pair o~ bidixec~ion 1 li~k~ 38 a~d 40 respec-ti~rely to each u~ l:wo acc s switche~ 42 a~d 44 wit:~in t~al subunit 18~ Thl3 access switch3.~g ele~ents, such - as acc~s ~wit~ eles~e~t~ 42 and 44 of ~ub~it 18 are o~ .
1:he same switch:L~g @le~e~t ~nf:igura~o~ as ar~ the switch-i~g elemen~s of the group switch 10. Ac~es~ swit~hiny ele~ents 42 arl~ 44 each p3:ovide access for s~burlit 18 to o~e ~ a pai~: of a sec:ond group of proc-ssors, such ?S processors Bo ~ Bl in tersninal su}~ it 18~ Oth~
pairs o~ B-type processors are included within te~inal subunits 20, 22 and 24, but ~or purpose of desc:~iption, only th2 B-proc~ssors ~f ~unit 18 are illustrated.
This second group of proce3sors, the B-processors r ar~

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dedica-ted to a second ?frroup ol` processin!r fun(tions, such as call control (the processing of call related data, such as -ignalling anal~/sis, trans-lations~ etc.) for -the terminals interfaced by terminal subunit 18 and may also be implemented by In-tel ~orp. microprocessor Model Mo. 8085 or its equivalent. A security pair of processors is constituted by -the inclusion of identical processing functions in B-processors 46 and 48 and the access switches 42 and 44 for terminal subunit 18, therefore allowing each terminal cluster such as the Ao cluster to select either half of -the security pair, i.e. either B-processor 46 via access switch 42 or B-processor 48 via access switch 44 in the event of a failure of one half of the security pair, thereby providing an alternate path.
Referring now to Figure 2, the group switching matrix 10 having four independent planes of switching capability, plane 0 at 100, plane 1 at 102, plane 2 at 104 and plane 3 at 106 is illustrated.
A plurality of planes are provided to meet the traffic and service integrity requirements of the particular system application. In preferred embodiments, two, three or four planes of switching may be provided, which will service 120,ooo or more terminals, i.e. subscriber lines terminating in the aforementioned line circuits such as that of Canadian Patent number 1,096, s22.
Each plane of switching may contain, up to three stages of swit-ching elements in a preferred architecture. Access switching which selects a particular plane for a connection may be located within the individual terminal unit 12, rather than in the group switch 10. The particular plane of switching elements is selected for a connection by the access switching stage in the terminal unit. Thus, access switching element 42 in subunit 18 can select, for example, plane 0, 100 via link 26 and plane 3, 106 via link 30.

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Ala~ Jame~ I.awrenc~3, tO al-1-',~1-1 ~:oup switc~ 10 is ~aodulasly lexpanaa~le either hy increa g the nu~er of planes to increase data tra~ic dling per:9rmallCs' ~ or b~ crea;sing the number of stag~s of swl~chi~g elements or t.'le n~Dber of switch~ ng elemerlts per stag~ to lncrease t~e num~er o~ te~nals ser~rea by the group ~itch. The number of stages per pla:Le o~ the groUl? ~witch 10 for typical application ~eguir.emen~ i modular.Ly .expandabl~ ~ ~ollow-~:
~_ ~N}~S . T2~DE~
IoSTA~E PE~ LOC~; AP~l!ION_ APP~ICATIO~
. .''.'' ' P~ 7E'' ~ ~9 ~3 _ 1 ONI~ 8 1,~00 1,120 2~0 aIld 2 64 10, 00011, 500 3, S00 1, 2 and 3 1, 024 ~100, 00 0>120, 000 ~ 60, 00 0 .
R~ferring naw to Figu:Ee 3, a ~undamental switching .
1~ eIe~ent o t~:e }?resent in~ntion ~rom which all switching .
stage~ are c~nigured may comprise a multiport sillglesided swit~-h 300 which is illustrati~rely desc:ri}~ed as a 16;port switch:L~g elem~t. ~t is to be ~derst~d l:hat the numb~r o por~s could be greate~ r less t:han sixt~e~, whi h i5 2~ . described as ~ ex~ple only. A single-3i~ed switch may be def irled 2~3 a switc~ing alement ha~ring a plurality oi~
pcrts o bidireckional transmission capabilit~ in which d~ta rec~ d a~ any port may be switc:hed to and transm:Ltted by a~Ly po~ (eithe:~ the ~a~e or o~er port Ot ~he swit~h~ng ~5 elemen~. Opexa~ionally, all data tran~er from po~ ts:
port wi1:h~ switc~ing element 300 is acs:cmplished ~ia a bit-parallel ti~e di~ision multiple~ DM~ bus 302, which enables space swi.tchi~g which may be defined ?S ~he ~?ro~rision of a transmissio~ path bet~een any two portC within the switching elemerlt:.
Each port 0 'chru 15 of swi.chi;lg element 300 inc:ludes its own rec~ive c:~ntrol logic R.Y302 and its own transmit control logic Tx3 0 6 illustra~ed by way of example, ~. or port number 7. Data is transf~rred to ~nd fro~ any port such as port 7 of the switchlng el~t 300 f rom switeh--Ala~ James Lawrence, et. al.
l~
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elements o~ liXe con~gurati~n with whic~ switching el~m~nt 30~ is linked in bit-serial for~at ~i~ the receive control -~
input line 308 and ~ransmit ~ontrol output line 310, respec-ti~ely, at the 4.096 ~b/s system clock rate, with 512 serial bits c~nstituting a frame, which i~ ~ubdivided into thirty- -two cha~nels o~ 16-bit~ ea h.
Data tr~nsmitted serially ~rom the ~ixtee~ port3 is both rate a~d pha e sy~chro~ous~ i~e., ~he tra~smit eontro iogic 30~ and the equ:L~alent ~a~smit c:on~ol logic ~or t:he ather 15 port5 0~ the ~witching ele~e~t 300 all trar~s-mit a~ the same 4 . 096 D~/s cloc~c rate, and at arly ins~ant are ~ransmitti~g th~ same bit posi~iorL c~f a frame. On the other ha~d ~ rec~ption of }: i~ erial aata at the recei~e cs:~ntrol logic 304 o~ po~ 7 and at all o~aer ports ~f the switchi~g ele~e~t 300 i~ rat~ synchro~ous only, i. e,, there is no nece~sary r~la~ic~nship wil:h respect to wh~ch . bit ~n a f~ at a~y ~wO por~s may b~ recei~ing at any islsta~t. Thus, re~ption is phase aqync.~onous. Rec~i~Je co~ ol logic 304 and transmi.t control logic 306 each in clude a co3ltrol l~gic portion and ~ random access m~ory~
described with rei~eren ::e to Figure 9 .
Re:Ee:~ing now to Pigure 4, one pla~e of group switch 10, uch a-~: plas~e 0, 100 is illustrated. As de~c~ibed with ref ereIlc~ to Figure 3, ~e switching elements such 2~ . as 108, 110, 112, from which the group switch pIa~e is cons tr-acted æe 16-port single-sided swi~chi~g elemen~s 30û o It is only by de:~ition L . e., posi~ion ~ the swi~ h-ing net~r~c t t~at switoh por~s a~e ~esig~ed as :Lnl.ets .or outlet I~ the three stage group switch plane 1O0J aIa .
illus~rati~e em~odi~ents shows ports 0 thru 7 o switch-i~g elemen~s 108 and 110 ~n stages 1 and 2 are de~ignated .
a i~l~ts and ports 8 ~hru 15 axe de~i~nated aC outlets, thus appeari~ as two~sided, w~erein in stage 3, all switch-i~g el~ments such as switchi~g elements 112 are single~sided, i.e., all ~ortS are designed as inlets.
In general, considering any group switch stage, i a~
soma ~ime additional stages are nacessary to modularly effe~t ne~ork growth, then t~e s~age is equip~ed as a two sided ~3~3~

Al an J~ne~ ~awrence, et. al.

~tage wi~h the outle~s reserve~ ~or ~rowth. ~we~er~ if at aRy ~tage the 5i2e 0~ the networ~ allows great~r tha~ -half ~he ~axLmum r~quired term~als-to be conn~cted, ~hen the stag~ is equippad as a single-~ded stage~ This allcw~
co~ual m~ular expa~.ion up to the max~mum required ~etwork ~ize without re~uiring a rearrange~ent o the li~k-~ng betwee~ ~age~. . .
The.~odula~ exp~ ion o khe ~witc ~ y el~ment 300 to a switchin~ plane 100 i5 illustra~ed ~y ~i~ures S(a~ ~hru 5 ~d) . Pi gure 5 ~a) illllstrate~ the size o~ a g~oup switch plan6! of a group ~itch 10 reqaired for an application o~
one te~:sninal ~ it Aa~i~g, for exa~nple~ ut 1000 subsrriber l~es . ~!hu~, po:r~ 0 naay ~e coupled to lir~e 2 6 o~ te~ninal subu~lt.18 while pc~ 1 thr~a 7 are coupled to ~ther acc~ss swi~ches i~ t~t? Aal l~it 12 . Por1:s 8 thru 15 are resen~ed ~or networ~ gr~w~O
Refe~:ri~g t~ Fi~e 5 (b), an exampl~ si~ the ~ext stage o~ growt}l o:~ the grQUp~ switch pla2le 100 i~ illu tratPd~ for ........ twc te~i~al uD.its, such as t~al units 12 a~d 14. Thus, two ~irs~ s~age s~itching elements are prc~71aed pe~ plane of the group ~witch with each plane ha~g c2cond ~tage swi~chi~g el~ments t ' :Eor examlple 0, 1, 2 and 3 to intercon~ect the two first staga switc}~i~g el~ents. The outlets on the seccnd ~tage a~e reser~ed for su~seque~ networ~ growth, a~d ~ ; netwo~}c (o~e plane of whic:h i5 illus-~te~) ws.ll s~r~ice a~ou~ 2000 subs riber li~e Re~erri~g now ~o Fisure 5(c~, a~ example o the grow~h of a s~itchi~g plane 100 ~ ac~o~oda~e eight ~ermi~al u~it~
iS illu tratedO The ~tage 1 and ~taga 2 switching element~
are now ~h~wn as fully inter~onnected an~ onl~ stage 2 o~tlets are a~a~lable ~or further growth, hence to intPr connect ad~itional groups o~ up to eight ~e~minal units, a ~hird stage oi switching per plane m~s~ be ad~ed, as illus trated ~y Fig~r~ 5~d), which ill~s~ra~es s~aen te~minal unit-~ coupled to ~he expanded grOUD switch plane. Typical-ly~ the switehing capability of the rletwor.~ or Fig~x~ ~ (c) is about 10, 000 subs~riber 1ln~3 a~d the switc:hing capability ~3~

A~ Jame~ LawxencP, et. al.
~, , --lg--o:E ~he netwc~rk of Fiyure 5 (d) :is about ~0, 000 subscriber lines. The unconnec:ted po~ts as shown in Figure 5 (}~
5 tc) as~d 5 td) re available for expansion~ and each plar~e of t~ ~etw~rk, :~or exa~ple Fic~re 5 (d~ is e~panded by , -connection of t:}lese ports up to, for exa~ple, the net~o~
of Figu:~:e 4, whic:~ ha~ a capacity to ~itch ~n ~xc~;s of 100, 000 ~criber li~e~ .
Rsferring now to Figu:ee 6 ! a lir e termi~al suhunit 18 i5 illus~ated which i~cludes up t~ eigh~ t~al cl~te:r~ 36, each e7~ which te~inal clu^~te~s ~clude ~ty subscr~ber li~es, a t ~ al i~terfaca and an O A-microprocessox, ~ee of whic}~ te::minal clustE~rs a:re illust:rated a~ 36, 37 ar~d 39. The termi~al sub~ it 18 access ~witches 180 a~d 181 senre eight terminal cluste~;, . 15 - thre~ of which are illus~rated or sLmpli~ity of descrip~
tio~. Each ~erminal ~te ~acs, such as interface 190 i5 associatQd with fo~ example, siæl:y subscriber l~es f::c~
5iX~ ~e circui~, a~d an A processor 198 which is dedi-cated to ce~in p~ocass:~g ~unctio~s, such as path set-up ~: through the switc~i~g r~etwor3cr or te~al con~l, for li~es coupled to ~ ~e~inal ir~terfac~ 1~0. Each te~mi~al int~r:Eace 1~0 has one bidire t~ onal transralssio~ li~ such as 1~ 199 to a porl: of eac:h o~ the a~c 5S swi~c:hes s~ch as access switches 180 and 181., Each ac ess swit~h such as acc:ess switc~ 180, ~ich c~xises the 16-p~rt swi~ching ele~ent descri~ed with rer2renca to Figure 3, provi~es switched acc~33 eit~e~r to the pl2n~ of the group switch 10, fox exarapl~, ~Ia outlet porl:s 8, 10, 12, 14 01:` to a B-proca~sor 18:3 ~i~ ~ox example an ou~let such as outlet 3a port 9, t~is 3~-processor ~erform~g other process~g fun ction~ such as call c~trol. ~used outlet ports o~ th ac~ess switch, 3uch as p~ts 11, 13 and 15; are shown as SP.~E and ar~ a~ailable for e~uipping other de~ices such as alarms, monitors, dia~nostics controllers, e~
R~ferrins now to Pigure 7, a ~run~ te~inal subunit such as subunit 18 is showm which is ~u~ctionally ide~tical to the line ter~inal s~bunit described with rerorenc2 ~o 3~

Alan Jame~ Lawrence, et.

Figu~e 6; howeYer, whic:h ser~ice.~ a lesser nunsber o:~ high traffic i~puts. To ac:count or the increased trai~fic inte~si~y-o~ trun~ g:roups co~npared with line terminals, the truYlk te~minal subunit compr.ises up to four texminal ~terfa~e~ each of which is asso,ciate~ with, ~or example, thir~y ~run}c tenLL~als. Thus, ~lets 4 t~rou~h 7 on each ~cce~ switch 180 and 181 areun~sedin thi~ con~iguration.
Thu~, ~k tex~n~l clusters 60 and 61 o~ ~ou~ t~k .t~2al ~laste~ e illustrated, each i~c~ di~g a te~
al int~ace 62 a~d 63 re~pecti~rely and an A~proces~or a~d memc~ry 64 aIId 65 respec~elyO .
The B~proc~s~or and associa~ed ~nemory 66 ana 67 cuupl~d to acce~s ~witch L80 a~d B-processor ~a as~;ociated m~ory 68 a~d 69 coupled to aGce ~i switch 181 a~e o~ the same con-. iguratioIl as-descri~ed with re~erence to figure. 6, arLd may for Pxample coD~rise Intel Corp. 8085 ~v~l~del microprocessors.
. Referri~lg n~w to Pigt~rP 8, t~le sixteen po~t switching .
eleYne~t 300 desc~ ~ ed wi ~ re~erence ~o ~iglIre 3 will be f~Lrt~heu~ d~sc~eibe~. Each po rt, sl~ch ?9; pox~t 15 0~ t~he switc~-2~ i~ g eleYne~lt 300~ consis~s o~ a re ei~e cont~:ol logic 304, a t~r ~ sr~it contarol logic 306, inp~t ~ d ou~put lulidirec~ion-al ~ ansm~s-~io~ pat~ls 308 a~d 310 resp~c~i~ely, ~ d acce~
to a paurallel ti~me di~ision mul~iplexed bus 30~ wit~lin switch~g el~ment 30 a .
2~ a prefa ~ e~ e~lbod~I~ent of the inYen~io~, co~e~ions e set up thcough the swi~chi~g ele~ent 300 on a u~nidirec--tional ~siiI?l ~ ~ basis. A siI~ple~ connection ~e ~ een ~
input chauLnel of a po~ (one o~ 32 chalun~ls) to ~ output cha~Ln~l of auly port (one of 51~ chaI~nels) is est~blishe~
3Q` by aun ~ - ~ au~n~!l c~n~and r~fes~red to as a SEI;@CT cc$mnaund.
TSis S~3~ECT co~m~an~ is co~tained i~ ~ e si~gle 16-~it word i~ ~ e input cha~Lnel reqrl~sting the connection. A nu~ber of differe~ t~pes of cor~lections ~ e possible thLr~ugh a switch ~ g ele~ent and these are differentiated by in~or-nLation in t~he S~I~ECT co~nn ~ d. Typical select coD~nands aLea ~any po ~ , any chau~nel"; which is a conmnand tha~ is recei~ed by the recei~re control logic o. ~he po ~ and in~tiatos a coDLnection to any rree chax~nel in any outle~ ¦

3~
-- ._ . . . .... .

Ala~ Jame~; Lawrence, et. al.

o~ a~y port, "Por~ N ~ ~y channel ''; is anather S~:I,ECT
command which i~itiates a connectio~ to ~y t~re~ chan~el in a particular po~ N, ~.e., port 8 "Port N, C~annel ~;
i~ anoth~3: S}~ECT command which, l~itiate~ a con~ctic:n to a speciie~ ch2~el M ~uch a cha~nel 5 in ~ speci:ied port N, such a~ po~t a. Other ~p~c:ialized SEIECT c=and such as ~comlact to o~e c~f any add ~r e~ren) ~ ered port~"
aIld specialized cha~n~l 16 comm~d~ and ~ai~ter~ance commands ~ chan~el 0 ~e ~cluaed in the capaci~y o the switch module ~one por~ ~Lereoi~ ~ei~g comprise~ o~ on~ modul~), as described i~L greater de~a~.l wi~h re~ere~ e to Pigur e 9 .
The receiYe c~ntrol logic 304 for each pOIt sy~chro~izes ts:~ the incoming dat~ from o~er switchi~g ele~ents. T}le ch~el ~umber ( 0-31~ of t~e ~ncomLn~} chaD;nel i s use~ tt:3 lS f etch dest~a~on port and chan~el addre~se3 f~om port .
and channel a~dress storage RA~L's. ~uri~g ~he multiple~ed B m3od~ e access to bus 302` i~ ~e cha~nel th~ re~:eive lc~gic sends the recei~ed chan:Qel wc~rd along with its des~-a~ion p~rt and c~a~el ad~e~ses ~o the ~1~ bu~; 302 of swit h~ng elemen~ 300. Dur~g è~re~ us cy~le tthe ~ime duri~g3wh~i h data is trarlsferred from the rE~caive c~nt ol logis: ~ to the transmit control 1~3gic 306), every r~l5-~it logIc at eve~ port looks for its E~ort address cm the ~ bus 3~2. I~. ~he port r~ulPber Oll the bus 302 c~rresponds 2$ ta the unique address of r~ar~i~ular ~ort, ~e data (cl~el t~rds) o~ the bus 302 is writte~ into ~e data RAM of t}:~e re~ g-nizing port at an address c~rre~po~di~s to ~e addres~ -read out ~ e chanD~l RAM to th~ rec~i~re c~ntrol logic port O This accomplishes a o~e-word da~ ransf er ~rom a rereive co~tro.l logic t~rough ~he ~D~ bus 302 to the tra~s- .
mit control logic of a port.
The port transmi.t and rec i~Te co~rol logic for a typical port 3ûO operates as follows: Da~a at 4 . 096~b/s on line 308 i.s coupled into i~put syr~c circui~ 400, which pro~ide bit a:~ld word synchroniza~ion to the info~snation ~.
on li~e 3û8. The out~u~ of sync cir~uit 400 is ~ 16~

~ . .

. Alan Jame~ Lawrenc~, et, al.

,, cha~nel word and i~s channel number (representing the channel position within the fr;ame3, is coupled to -a ~irs~ lrs~-out buf:~er register stac}c 402 which synchroniz~s data on line 403 to th~ bu~ 302 ti~ing, which is re~uired si~::e aata o~n line 308 is asynchxenous to the ~us; 302 ~g. The FI:FO bui~er 402 outpu~ i~; a 16-~it chann~l word a~d it 5-bit ch~nel rlumbex. I~-fo~matio~ co~tainea wit~:Ln the 16~bit chaD~el wora in-dicates the ~ture of ~he in~o~Latiora co~tair~ed by 1:he wordO Thi~ ~fo~tion i~ contai~ed withi~ protocol bits o~ the char~n~l word a~a toge~e~ with ir~oxmation i~ the ~ecaiYe c:o~trol ~¢ 404 speci~ies the action to be l~ by t:he rec~e cont ol Ci~CU;Lt 406 for this .
ohar~el in this frame.
7 5 Five ~ypes o actions, 5PAT~, 5EI2~ aG~, ES~APE
or IDT ~C~æaR are poscihle . I;E t:h~ proto ::ol is SPAT~
~speec~ dat~ woras~, ~e chan~el word ~s sent to - bus 3Q2 u~odified and the c}~nel add~ess etches des~ a~:ion ~?ort ~ l addr~sses from t~e channel RAM 408 a~d the po~ RA~ 410 a~sd co~ples th~ to ~he bus ', 30~ du~ing ~e p~rt' s receive logic bus access t~me ~;lot~
If a select co~m~a is "a~y port~ y chan~el" the ~irst:
fre~ po:rt selec~ ci~ 412 selectY a transmit logic wi~h a~ chan~Lel to do ~ "first ~xee channel selec~" :
into. 3~uring ~e recs~e logic T9~ bus: 302 acces~ t~
a "i~irst :f~xe~ chaDnel select" is done into the selected po~: into the ~elec~es~ ~ransmi~ logic whic:h retu~ a "~ree charmel" n~nber ~ro~a its ~ir~t ~ree channel searc~
cir~it 414. A iJl~C}t receive cir~it 416 eY~a~nes t:he c~nt~ats o~ channel-16 for p th set-up failure i:ndicatioals frt~m suc~eedi~g stages o ~Ae swit ::hi~g ne~w~r3c that ha~e been set up throllgh ~he trans~nit logic 306 of the module~, ~laCR search logic 408 examines the recei~e control ~ 404 ~or chans~els l:hat ar~ ~AC~; ' ed (not ac.l~nowledged) and causes 3 5 the channel m~mbers of N~CR ~ ed ::harmels to be out~?ulsed from the tran.smit logic 306 in chan~el-16.
T~ smit logic 306 examines the state of thf~ ~or~

~3~3'~
Alan James Lawxence, et. al.

--18-- .
adare~s lines of t~e bus 30~ Wi~l its module identi~ at~ on code at decode po~t logic~ If t~le correct port addre~s is ~ec:aded at decoder 420, and the select line o bus 302 is inacti~2, then ~e conte~t~ o t}le SPATA line~ o~ the bus 302 will be written in~o dat~ ~ 422 at an ad~ress gi~
by the state of the channel add,.~eass lines of the bus 30~.
:1: the select line o:E bu~ 302 is ac~i~e a~d a first free c:han~el ~earc:h is reque3te~ by receive control SUC}
ac~ 406 ~for any channel selection) t~en rlo data RAl!l 422 14 write operatios~ c: ccurs, but a free cha~nel n~n~er is return-ed to the re~ue~T~g recoive logic such as 3 0 4 fr the ~ rsJ f:l:ee channel search circ~it 414 .
The data R~N .22 i5 a time slot L~tercha~ger ar~d is read out of se~ tially under the co~trol o:E~ a c:ounter I5 colltai~ed in trarlsmit/buq ti~ri~ circuit 428. Words read ou~ of dat2 RAI!E 422 a:~e loaaed into a p allel-inpu~-ser-r ial~utpul: regi~ter 430 which couples the serial bit ~tream.
to tra~smit li~ 310 at 4. 096 ~/s. 'r~e word loaded i~to output re~ister 430 may ~e modified in cha~el 0 or 16.
2Ç~ ncl O, ala~ms on li~e 432 are inserted (for error chec}~
i~g) and t~e NAC~; cha~el info~mation is ~s~rt~d ~ ch~-nel-16, wh~n re~i~ed, Dy logic 4340 The tra~smit eont:rol R~ 426 c:on~a:L~s t:he statu~ of e~ch out:g~ing channel. The transmit control logic 424 c:oclrdina~es the read and w~ite opera~ioa~ tc~ t~e dat. R~ 422 and transmi~ cont::cl R~
426, i~ree chann~l sear~:h 414, and outDu~ reg~.ster 430 load~

The est~ is~i~g of c:onr~ections t~:rough ~e netwclr}-.
between te~ni~ will now ~e descri:~ed.
As afor~mell~ioned, 'che 16-pork switching elemen~s pro~
Yide ~oth time ~nd space switching ~unctions for all ~an5-mission pa~h~ I~ror~ati~n arri~ing on the incoming path at a~y port f~r an~ channel can be transferred by the 16-port switching eleme~t to the outgoing pa~h o~ ~ny port, this gi~ing space switching, and any channel on that path, this gi~ing time switching. All speech and data (SP~T.~) transmission t~cough ~he ne~w~r.~ is the resul~ o~ i~di~idual ports in t~e =ulti-port switching elements implementi3g ~3~2~3~

Alan ;Jam~3s ~awrence, et~ alO

~19--trarL~:Eormation o~ input channel. (one out of 512) to output ch~Lel (one ou~ of 5123, as predeten~ ed by - path se~-up procedures, with thirty-t:wo channel woxds per frame OXL any giYe~L t:ransmis;sion pa~. Figure 10 illust:~ates one ex~plary chan~Lel word ~o~Qat which is applicable to all ~af chanxLel.s 1 through. 15 and 17 th~ou~h 31, ?il oi~ which c~anrL~!ls are 9P~r~ ch~n2Lel~ .
l!h~ ch~nel word for~ats for c~ L~l O (~ai~te~La~Lce axLd sy~lchronizatio~L) a~Ld chan~lel 16 ~sp~c~al purpose Ia con~ol, ~ACR, ~c. ~ are illu~ated by Figure 11.
T~e SPATa cha~n~ls ca~ ~e us d for both digital speech a~d ~terproc cor d~ta transmission. Whe~
speech is ~i~ LLtt~d~ 14 ~its per c~a~nei word are a~ailable for the e~coded PC~ sample ~a 2-Di~S a~
available fox network protocol selec:tion. ~hen use~
:or path Ret up cont.~ol, 13 bi~s/channel word are available for the aat a~d 3-~ts or protocol selec~ion.
~he channe~ wo~d fo~mat er~ables switc}liD.g t~ ughout - ~:he net:wor3c, which ~volve~3 con~ectio~ through a plurali~
2~ of the 16-port switchi~g- eleme~t~. These ccs~nections are.~urlidi;2:actional. For bidirectional co~ec~io~ i two un~ directio~al con~e~tions are re~{uired.
Reerr~g now to ~igure 10, Px~plary cha~nel wor~
formats are illustrat d for all oha~L~els excep~. chana~ls O arid 16. ~igure 11 illustrates exesnplary c:ha~s~el ward formats ~or channel 16~, Figures 10 ta~ through 10 (d) illustrate data ~i~ld fo~mats for SE~EC~ ROG~5'E, ESC~ , SPA~ an~ ID~:~CILEA~ respee~ 31y. Figu::eq 11 (a) th~ough 11 ~e) illu trate 5ET.~C~, ES~PE, ~3:0I,D and ID~C~E~R
3CI~ for chan~el 16 and the alarm format for cha~slel 0. The channel words i~ channel O also contain the ~rame s~nc~ron-ization bit pat~ern (6 ~its) between adj~ining l~-port switchins elements.
s~æ T command sets up a connes:tion through a swit::h-3S ing el~Gent.
I~TE~RO~ command is usPd a~t~r ~he path is 52t Up to de~ermine which port was chosen i~ the switching elemen~
for th t path.

~3L3~

Alan Jame~ Lawrence, et. al.
ç
3 ~
--2 C~ ~
~;CaPE command i~ us ed or~ce a path has been set up to J
transfer i~fo~mation between t~,70 terminal clusters a~d to -distinguish such information from digiti~ed speech samples.
~PATA format is used to tr~s~er speech or data in-o~Qa~ion be~we~n arly two te~ninals . -ID~E/ChEAR command fol:mat :indicate~ that the cha.~el iq clear. ` ¦
Po~ char~l 16 " the S T ~CT, E5cApE~ d IDIæ/CI~R
cpmma~ds are si~ilar to those described with re~eron~e to Figu~e lO, except as ther~ is nD SPATA made, the :~TERRC~ c~ is not required and since c:harmel 16 c:a~ie~ the N~ char:~el, the types o~ SE~CTS are r~- .
stricted. the ~iOI,D co~and ma~tain3 a char~nel 16 connec~i~n ~.
onca it has been set up by SE~:CT commands. Cha~nel Q is r~3e~ed ~or maint~nance and diagnostics ~f ~he n~w~r}c~
Referr~g now to Figure 12, which illustrates a tarminal subu~t 1~ which conta:~ns it po:~io~ o~ the ac~::e-~s ~wit~hing stage, accass sw~ tches 42 and 44, as descri~ed with refOEence to Pigure l, a~d the group switch 10, which c~ntains three stages o~ s~itchins. ~ndi~idual pla~es in ~e group switch and i~dividual switc~i~g el~e~t~ ~
wi~hin each s~age are not showll-, for s~m~lici~.y o~ desç:rip~ - ;
tion .
A con~ectio~ ug~ t~e swit~h~g networ~c is set 1 up from one te~i2lal-in~erface, suc~ a 690 to ~o~er J
ten~inal ~terf~ce sucEl as 19~; o:r ~rom a B-~rocessor such as 183 to aIlothe~ proc~sso:c such as A-processor 198 ass~ciate~ wi~ t~rmi~al in~er~ace i9~ ~y a series of SE~2CT c~mma~d~, i.e.~ chan~el word format~ ~ich are ins~rted into t~e PC~ fr~med ~it s~ream he~ ~ the orig-i~ating ter~ln.l interface (or processor~ and the acce~s switch in successiYe frames in t~e c~annal alloc~t~.d to the connection~ One SE~C~ c~mm~nd is required or each path connection thr~ugh each ~tage ~f swi~chi~g.
A connection throug~ the swi~ching networ~ is made ', by a se~uential series of connec~ons through individual sw~tching stages~ The conne~tion proceeds as an ~rderly ~.

~ .

113~2~3~ .
-,?1-progression from lower numberecl stageC; to higher numbercd stages by "inletto outlet" connections ac.-oss switching elements until a predetermined "ref-lection stage" is reached. Re~lection is the connection between inlet ports ln the switching element and enables connection to be made wi-thout penetrat-ing the switching network more than ls required to complete the desired con-nection. For a detailed description of the concep-t of reflection in a swit-ching network, reference is made to Canadian Patent number 1,101,531.
Across the switching element in the re~lection stage an "inlet to inlet" connection is made, followed b~ an orderl~ progression from higher numbered stages to lower numbered stages b~ "outlet to inlet" connections across switching elements.
The predetermination of the "reflection stage" is made with respect to a unique network address of the required terminal interface such as 190.
These rules are generalized as ~ollows:
If the terminating terminal interface is in the same terminal sub-unit, reflection is made to occur at the access switch.

.
If the terminating terminal interface is in the same terminal unit, reflection is made to occur at stage 1.
If the terminating terminal interface is in the same group of ter-minal units, reflection is made to occur at stage 2.
For all other cases, reflection is made to occur at stage 3.
Referring again to Figures 1 and 4, which illustrate a unique fea-ture of the network architecture, a terminal unit, such as terminal unit 12, which has 8 bidirectional transmission links to each group switch plane such ~as the illustrated plane 0 of Figure 4, these transmission links terminate on one switching-element in each plane. This switching element can be seen to have a unique address when viewed from the center (i.e. -third stage) of the ''~

- : , , :: :: - : . . . ~ . :

~`.32~3~

.

Alan ~ames Lawrence i et. al .

gro~p switch 10. Thu , i~or example, with reference to Figu~:e 4, the switch~g elemerlt 108 when viQwed ~rom a~y switc~ing el~ t in the third ~age is acc~ssible ~ia iIllet O fr stage 3 ~ollowed by ~let 0 ~rom stase 2~ This. co~Lstructs the addxess o the te~:minal ur~it, i . e ., i~ i5 ~7i~e~1 the add~ess TU ( O, 0 ) u Fu~:the~ore, a te~i~al subunit i~ uniquely ad~ces~ed wi~h~ a ter~in-al unit with respect to t~ie seco~d 8t2g~ et~r .i-wi~h ~efer~ce to Fi~r~ 1, te~:minal ~ubunit 18 ~an b~
see~ as TS~ ( ~ ) o~ T~ ~ O, O ) a~ it is uni~Euely ad~ressed from inlet~ 0 and 4 of ~irst ~tage swit~h tO, 0) . Similar-ly, eac~ te~inal i~ter:faca i~ each te~:minal cluster is ~uely ~dd~essed v~a its i~l t address on the access . swit~h. Thu~ address o a te~ l inter~ace ~ such as ~t~rface 190 ~ Figure 12 as see~ by any other te~mi~
al ~t~rface su~:h as 690 in tar~nal u~it 16, for ex3mpl~
is inaependent of . w}~ich ~witchi~g eleme~t in stage 1:hrea is ~e "r~flec:tion poi~ n.
Thi allow~ the pat}i set up ~t~olI~ng A-proc~ssor, 698, to la~ch ~e i~ollowing sequence of 5É~ ~CT ~ommland~
~to th~ ~twor3~ i~ order to ~e~ up a con~ecl:io~ to the t~al i~t~r:acs 190 whose networ3c ad~r@ss is, ~or example, (a,}:~,c,d) ~ .
~}~AME 1. SE~:C:T, ~ E~ PORT, A.~Y C~N~:
25. . T~i~; set~ a SPAT~ conrl~ction through ~he acc~s~
swit:ch to a group witc~ plane.
E~ 2 . S~ECI~ t l~Y PORT, ANY C~:
Thia set~ a ~onnectio~ through ~tage 1 o:E the ch~sen pla~e.
FRA~OE 3. S~XCT, A~ PORT, A~ C~EI,: .
This sets a co~nec:tion through stage 2 of the chose~ plane.
FRA~ 4 . S~CT PORT t a ~ ANY C~E~:
This reflP-cts the connec1:ion throug~ stage 3 to stage 2.
FR~2OE 5. S~ CT P~RT tb) A~ C}IA~
~his sets a connectiQn bac}~ through s~age 2. .

3~

iP~lan Jame~s La.wxenc~, et. al,.
L-l F~ME 6 . SEI.}3CT PORT ( c ) ANY C~EL:
Thi5 sets a co~ection ba ::k through stag~e 1 ~R~ 7 . S~5~2CT PORT ~ d) AN~ OEEANN~:.:
Thi~ sets a co~ tior~ bac~ through t~ae acc~ss switc:h to t~al i~te~:ace (a,b,c,d).
This ~etwor~ permit~ switching f~ward to any r~fl~ction poi;nt in 'che stage d~ mined as the re~lec~io~
tage~ d theQ back th~ough the natwor}~ with a co3ssta~t adds~es which is indeperldent oi~ the rei~lec~io~ swikching element i~ tha~ ~ta~
The se~uence of S~ECT~ can be used by any terminal ~terfac~ to et up a co~Lnection to TI ~a,b,e,d) and t:h~
''~st free h~el" selecti.on mechanism desc::ibed aba~re en~;ures minim~n. ~ans~is~3ion delay on the ~el~cted path~
Where. r~1ectio~ is possibl at an earlier switching ~tage as de~ de~ from the rule gi~ren abc~ve, a subset o the a~ov~ i sequer~ca ca~ be used. Thus, as shown in Eigl~e 12, processor, 183, w~ich is ~e ~me te~inal s~b~t 18 as i3 tex~al int~r~ac~ l90, need la~ch only the followi~g subset o the above se~ence.
F~A~13 1. SE~;EC:T. PO~ (d) ~Y CE~.
The proc ss~g ~unct~o~s pe~ ormed ~S~ f~e A, a:r~d B
p ocess~rs ar~ dep~nd~t upon t~e partie~lar computer pr~grams utilize~; how~ver, exemplz~ry processing funct~ons are~ ~al~ =oL, wh~c~ p~ovide~ t~e featu::es for e ch cla~ of sertr;tce for su~scr~ e~ or tr~nk li~e~3;
on~rol ~ w~ich se~era~es ~ al~ to c:all te~ als unde~
con~:ol of t}l~ te~inal c~n~ol p~ocessing~ and deco~es and ~n~e:rpset~ sequence~ of ~i:gslals ana dig~ts whic}l ara 30 . coupled as t~lepE~one eYents to t~e: te~in~l con~rol pro-ces~or for actsor~ r~-hl~b~, which ~ets up, ma~n~
ta;~ns, and tears down pa~s t~;ru ~he ne~:wor.~. as dtrse~ed ~y the term; nal control and signalling cont:^ol functions;
~ata ba:se cont~ol, which pero~ms all operat~o~ on the physical data ~ase and allows all other proc:e sas :to oper~
a~e independexltly of a parti:c~lar organ~zation tE~e data ~asa; and hardware control ~ ~icE~ comprehends process~s ~or ~3'~3~

iAlan ~ame Lawrenc:e ~ et, al .
l~ L

the contxol of the hardware actllally ir;lterfacing su~ascriber lines or ~l~lk5, and or the te~e~ninal urlits a}ld switchirlg elements . An exemplary dis tribution of processing functions is the allocation of b~are c~t::ol for up to 60 line te~m:Lnals or 30 trur~k termi~als at each A microprocessor aIld the bther functions }:eing performe~l by t:he :B m;lcroproces~
qor . or 50m8 ol:her nu~ er of te:Emina:Ls. OX oou~se, ~witch trol e:ould alters~ati~7ely be peri~o~:med by the A a~ic:rc)pro ce~sor.
Ref err~g ~ow to Fig~:e 13, ti:rQing diagra~s illu trati~re of t}le operatio~ o a switching element 300 are shown.
Figure 13 (a) show~ the cuxrent bu~ 302 ti~e slot numbe~
~a ch~?. mImb~, wi~ 16 time slots con~tituting one ch~el; wit~ the time ~lot rlu$bess being writte~ in he.xi-~ec~ otation, and wit~ c~annels 0, 1 and eight time slots o~ chan~el i~wo illustratQd. . .
Figu:~e 13 ~b~ is the 4 . 096 ~bf ~ bus c:loc3c.
Figure 13 ~c) illustrates the frama ~ynchro~ization which is a po:~ sy~chroni~ation com~d, which occu:s:s o~
}:us 302 during channel 31, ~ slot E.
Figur~s 13 (d) t:~u 13 ~h) illustrat~ for pClrt5 0, 1,2, 14 asld 15 o~ switching element 300 the ti~ne en~elopes o~
the bus 3 02 ~r n~f er actior~s of ~eir respecti~s port~; O
Ports 3 thru 13 are not illus~a~e~, but are operatis~ally iden~ical ~ 3~ach o~ ~he bu~ transf er enYelope 501, 502, 503 , 504 and 505 for por~s 0 , 1 , 2,14 a~d 15 respec~ ely are time ~ul~iplex~d~ Each e~elope inclu~es four t~e slots P,D,W,R, duri~g whic~, specific: ac~io~s occur on sp~cific lines o the Tr)~ bu~ ~02 during specific time~
such that only one po~ is transmit~ir.g info~ation an any ~ne line o~ TDM bus 302 at any ir~staDt in time. The .
pr2ci2e time of -Rtariing of any ~raDsf~r en~elope is deter-mined by a uT~ique port address code. .
Ref rring now to :E igure 14, 14 ~a) shows the system 35~ cloc~c illus~rat d by ~igure 1~ ~b) . Flg~re~ 14 ~b) thru 14 ~e) are expansions of ~.e time slot P,D,W a~d R of typical bus transf er en~elopes 501, 502, 50 3, 5 0 4 ~r 5 0 5 .
~' }

3~3~

. --~5--Bus 302 is comprised of th:irty-six urlidirec~ienal l~e~ :Eor performi~g bus interco~ atic~ ctions between all six~ee~ po~t~, a~ i:Llustra~ed ~y Figuxe 15.
The ~ignals tha~ the rec:eive loqic 304 o~ the module present~ to t}~e bu~ 302 a~e DATA ~16-bit~ each on a sep-arate line7 DESTI~TTO~ POR~ ~DR~:SS ( 4-bits eac~ on a separa~e li~e), DESTl~aTIO~ C~N~ ADD}tESS (~ its each '~
on a separate line), DATA VA:;ID tl-bi~), S~CT ~1-bit3, and MODE ~ it). i!he signals t}lat are xec~i~ed ~rom the lû bu 302 a~e S~ECTE~ ~ (5 ~it~ each o~ a sepæate li.ne), ACg~!tON~EDÇ;E [l~ ), Rnd MODU~E BUSY ~l-bit).
Depending on the FIFO. DAT~ word ~rom ~e FIFO ~u~fer 4a2 and the content oi~ the RECE~V~ CONTRO~ R~5 404 addressed by th~ channel ~u~be:: output oi~ FI~O 402 ~rarious signals T5 a::e presented to the bu~i 302 ana accepted rxo~ itf ar~d various wo::ds writ~en ~to t~e POR~, C~ ar~d ~
CO~ITR.O~ 5 of the recei~e logic 304 for the ena~led port. T~e SET ~: AS:TIVI~ hI~E o~ bu. 302 ~s ~ sp~cial fu~:ion l~e 'co o~erride the occurre~ce s:~ a p:: de~er~in~d 2Q fu~
Du:r~g time 510t P s~m on ~igur~ 14 ~b~ as a) ,the eurxently enabled ~eceiv~ logic 304 tra:nsmit to bus 302 the desti~a~ion transm:Lt logic port number and also pUt.5 t appropriate sig~als on bu li~es ~A~ V~ID, SEIæCT, L~qODE
2S and MOD~: BU5Y. O3~ the risi~g edge o the cl~ç~ shown on .
Figure 14 (a) a~ ,all tr~t logics ~û6 of all s~Yte~
po~ 5 pUt~ ate o~ ~o~e men~ion~d bus line~ to regis~ers a~sociated withdecode por~ ~umber circuit 420 and tras~s~it con~ol 424. Durins t~me 5101: D, shown 3~ on Fig~a 14~c) as ~ ,the receiYe logic of the enabled por~: puts info:rmation on the DATA Lr~S and DESTI~ATION ~, C~ ADD}~:SS L~ES. On the nOEt rising e~g~ o the cloc}e, shown o:n Figure 14 (a) 2S ~ , this in orma~ion is tra:~sferred i~to buf~e:r register~ associated with ~e ~5 data R~*l 422. During time slot W, shown on ~igure 1~ (d) as (5), if the port num~er represented by .he 4~ s on 3~

- Alan Jame~; ~awrence, etO al.
--2 ~ .
on the DEsTI~aTIoN PORT ADDRESS L~ES which occurred duri~g tim~ slot P matches.the port identifica~ion code, of a particular p~rt, whic~ code i5 ~i~ique for each port, an ope~a~ion- occ~:q at ~h~ port's transmi~: logicO The operati~n may be a write into th~ da~a ~1 422 o ~a~ pork or a -~espons~ to a S:E:IECT commaIld. Also du:ring time ~lot ~, a prop~: ~alue for ~h~ s~lected channel numbe~ i~ coupled ~rom first free chax~nel ~ea:rch circui~ 414 o~o the SE~ECl~D ;
cE~ ~ER 1INES, i~ appropriate, and a ~ralu~ ~eith~r logic 1 or ~ for an ack~owledge signa~ is evaluated. A
.N~C~; i5 Si:~laply ~e lac~ of a~ ac~cnowledg~nt ~ignal.
During tlme slot R, shown on Fi~ ~4 (e~ as (6), ~e ~es- .
ti3latio~ pc~rt transmi~ logic: places a respons~ on the S~ECT~D ca~ nu~nber a~d acknowledge~ lines. The e~abled re~eiv~ lo~ic trarL~ersthe stata of these line~ o a regi.~ter as~ociat~d with recei~e c~ rol 406 on the ~2ex~ .
C~OC~!t leadi~g edge sh~own a-~ (7) - ~y Fig~re 1~ ~a), arld some .later ~e, ~hown a.~ (8) by Figure 14~e3, update~ its own - p~rt cha~nel aIld receive corltrol RA~s 410! 408 arl~ 406 2 0 respecti~ely . -~a~x channe? ~ers recai~ed by a ~AC}; recsi~rer 416 at ~he r~ceiYe logic of a parti::ulax por~ will ca~se a reject bit to be set ~ the trar~sI;LLt logic o~ the same port at the a~ ess speci~ied ~y the rec~ive~ NAC~; channel ~u~er, ~ a NAC~; in chan:nel 16 ~ay }~e ael:od~l z~s "NACX channel 7" for example. ~h~ eæt t~ne the re~ei~e logic which has 52t-Up a path ~to cha~nel 7 attempts to write into channel 7, it will get r~o ac~owledge signal a~d will de~;~ gna~
the channel wi.th the path irlto chanr~el 7 as bei~g NAC~ ' ed.
rhe NAC~C se~rch circuit 418 will the~ outpul e ~:he num~er of ~he ~Cg ' ed chanr~el from it~ t:ransmit logic, in c~ l .
16. , Delay th~ the ne1:wor}~ is automatically minimized }:y the use of the. first fre~ channel search techni~ue. The first fr e channel s arch circllit 414 corltirluously looks at the "busy bit" o the transmit control RA~ 424 for id~e char.nels with the lowest channel numb~ high~ than the ~3'~

Alan James ~awrenc~, et. al.

-27~
current output channel num~er coupl~d to the serial data on PC~ line 310.
While the present invention has ~een descri~ed ~n connection with a preferred ~odlment there~, it is S to be understood that additional e~cdiments, mod~ication-~, ~
a~d application~ w~ic~ will ~ec:~me o~vious to those ~killea i~ ~he art ~r~ included w~tbi~ t~e spirtt ~nd ~cope o the ~ventio~ as ~et for~h by the clai~ appended h~r~to.

Date: March 13, 1978 ,'.

_~ .

Claims (22)

THE EMBODIMENTS OF THE INVENTION IS WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A distributed control digital communication system for selectively interconnecting a plurality of groups of ter-minals through a digital switching network having an access switching stage and one or more other switching stages, com-prising: a first group of data processing means for providing a first set of pooled processing functions for said groups of terminals, each of said processing means being associated with one of said groups of terminals; a second group of data proces-sing means for providing a second set of pooled processing functions for one or more of said groups of terminals such that said second processing functions are provided independently of the processing functions provided by said first group of processing means; and digital switching network means coupled to said first and second groups of processing means by one or more multiplexed transmission paths over which data and at least selection control signals are transmitted in frames con-taining a plurality of channels of said data, such that said path selection control signals establish communication over said multiplexed transmission paths thru said digital switch-ing network means between said first and second groups of data processing means with said path selection control signals preceding said data on said multiplexed transmission paths in the same channels and selectively interconnect said terminals over transmission paths thru said switching network in channels designated by said path selection control signals.

2. A distributed control system in accordance with claim 1 wherein said multiplexed transmission paths are bidirection-al transmission links.

3. A distributed control system in accordance with claim 1 wherein said data and control signals are transmitted over said transmission paths bit-asynchronously.

4. A distributed control digital communication system in accordance with claim 1 further comprising a plurality of terminal unit means, each of said terminal unit means having coupled thereto a plurality of said groups of terminals and including means for multiplexing data from said terminals onto said transmission links together with said path selection con-trol signals.

5. A distributed control digital communication system in accordance with claim 1 wherein each data processing means of the first group of data processing means is coupled to at least two access switching means having said multiplexed transmission paths coupled to inputs thereof and having outputs coupled therefrom to said multiplexed transmission paths upon which said data between said terminals and said path selection control signals are multiplexed to said digital switching network.

6. A distributed control digital communication system in accordance with claim 1 wherein each data processing means of the second group of data processing means is coupled to one or more access switching means having said multiplexed trans-mission paths coupled to inputs thereof and has outputs coupled therefrom to said mulitplexed transmission paths upon which said data is coupled between each data processing means of said second group of data processing means and said switching network.

7. A distributed control digital communication system in accordance with claim 1 wherein said data comprises frames of digitally encoded PCM speech samples in a plurality of channels from telephone lines circuits.

8. A distributed control digital communication system in accordance with claim 1 wherein said data comprises frames of digitally encoded PCM speech samples in a plurality of chan-nels from telephone trunk circuits.

9. A distributed control system in accordance with claim 5 wherein each of said data processing means of said second group provides a set of pooled processing functions accessible over said multiplexed transmission paths by any of the data processing means of the first group.

10, A distributed control digital communication system in accordance with claim 1 wherein said digital switching network comprises an expandable group switching elements, each of said elements having two or more inlets and two or more outlets and being adapted to selectively reflect traffic enter-ing any inlet of said switching element back to any other inlet of said switching element and for connecting the outlets of said switching element to the inlets of other switching stages.

11. A distributed control digital communication system in accordance with claim 1 wherein the data processing means of said first and second groups of data processing means are microcomputers.

12. A distributed control digital communication system in accordance with claim 1 wherein said switching stages of said switching network are comprised of switching elements operable as either single sided switching elements or multisided switching elements within said switching network.

13. A distributed control digital communication system in accordance with claim 5 wherein each data processing means of said first group of data processing means is adapted to pro-vide as processing functions at least path set up and terminal device supervision for its respective group of terminals and wherein each of said second group of data processing means is adapted to provide as a processing function at least call control for its respective group of terminals.

14. A distributed control digital communication system in accordance with claim 13 wherein each processing means of said second group of processing means is further adapted to provide call translation as a processing function for its respective group of terminals.

15. A distributed control of digital communication system comprising a plurality of terminal units for interfacing a plurality of PCM communication terminals carrying digitized speech in frames containing a plurality of channels of said digitized speech to a common communication path upon which said frames and in-channel path selection control signals are multiplexed, and comprising: means for deriving at least digi-tal path selection control signals for each PCM terminal inter-faced thereto; a digital switching network coupled to said communications path for bit asynchronously interconnecting said PCM terminals through paths established thru said switch-ing network in response to said in-channel path selection control signals, and; means at each of said terminal units for selectively multiplexing said digitized speech and said in-channel path selection control signals on said common com-munications path such that said digital path selection control signals precede said digitized speech in channels designated by said path selection control signals on said common communication path.

16. A distributed control digital communication system in accordance with claim 15 wherein said switching network is comprised of a multistage group switch.

17. A distributed control digital communication system in accordance with claim 15 wherein each of said means for deriving said path selection control signals for a group of said PCM terminals comprises one processor or a group of processors.

18. A distributed control digital communication system in accordance with claim 15 wherein said PCM terminals each are associated with a telephone subscriber line.

19. A distributed control communication system in accordance with claim 15 wherein said PCM terminals each are associated with a telephone trunk line.

20. A distributed control digital communication system in accordance with claim 17 further comprising: a second group of processors, each of said processors of said second group of processors providing other processing functions for a plurality of said groups of PCM terminals; and means for coupling interprocessor control signals from one processor of a group of processors to any other processor through said paths established thru said switching network by said path selection control signals to provide communication therebetween.

21. A distributed control digital communication system in accordance with claim 19 wherein at least one of the processing furnctions provided by each of the processors of said second group of processors includes call translation.

22. A method of communication between a plurality of terminals having data in frames containing a plurality of channels of said data coupled thereto, wherein a plurality of groups of said terminals are selectively interconnected thru a digital switching network in response to in-channel path selection commands, comprising the steps of: deriving a first set of processing functions including said in-channel path selection commands for said groups of terminals, and processing functions being derived by a first plurality of processors in a first group of said processors; deriving a second set of processing functions by a second plurality of processors in a second group of processors for one or more of said groups of terminals such that said second set of processing functions are derived independently of the first set of processing functions; and interconnecting said first and second pluralities of processors thru a digital switching network coupled to the first and second pluralities of processors by one or more multiplexed bidirectional transmission links over which data and at least path selection control signals are bit-asynchron-ously transmitted to provide interconnection between said first and second pluralities of processors in channels designated by said commands and selective interconnection of said data in said channels between said terminals over common transmission paths thru said switching network established by said path selection control signals.