CA1080807A - Distortion adapter receiver having intersymbol interference correction - Google Patents
Distortion adapter receiver having intersymbol interference correctionInfo
- Publication number
- CA1080807A CA1080807A CA267,422A CA267422A CA1080807A CA 1080807 A CA1080807 A CA 1080807A CA 267422 A CA267422 A CA 267422A CA 1080807 A CA1080807 A CA 1080807A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- producing
- output
- correcting
- representing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
- H04L27/2277—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using remodulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/005—Control of transmission; Equalising
Abstract
DISTORTION ADAPTER RECEIVER
HAVING INTERSYMBOL INTERFERENCE CORRECTION
Abstract A differentially adaptive receiver system in which correction is provided for degradation of performance caused by overlapping of adjacent data pulses. A reference signal is produced having the same complex envelope as the received signals and having a constant phase state independent of changes of phase state of the received signals. The received signals are detected against the reference signal as in an ideal matched filter receiver. The detected signals are integrated by an integrate and dump filter over the duration of the pulse period. A correction signal representing the amount of overlap between overlapping adjacent pulses is summed with the output of the integrated dump filter. The sum of the correction signal and integrate and dump filter output is sampled and held by sample and hold circuit to produce the digital data output.
The invention herein described was made in the course of or under a contract or subcontract thereunder with the Department of Defense.
HAVING INTERSYMBOL INTERFERENCE CORRECTION
Abstract A differentially adaptive receiver system in which correction is provided for degradation of performance caused by overlapping of adjacent data pulses. A reference signal is produced having the same complex envelope as the received signals and having a constant phase state independent of changes of phase state of the received signals. The received signals are detected against the reference signal as in an ideal matched filter receiver. The detected signals are integrated by an integrate and dump filter over the duration of the pulse period. A correction signal representing the amount of overlap between overlapping adjacent pulses is summed with the output of the integrated dump filter. The sum of the correction signal and integrate and dump filter output is sampled and held by sample and hold circuit to produce the digital data output.
The invention herein described was made in the course of or under a contract or subcontract thereunder with the Department of Defense.
Description
1~8~ 7 T~e inyention relates ~o receiyexs used for signals haying ~ul~i-path corrupted phase properties and ~ith d:istortion caused by oYerlapping of adjacent data pulses.
There has previously been described a communications system for improved reception of signals which lYere transmitted through co~nunications channels having multipath distortion characteristics, Within that system a reference signal is produced in the receiver which has the same complex envelope as that of the received signals over a number of received pulses.
The reference is used in a coherent matched filter-type detector employing decision feedback to permit coherent detection of the signals without the use of channelizing filters for systems employing multiple phase state digital signal modulation. Although the referenced system was capable of operating sYith signals from a plurality of channels, it ~YaS required that there be no ~ -appreciable oYerlap between adjacent pulses within any one channel in order to produce a valid determination of the phase state of pulses within any channel, Intersymbol interference caused by overlapping of adjacent pulses in the previously disclosed system and ln other such communications systems reduced the signal levels within the receiver for some pulses and increased the level for others. For pulses in which the signal .., B ~ ~
, '`A~;
,~` :
~ ~ 8 ~
amplitude was lowered, the amplitude was often insufficient to permit a valid determination of the phase state of that pulse.
Consequently, the system had to be operated with sufficient time spacing between adjacent bits that no overlapping could occur for any possible channel conditions. Hence, the data rate for any one channel was appreciably lowered due to the non-overlapping requirement.
B
,~
. . .
-Accordingl~, it is an object of the pl~esent inyention to provide a communications receiveT system for digital data in which the effects of intersymbol interference are su~stantially decreased.
It is also an objec~ of the preslsnt invention to provide a differ~
entially adaptive communications system which may be operated at a higher data rate than previous s~stems in the prPsence of intersymbol interference~
Moreover, it is an object of the present invention to proYide a differentially adaptive communications system haYing a correction signal producing circuit for correcting recei~ed signals for intersymbol interference.
10These, as well as other objects of the invention, are met by provid-ing a differentially adaptive receiYer which is self~adaptive to multipath distortion having means for compensating for intersymbol interference. With-in the present description of the inYention and accampanying claims, the terms "differentially adaptive receiver" and "receiYer which is self~adaptive to multipath distortion" and similar terms are defined as a recei~er in ac-cordance with the above-described communications system having means for producing a reference signal which has the same complex envelope as that of received signals over a number of received pulses and in which the reference signal is used in a coherent matched filter detector employing decision feedback. The interference compensating means may comprise means for deter-mining the presence of the intersy~bol interference and means for correcting information bearing s~gnals within the receiYer in response to the inter~ ~`
symbol interference dete~mining means. The means for determining the presence of intersy~bol inter~erence mar produce a signal in response to the oYerlap bet~een adjacent syn~ls. The means ~or determining the presence of int0r~
sym~ol interference mc~r also comprise means for comparing the ~alue of a present bit :. . . : :
- ' ' ' ''~ ` ' ~ 8~
decision with the value of the integral of the received signal.
The correcting means may further operate in response to the comparing means to provide a signal for correcting the magnitude of the integrated signal to correspond to the correct bit decision state.
The invention may also be practiced by providing a receiver having means for producing a signal representing the integral of detected received signals wherein the received signals comprise a series or train of pulses each of the pulses being encoded with one of a predetermined number of phase states, means for producing - an output signal which is a dc voltage representative of the dis-crete states of the pulses and having a separate voltage level corresponding to each of the possible states, means for producing an error signal corresponding to the difference between the out-put signal and the integrated received signal, and means for producing a correcting signal in response to the error signal wherein the correcting signal and integrated signal are summed prior to being sampled to produce the output signal. The output signal producing means preferably comprises means for producing one or more samples of the signal representing the integral and means for maintaining or holding the value of the integral of the samples constant over a predetermined time period determined by external synchronization means. The correcting signal pro-ducing means in preferred embodiments includes means for multi-plying the error signal by the output or sampled signal, means for averaging the product produced by the multiplying means, and multiplying means for multiplying the averaged signal produced by the multiplying means by the output signal. The correcting signal is produced so as to have a magnitude which is proportional to the amount of overlap of adjacent ones of the pulses.
,~ ~
: .
~ ~ V ~ 7 The invention also encompasses a combination of means for receiving multipath distorted phase shift keyed signals, and means for producing a reference signal which has substantially the same modulation envelope as the received signals over a short time period and also having a phase state independent of the changes of phase state in the received signals which is preferably equal to a zero phase shift state or a predetermined one of the phase states but invariant as the phase state changes among pulses, means for detecting the phase state of the received signals by comparing the phase state of the received signals with the phase state of the reference signal, means for integrating the detected signal which also includes means for resetting the integrating means to a zero value at the conclusion of a bit time period, means for summing the integrated detected signal with a correction signal so as to produce a corrected detected signal, means for sampling the sum produced by the summing means and for producing an output signal in response to the sampled signal which represents the phase state of the received signals by a dc voltage having a value which corresponds to each of the possible phase states, means for producing a signal representing the dif-ference between the sum produced by the summing means and the output signal, means such as a shift register for storing a signal representing the phase state of the immediately previously produced pulse which may be a binary digit, first multiplying means for multiplying the signal repr$senting the difference by the signal stored in the storing means, means for producing a signal representing the average signal over a pulse time period of the difference or error signal over at least a portion of a pulse period, and second multiplying means for multiplying the signal representing the average by the same stored signal ~' 5 ~8~B~
within the storing means in which the correcting signal is produced as the product generated or produced by the second multiplying means. The correcting signal is produced as the output of the second multiplying means having a magntiude and polarity such as to correct the output of the integrator for error caused by overlap between adjacent pulses. The magnitude and polarity of the correcting signal are in proportion to the amount or total time period multiplied by magnitude of adjacent ones of the pulses. The sampling means preferably samples the sum produced by the summing means a plurality of times during a pulse processing or time period at predetermined intervals until the correction signal is substantially zero at which time the present bit decision is substantially uncorrelated with the previous bit and at which time the error is reduced to the minimum level in the least mean square sense. The phase state of the re-ceived signal may be a binary phase shift key having two predeter-mined values, quarternary phase shift keying having four predeter-mined values, or of any other type of phase shift keying modula-tion.
"~ ~, ~ - ,r-....
, Accorcling to a broad aspect of the present invention, there is provided a differentially adaptive receiver comprising: means for receiving multipath distorted phase shift keyed pulse signals; means for deriving a reference signal having substantially the same envelope as pulses of received signals an(l a phase state independent of changes of phase state in said received signals; means for detecting the phase state of said received signal pulses, said detecting means comprising means for comparing the phase state of said received signals with the phase state of said reference signal; and means for compensating said received signals for intersymbol interference.
~ ccording to another aspect of the present invention, there is provided a receiver comprising in combination: means for producing a signal representing the integral of detected received s~gnals, said received signals comprising a series of pulses, each of said pulses representing a discrete digital state; means for producing an output signal representing the discrete digital states of said received signals; means for producing an error signal representing the difference between said output signal and said signal repre-senting said integral; means for producing a correcting signal in response to said error signal; and means for summing said signal representing the integral and said correcting signal.
According to another aspect of the present invention, there is provided the method comprising the steps of: producing a signal represent-ing the integral of detected received signals, said received signals com-prising a series of pulses, each of said pulses representing a discrete digital state; producing an output signal representing the discrete digital states of said received signals; producing an error signal representing the difference between said output signal and said signal representing said integral of detected received signals; and producing a correcting signal in response to said error signal.
1~8~8~)~
Brief Description of the Drawings FIGURE 1 is a schematic block diagram showing a decision adaptive communication receiver system incorporating the present invention;
FIGURES 2 and 3 are waveorms o signals within the system useful in attaining an understanding of the invention; and FIGURE 4 is a block schematic diagram of a portion of a decision adaptive receiver system employing quarternary phase shift keying in which the present invention is used to advantage.
.
~ 8V ~
Description of the Preferred Embodiments In FIG. 1 is shown a schematic block diagram of an embodi-ment of the invention in a binary phase shift keying receiver system. The system shown in FIG. 1 employs the same basic receiver circuit as the embodiment of the invention shown in FIG. 2 of the referenced patent where like named elements per-form a similar function. The input signal from the IF filter is coupled both to multiplier 22 and to delay circuit 12 which produces a delay of one baud or bit period time. The signal from the IF filter output is compared with a reference signal by multiplication or detection by multiplier 22.
The reference signal is produced in the manner described in the referenced patent. The incoming IF signal is delayed by delay circuit 12 and multiplied by the digital output of the previous bit which may be represented as +l or -1. As the signal output from delay circuit 12 arrives at inverse modulator 14 at the same time as the cGrresponding digital output repre-senting the +l or -1 state, the output of inverse modulator 14 is a signal having the same complex envelope as the incoming signals but with a constant phase state.
The output of inverse modulator 14 is added with the sig-nal circulating in the loop comprising summer 17, delay line 18, and operational amplifier 16. The signal circulating within that loop is made up as a sum of a number of previous inputs from inverse modulator 14 all having substantially the same complex envelope and phase state. Since noise within a single pulse input from inverse modulator 14 is essentially a random phenomenon, the composite reference signal formed from a summa-tion of a number of pulses produced from inverse modulator 14 has a greatly reduced signal-to-noise ratio than a single input . .
: ~ , .. .. ... .
lO~VB~7 pulse as the noise components of the summation of many such pulses tend to cancei while the signal content is additive.
The gain of operational amplifier 16 is set less than unity such that the amplitude of the reEerence signal emerging from recirculating filter 20 is maintained at a constant level.
The detected signal produced by multiplier 22 is a posi-tive going signal of alternating amplitude for an input pulse having a first phase state and a negative going signal input pulse having a second phase state. The output from multiplier 22 is coupled to the input of integrate and dump circuit 24.
Starting at the beginning of the pulse period as marked by a timing pulse from synch circuit 26, integrate and dump circuit 24 produces an output signal which is essentially the integral of the signal on its input. In previous systems the output o-f integrate and dump circuit 24 was sampled directly at a time near the end of the pulse period and a decision was made as to whether the sampled voltage was positive or negative and greater in magnitude than a predetermined threshhold voltage. If the signal voltage from the output of integrate and dump circuit 24 was positive and above a preset threshhold voltage, a digital signal was produced by the sampling circuit which represented a +l state. If the output voltage on the output of integrate and dump circuit 24 was negative and less the preset threshholde voltage, the sampling circuit produced an output signal repre-senting the digital state of -l.
A typical output waveform from integrate and dump circuit 24 is shown in FIG. 3 for the three pulses shown in FIG. 2. All three pulses have essentially the same complex envelope although the phase state of the carrier signal within each pulse may vary.
For the first pulse shown in FIG. 2, there is essentially no .; ~
.
.. . . .
1~`138~)7 intersymbol interference although a tail of the pulse caused by multipath distortion may stretch beyond the predetermined pulse period. The value of the output voltage from integrate and dump circuit 24 increases monotonically from the beginning of the pulse period and exceeds the threshhold level of +VT
before the end of the pulse period. Sample and bit decision circuit 30 makes the determination that the pulse represents a state corresponding to a digital output of +1.
For the second pulse period shown in FIG. 2, the tail end of the -first pulse overlaps the initial portion of the second pulse. Because of the combination of phase states of the overlapping pulses and the point at which the overlapping begins the overlapping portion of the first pulse causes the output of integrate and dump circuit 24 to first swing negative although a digital state of +l is intended by the actual phase state of the second pulse. This is shown by the lighter of the two lines shown for the output of integrate and dump circuit 24 during the second pulse period as it would appear in the absence of inter-symbol interference cancellation. Although the overlapping of the first pulse into the second pulse disappears before the second pulse output from integrate and dump circuit 24 is sampled, the integrated output voltage never reaches the thresh-hold voltage +VT thereby producing an error as no decision can be reached. During the third pulse period, the pulse has a phase characteristic representing a digital -1 such that the contribution caused by the overlapping portion of the second pulse causes the output voltage at the output of integrate and dump circuit 24 to fall at a greater rate than is otherwise required No error is thereby produced although some circuits may be saturated due to the increased voltage magnitude.
, .: : . - . . ~ , : -; . . : . .
.
10~3~80'7 To compensate for the presence of intersymbol interfer-ence, intersymbol interference compensation circuit 10 is added between the output of integrate and dump filter 24 and the input of sample and bit decision circuit 3u to compensate for the undesirable variations iTI the output of integrate and dump circuit 24. In the embodiment of the invention shown in FIG. 1, sample and bit decision circuit 30 continuously samples the output signal produced by summer 28 during the latter portions of each pulse period. An error signal is formed at the output of summer 32 corresponding to the difference between the digital +1 or -1 output from sample and bit decision circuit 30 and the input to that circuit which is the sum of the output of integrate and dump circuit 24 and a correction signal. A11 of the analog signals within the system are approximately normalized between levels of voltage corresponding to the digital signal repre-senting digital states of +l and -1 from an automatic gain control circuit which operates upon signals within the system prior to the IF filter. In the absence of intersymbol interfer-ence, the error signal on the output of summer 32 has an average value of zero because the output voltage from integrate and dump circuit 24 is at approximately the same voltage level as the digital signal representing the +l or -1 bit decision. In the presence of intersymbol interference, the error signal will begin to assume a non-zero level.
The bit decision from the previous pulse is stored within digital storage means for shift register delay 40. Shift register delay 40 may comprise one or more flip-flops. A correlation be-tween the error signal and the previous bit decision is performed by multiplying the error signal by the previous bit at the output of shift register delay 40. The resultant product or correlation ~, ' - ' , :............. '' : . .
. . .
10~ V~
f~lnction is filtered or, equivalently, averaged by low pass filter 36 to obtain at the output thereof an estimate o the error in the output of integrate and dump circuit 24 caused by intersymbol interference.
The output of lol~ pass filter 36 is multiplied by the output of shift register delay 40 thereby producing the correc-tion signal which is coupled back to summer 28. This final multiplication is necessary so that the outpu~ of low pass fil~er 36 is multiplied by either 11 or -1 to give the proper polarity of correction voltage. The output of summer 28 continues to be sampled and further error and correction signals produced until the error signal becomes substantially uncorrelated with the previous bit decison. At that time, a final decision is made as to the proper value of the digital output signal from sample and bit decision 30. A pulse from synch circuit 26 then causes integrate and dump circuit 24 to dump or reset to zero at the end of the pulse period so that the system may then process the next incoming received pulse.
- The action of intersymbol interference compensation circuit 10 is shown diagrammatically in FIGs. 2 and 3. Without the presence of intersymbol interference compensation circuit 10 the output of integrate and dump circuit 24 would appear as shown by the thinner lines during the second and third pulse periods. The correction signal which is formed within intersymbol interference compensation circuit 10 is approximately represented by the area at the end of the first pulse period which is shown as the shaded section in FIG. 2. The greater the overlap between the two pulses the larger will be the shaded section. When the correction signal is added to the output of integrate and dump circuit 24, the - 30 summed output as it appears on the output of summer 28 follows the ; . . . . . .
,`'' :' ' . -: ' , : .
~80~ 7 voltage as illustrated by the heavier of the lines shown during the second and third pulse periods. The presence and application of the correction signal causes the sampled output from summer circuit 28 to exceed in magnit:ude -~V~ during the second pulse period so that an error on the output of the circuit is avo-ided.
During the third pulse period, the correction signal a~so acts to bring the output of summer circuit 28 within expected limits although no error would have been produced. However, an advantage is attained in that the amplitude of the signals emerging from summer circuit 28 are restrained to be within expected limits so that saturation conditions on the input of sample and bit decision circuit 30 and the output of summer circuit 28 are thereby avoided.
An application of the invention within a quarternary phase shift keyed system is shown by the schematic block diagram shown in the view of FIG. 4. A block diagram of a larger portion of the receiver symbol without the use of an intersymbol interference . compensation circuit is shown in FIG. 4 of the referenced patent.
It is to be understood that for purposes of clarity of illustration the system shown herein in FIG. 4 represents anly a portion of the receiver system shown in FIG. 4 of the referenced patent and that in the operative system the remaining portions of the system shown in FIG. 4 of the referenced patent should be provided in each of the two quadrature channels. As in the previously described embodiment of the invention, an intersymbol interference compensation circuit 41 is coupled between the output of integrate and dump circuit 42 and the input of sample and bit decision circuit 60.
An error signal is formed as before on the output of summer 56 representing the difference between the output signal on the output of sample and bit decision circuit 50 representing a digital +l or -1 and the output from summer 44, the input addends of which are ~,.'.; - - , : . : - . .
.. . . .
~08VB~7 the output from integra~e and dump circuit 42 and the correction signal. Shift register delay 58 functions as in the previously described embodiment storing the value of the digital output from the previously processed data bit. The error signal is correlated with the previous bit by multiplier 52, averaged by low pass filter 51, and corrected to the right polarity by multi-plying the averaged output from low pass filter 51 by the previous bit decision on the output of shift register delay 58. The output from multiplier 50 is thus formed identically with the correction signal of the previously described embodiment. However, because of the quadrature channel, a correction or compensation must be made for intersymbol interference caused by data bits or pulses in the quadrature channel. An identical intersymbol interference compensation circuit is coupled between the integrator and sample circuits of the quadrature channel. The output of the shift register delay of the quadrature channel is coupled to one input of each of multipliers 54 and 48. The error signal from summer 56 is coupled to the second input of multiplier 54 and low pass filter 55 identical to low pass filter 51 is coupled between the output of multiplier 54 and the second input o multiplier 48. In this manner a second component of the correction signal is produced at the output of multiplier 48 identical l~ith the production of the component of the correction signal produced on the output of multiplier 50 but in which the output from the shift register delay of the quadrature channel is used as the signal to which the error signal is correlated. The two components of the correction signal are summed by summer 46 to thereby produce the correction signal coupled to summer 44. In general, for systems having more than two possible phase states or having channels in quadrature or predetermined phase relationship to ., . . ~ . ~ . :
.. , . . . . :
.~ . ~. , .~ .
~3B~8V'7 one another, it is required that there be a component of the correction signal in any one channel produced in response to intersymbol interference caused by pulses within the other channels.
The invention can also be used to cancel interference from - more than one previous pulse by correlating the error signal with the stored digital bit decisions from as many previous pulses for which it is desired to cancel the intersymbol inter-ference. For example, if it were desired to cancel interference from two immediately previous pulses, a second shift register delay would be proYided which stores the digital bit decision from the second previous pulse. This may be formed by delaying - the output of the already provided shift register delay circuit by one more bit time with the addition of a second shift regis-ter delay circuit. The error signal is then multiplied by the output from the second shift register, the output of the first multiplier filtered by a low pass filter, and the averaged output from the low pass filter corrected in polarity by multiplying by the same bit decision output. The output from the second multiplier coupled to the shift register delay circuit storing the bit decision from two bits previous is summed with the output of the second multiplier coupled to the shift register delay cir-cuit storing the immediately previous bit decision to form the error correction signal. This structure may be cont~inued for cancellation of intersymbol interference from as many prevlous pulses as is desired and deemed expeditious depending upon the ; exact properties of the communications channels in which the system is used.
This completes the description of the preferred embodiments of the invention. Although preferred embodiments of the invention ~ .
.
.. . .
- .
~8~8~'7 have been described, numerous modlfications and alterations thereto would be apparent to one having ordinary skill in the art without departing from the spirit and scope of the invention.
;~ : ?
:, ,
There has previously been described a communications system for improved reception of signals which lYere transmitted through co~nunications channels having multipath distortion characteristics, Within that system a reference signal is produced in the receiver which has the same complex envelope as that of the received signals over a number of received pulses.
The reference is used in a coherent matched filter-type detector employing decision feedback to permit coherent detection of the signals without the use of channelizing filters for systems employing multiple phase state digital signal modulation. Although the referenced system was capable of operating sYith signals from a plurality of channels, it ~YaS required that there be no ~ -appreciable oYerlap between adjacent pulses within any one channel in order to produce a valid determination of the phase state of pulses within any channel, Intersymbol interference caused by overlapping of adjacent pulses in the previously disclosed system and ln other such communications systems reduced the signal levels within the receiver for some pulses and increased the level for others. For pulses in which the signal .., B ~ ~
, '`A~;
,~` :
~ ~ 8 ~
amplitude was lowered, the amplitude was often insufficient to permit a valid determination of the phase state of that pulse.
Consequently, the system had to be operated with sufficient time spacing between adjacent bits that no overlapping could occur for any possible channel conditions. Hence, the data rate for any one channel was appreciably lowered due to the non-overlapping requirement.
B
,~
. . .
-Accordingl~, it is an object of the pl~esent inyention to provide a communications receiveT system for digital data in which the effects of intersymbol interference are su~stantially decreased.
It is also an objec~ of the preslsnt invention to provide a differ~
entially adaptive communications system which may be operated at a higher data rate than previous s~stems in the prPsence of intersymbol interference~
Moreover, it is an object of the present invention to proYide a differentially adaptive communications system haYing a correction signal producing circuit for correcting recei~ed signals for intersymbol interference.
10These, as well as other objects of the invention, are met by provid-ing a differentially adaptive receiYer which is self~adaptive to multipath distortion having means for compensating for intersymbol interference. With-in the present description of the inYention and accampanying claims, the terms "differentially adaptive receiver" and "receiYer which is self~adaptive to multipath distortion" and similar terms are defined as a recei~er in ac-cordance with the above-described communications system having means for producing a reference signal which has the same complex envelope as that of received signals over a number of received pulses and in which the reference signal is used in a coherent matched filter detector employing decision feedback. The interference compensating means may comprise means for deter-mining the presence of the intersy~bol interference and means for correcting information bearing s~gnals within the receiYer in response to the inter~ ~`
symbol interference dete~mining means. The means for determining the presence of intersy~bol inter~erence mar produce a signal in response to the oYerlap bet~een adjacent syn~ls. The means ~or determining the presence of int0r~
sym~ol interference mc~r also comprise means for comparing the ~alue of a present bit :. . . : :
- ' ' ' ''~ ` ' ~ 8~
decision with the value of the integral of the received signal.
The correcting means may further operate in response to the comparing means to provide a signal for correcting the magnitude of the integrated signal to correspond to the correct bit decision state.
The invention may also be practiced by providing a receiver having means for producing a signal representing the integral of detected received signals wherein the received signals comprise a series or train of pulses each of the pulses being encoded with one of a predetermined number of phase states, means for producing - an output signal which is a dc voltage representative of the dis-crete states of the pulses and having a separate voltage level corresponding to each of the possible states, means for producing an error signal corresponding to the difference between the out-put signal and the integrated received signal, and means for producing a correcting signal in response to the error signal wherein the correcting signal and integrated signal are summed prior to being sampled to produce the output signal. The output signal producing means preferably comprises means for producing one or more samples of the signal representing the integral and means for maintaining or holding the value of the integral of the samples constant over a predetermined time period determined by external synchronization means. The correcting signal pro-ducing means in preferred embodiments includes means for multi-plying the error signal by the output or sampled signal, means for averaging the product produced by the multiplying means, and multiplying means for multiplying the averaged signal produced by the multiplying means by the output signal. The correcting signal is produced so as to have a magnitude which is proportional to the amount of overlap of adjacent ones of the pulses.
,~ ~
: .
~ ~ V ~ 7 The invention also encompasses a combination of means for receiving multipath distorted phase shift keyed signals, and means for producing a reference signal which has substantially the same modulation envelope as the received signals over a short time period and also having a phase state independent of the changes of phase state in the received signals which is preferably equal to a zero phase shift state or a predetermined one of the phase states but invariant as the phase state changes among pulses, means for detecting the phase state of the received signals by comparing the phase state of the received signals with the phase state of the reference signal, means for integrating the detected signal which also includes means for resetting the integrating means to a zero value at the conclusion of a bit time period, means for summing the integrated detected signal with a correction signal so as to produce a corrected detected signal, means for sampling the sum produced by the summing means and for producing an output signal in response to the sampled signal which represents the phase state of the received signals by a dc voltage having a value which corresponds to each of the possible phase states, means for producing a signal representing the dif-ference between the sum produced by the summing means and the output signal, means such as a shift register for storing a signal representing the phase state of the immediately previously produced pulse which may be a binary digit, first multiplying means for multiplying the signal repr$senting the difference by the signal stored in the storing means, means for producing a signal representing the average signal over a pulse time period of the difference or error signal over at least a portion of a pulse period, and second multiplying means for multiplying the signal representing the average by the same stored signal ~' 5 ~8~B~
within the storing means in which the correcting signal is produced as the product generated or produced by the second multiplying means. The correcting signal is produced as the output of the second multiplying means having a magntiude and polarity such as to correct the output of the integrator for error caused by overlap between adjacent pulses. The magnitude and polarity of the correcting signal are in proportion to the amount or total time period multiplied by magnitude of adjacent ones of the pulses. The sampling means preferably samples the sum produced by the summing means a plurality of times during a pulse processing or time period at predetermined intervals until the correction signal is substantially zero at which time the present bit decision is substantially uncorrelated with the previous bit and at which time the error is reduced to the minimum level in the least mean square sense. The phase state of the re-ceived signal may be a binary phase shift key having two predeter-mined values, quarternary phase shift keying having four predeter-mined values, or of any other type of phase shift keying modula-tion.
"~ ~, ~ - ,r-....
, Accorcling to a broad aspect of the present invention, there is provided a differentially adaptive receiver comprising: means for receiving multipath distorted phase shift keyed pulse signals; means for deriving a reference signal having substantially the same envelope as pulses of received signals an(l a phase state independent of changes of phase state in said received signals; means for detecting the phase state of said received signal pulses, said detecting means comprising means for comparing the phase state of said received signals with the phase state of said reference signal; and means for compensating said received signals for intersymbol interference.
~ ccording to another aspect of the present invention, there is provided a receiver comprising in combination: means for producing a signal representing the integral of detected received s~gnals, said received signals comprising a series of pulses, each of said pulses representing a discrete digital state; means for producing an output signal representing the discrete digital states of said received signals; means for producing an error signal representing the difference between said output signal and said signal repre-senting said integral; means for producing a correcting signal in response to said error signal; and means for summing said signal representing the integral and said correcting signal.
According to another aspect of the present invention, there is provided the method comprising the steps of: producing a signal represent-ing the integral of detected received signals, said received signals com-prising a series of pulses, each of said pulses representing a discrete digital state; producing an output signal representing the discrete digital states of said received signals; producing an error signal representing the difference between said output signal and said signal representing said integral of detected received signals; and producing a correcting signal in response to said error signal.
1~8~8~)~
Brief Description of the Drawings FIGURE 1 is a schematic block diagram showing a decision adaptive communication receiver system incorporating the present invention;
FIGURES 2 and 3 are waveorms o signals within the system useful in attaining an understanding of the invention; and FIGURE 4 is a block schematic diagram of a portion of a decision adaptive receiver system employing quarternary phase shift keying in which the present invention is used to advantage.
.
~ 8V ~
Description of the Preferred Embodiments In FIG. 1 is shown a schematic block diagram of an embodi-ment of the invention in a binary phase shift keying receiver system. The system shown in FIG. 1 employs the same basic receiver circuit as the embodiment of the invention shown in FIG. 2 of the referenced patent where like named elements per-form a similar function. The input signal from the IF filter is coupled both to multiplier 22 and to delay circuit 12 which produces a delay of one baud or bit period time. The signal from the IF filter output is compared with a reference signal by multiplication or detection by multiplier 22.
The reference signal is produced in the manner described in the referenced patent. The incoming IF signal is delayed by delay circuit 12 and multiplied by the digital output of the previous bit which may be represented as +l or -1. As the signal output from delay circuit 12 arrives at inverse modulator 14 at the same time as the cGrresponding digital output repre-senting the +l or -1 state, the output of inverse modulator 14 is a signal having the same complex envelope as the incoming signals but with a constant phase state.
The output of inverse modulator 14 is added with the sig-nal circulating in the loop comprising summer 17, delay line 18, and operational amplifier 16. The signal circulating within that loop is made up as a sum of a number of previous inputs from inverse modulator 14 all having substantially the same complex envelope and phase state. Since noise within a single pulse input from inverse modulator 14 is essentially a random phenomenon, the composite reference signal formed from a summa-tion of a number of pulses produced from inverse modulator 14 has a greatly reduced signal-to-noise ratio than a single input . .
: ~ , .. .. ... .
lO~VB~7 pulse as the noise components of the summation of many such pulses tend to cancei while the signal content is additive.
The gain of operational amplifier 16 is set less than unity such that the amplitude of the reEerence signal emerging from recirculating filter 20 is maintained at a constant level.
The detected signal produced by multiplier 22 is a posi-tive going signal of alternating amplitude for an input pulse having a first phase state and a negative going signal input pulse having a second phase state. The output from multiplier 22 is coupled to the input of integrate and dump circuit 24.
Starting at the beginning of the pulse period as marked by a timing pulse from synch circuit 26, integrate and dump circuit 24 produces an output signal which is essentially the integral of the signal on its input. In previous systems the output o-f integrate and dump circuit 24 was sampled directly at a time near the end of the pulse period and a decision was made as to whether the sampled voltage was positive or negative and greater in magnitude than a predetermined threshhold voltage. If the signal voltage from the output of integrate and dump circuit 24 was positive and above a preset threshhold voltage, a digital signal was produced by the sampling circuit which represented a +l state. If the output voltage on the output of integrate and dump circuit 24 was negative and less the preset threshholde voltage, the sampling circuit produced an output signal repre-senting the digital state of -l.
A typical output waveform from integrate and dump circuit 24 is shown in FIG. 3 for the three pulses shown in FIG. 2. All three pulses have essentially the same complex envelope although the phase state of the carrier signal within each pulse may vary.
For the first pulse shown in FIG. 2, there is essentially no .; ~
.
.. . . .
1~`138~)7 intersymbol interference although a tail of the pulse caused by multipath distortion may stretch beyond the predetermined pulse period. The value of the output voltage from integrate and dump circuit 24 increases monotonically from the beginning of the pulse period and exceeds the threshhold level of +VT
before the end of the pulse period. Sample and bit decision circuit 30 makes the determination that the pulse represents a state corresponding to a digital output of +1.
For the second pulse period shown in FIG. 2, the tail end of the -first pulse overlaps the initial portion of the second pulse. Because of the combination of phase states of the overlapping pulses and the point at which the overlapping begins the overlapping portion of the first pulse causes the output of integrate and dump circuit 24 to first swing negative although a digital state of +l is intended by the actual phase state of the second pulse. This is shown by the lighter of the two lines shown for the output of integrate and dump circuit 24 during the second pulse period as it would appear in the absence of inter-symbol interference cancellation. Although the overlapping of the first pulse into the second pulse disappears before the second pulse output from integrate and dump circuit 24 is sampled, the integrated output voltage never reaches the thresh-hold voltage +VT thereby producing an error as no decision can be reached. During the third pulse period, the pulse has a phase characteristic representing a digital -1 such that the contribution caused by the overlapping portion of the second pulse causes the output voltage at the output of integrate and dump circuit 24 to fall at a greater rate than is otherwise required No error is thereby produced although some circuits may be saturated due to the increased voltage magnitude.
, .: : . - . . ~ , : -; . . : . .
.
10~3~80'7 To compensate for the presence of intersymbol interfer-ence, intersymbol interference compensation circuit 10 is added between the output of integrate and dump filter 24 and the input of sample and bit decision circuit 3u to compensate for the undesirable variations iTI the output of integrate and dump circuit 24. In the embodiment of the invention shown in FIG. 1, sample and bit decision circuit 30 continuously samples the output signal produced by summer 28 during the latter portions of each pulse period. An error signal is formed at the output of summer 32 corresponding to the difference between the digital +1 or -1 output from sample and bit decision circuit 30 and the input to that circuit which is the sum of the output of integrate and dump circuit 24 and a correction signal. A11 of the analog signals within the system are approximately normalized between levels of voltage corresponding to the digital signal repre-senting digital states of +l and -1 from an automatic gain control circuit which operates upon signals within the system prior to the IF filter. In the absence of intersymbol interfer-ence, the error signal on the output of summer 32 has an average value of zero because the output voltage from integrate and dump circuit 24 is at approximately the same voltage level as the digital signal representing the +l or -1 bit decision. In the presence of intersymbol interference, the error signal will begin to assume a non-zero level.
The bit decision from the previous pulse is stored within digital storage means for shift register delay 40. Shift register delay 40 may comprise one or more flip-flops. A correlation be-tween the error signal and the previous bit decision is performed by multiplying the error signal by the previous bit at the output of shift register delay 40. The resultant product or correlation ~, ' - ' , :............. '' : . .
. . .
10~ V~
f~lnction is filtered or, equivalently, averaged by low pass filter 36 to obtain at the output thereof an estimate o the error in the output of integrate and dump circuit 24 caused by intersymbol interference.
The output of lol~ pass filter 36 is multiplied by the output of shift register delay 40 thereby producing the correc-tion signal which is coupled back to summer 28. This final multiplication is necessary so that the outpu~ of low pass fil~er 36 is multiplied by either 11 or -1 to give the proper polarity of correction voltage. The output of summer 28 continues to be sampled and further error and correction signals produced until the error signal becomes substantially uncorrelated with the previous bit decison. At that time, a final decision is made as to the proper value of the digital output signal from sample and bit decision 30. A pulse from synch circuit 26 then causes integrate and dump circuit 24 to dump or reset to zero at the end of the pulse period so that the system may then process the next incoming received pulse.
- The action of intersymbol interference compensation circuit 10 is shown diagrammatically in FIGs. 2 and 3. Without the presence of intersymbol interference compensation circuit 10 the output of integrate and dump circuit 24 would appear as shown by the thinner lines during the second and third pulse periods. The correction signal which is formed within intersymbol interference compensation circuit 10 is approximately represented by the area at the end of the first pulse period which is shown as the shaded section in FIG. 2. The greater the overlap between the two pulses the larger will be the shaded section. When the correction signal is added to the output of integrate and dump circuit 24, the - 30 summed output as it appears on the output of summer 28 follows the ; . . . . . .
,`'' :' ' . -: ' , : .
~80~ 7 voltage as illustrated by the heavier of the lines shown during the second and third pulse periods. The presence and application of the correction signal causes the sampled output from summer circuit 28 to exceed in magnit:ude -~V~ during the second pulse period so that an error on the output of the circuit is avo-ided.
During the third pulse period, the correction signal a~so acts to bring the output of summer circuit 28 within expected limits although no error would have been produced. However, an advantage is attained in that the amplitude of the signals emerging from summer circuit 28 are restrained to be within expected limits so that saturation conditions on the input of sample and bit decision circuit 30 and the output of summer circuit 28 are thereby avoided.
An application of the invention within a quarternary phase shift keyed system is shown by the schematic block diagram shown in the view of FIG. 4. A block diagram of a larger portion of the receiver symbol without the use of an intersymbol interference . compensation circuit is shown in FIG. 4 of the referenced patent.
It is to be understood that for purposes of clarity of illustration the system shown herein in FIG. 4 represents anly a portion of the receiver system shown in FIG. 4 of the referenced patent and that in the operative system the remaining portions of the system shown in FIG. 4 of the referenced patent should be provided in each of the two quadrature channels. As in the previously described embodiment of the invention, an intersymbol interference compensation circuit 41 is coupled between the output of integrate and dump circuit 42 and the input of sample and bit decision circuit 60.
An error signal is formed as before on the output of summer 56 representing the difference between the output signal on the output of sample and bit decision circuit 50 representing a digital +l or -1 and the output from summer 44, the input addends of which are ~,.'.; - - , : . : - . .
.. . . .
~08VB~7 the output from integra~e and dump circuit 42 and the correction signal. Shift register delay 58 functions as in the previously described embodiment storing the value of the digital output from the previously processed data bit. The error signal is correlated with the previous bit by multiplier 52, averaged by low pass filter 51, and corrected to the right polarity by multi-plying the averaged output from low pass filter 51 by the previous bit decision on the output of shift register delay 58. The output from multiplier 50 is thus formed identically with the correction signal of the previously described embodiment. However, because of the quadrature channel, a correction or compensation must be made for intersymbol interference caused by data bits or pulses in the quadrature channel. An identical intersymbol interference compensation circuit is coupled between the integrator and sample circuits of the quadrature channel. The output of the shift register delay of the quadrature channel is coupled to one input of each of multipliers 54 and 48. The error signal from summer 56 is coupled to the second input of multiplier 54 and low pass filter 55 identical to low pass filter 51 is coupled between the output of multiplier 54 and the second input o multiplier 48. In this manner a second component of the correction signal is produced at the output of multiplier 48 identical l~ith the production of the component of the correction signal produced on the output of multiplier 50 but in which the output from the shift register delay of the quadrature channel is used as the signal to which the error signal is correlated. The two components of the correction signal are summed by summer 46 to thereby produce the correction signal coupled to summer 44. In general, for systems having more than two possible phase states or having channels in quadrature or predetermined phase relationship to ., . . ~ . ~ . :
.. , . . . . :
.~ . ~. , .~ .
~3B~8V'7 one another, it is required that there be a component of the correction signal in any one channel produced in response to intersymbol interference caused by pulses within the other channels.
The invention can also be used to cancel interference from - more than one previous pulse by correlating the error signal with the stored digital bit decisions from as many previous pulses for which it is desired to cancel the intersymbol inter-ference. For example, if it were desired to cancel interference from two immediately previous pulses, a second shift register delay would be proYided which stores the digital bit decision from the second previous pulse. This may be formed by delaying - the output of the already provided shift register delay circuit by one more bit time with the addition of a second shift regis-ter delay circuit. The error signal is then multiplied by the output from the second shift register, the output of the first multiplier filtered by a low pass filter, and the averaged output from the low pass filter corrected in polarity by multiplying by the same bit decision output. The output from the second multiplier coupled to the shift register delay circuit storing the bit decision from two bits previous is summed with the output of the second multiplier coupled to the shift register delay cir-cuit storing the immediately previous bit decision to form the error correction signal. This structure may be cont~inued for cancellation of intersymbol interference from as many prevlous pulses as is desired and deemed expeditious depending upon the ; exact properties of the communications channels in which the system is used.
This completes the description of the preferred embodiments of the invention. Although preferred embodiments of the invention ~ .
.
.. . .
- .
~8~8~'7 have been described, numerous modlfications and alterations thereto would be apparent to one having ordinary skill in the art without departing from the spirit and scope of the invention.
;~ : ?
:, ,
Claims (21)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A differentially adaptive receiver comprising: means for receiving multipath distorted phase shift keyed pulse signals; means for deriving a reference signal having substantially the same envelope as pulses of received signals and a phase state independent of changes of phase state in said received signals, means for detecting the phase state of said received signal pulses, said detecting means comprising means for comparing the phase state of said received signals with the phase state of said reference signal; and means for compensating said received signals for intersymbol interference.
2. The receiver of claim 1 wherein said intersymbol interference compensating means comprising in combination: means for determining the presence of intersymbol interference; and means for correcting information bearing signals within said receiver in response to said intersymbol inter-ference determining means.
3. The receiver of claim 2 wherein said means for determining the presence of intersymbol interference produces a signal in response to overlap between adjacent symbols.
4. The receiver of claim 2 further comprising: means for producing a signal representing the integral of said information bearing signals; and means for producing a signal representing a present bit decision from said signal representing the integral; and wherein said means for determining the presence of intersymbol interference comprises: means for comparing the value of said present bit decision with the value of said signal represent-ing the integral.
5. The receiver of claim 4 wherein said correcting means comprises:
means for producing a correcting signal for correcting said signal represent-ing the integral in response to the output of said comparing means; and means for summing said signal representing the integral and said correcting signal.
means for producing a correcting signal for correcting said signal represent-ing the integral in response to the output of said comparing means; and means for summing said signal representing the integral and said correcting signal.
6. A receiver comprising in combination: means for producing a signal representing the integral of detected received signals, said received signals comprising a series of pulses, each of said pulses representing a discrete digital state; means for producing an output signal representing the discrete digital states of said received signals; means for producing an error signal representing the difference between said output signal and said signal representing said integral; means for producing a correcting signal in response to said error signal; and means for summing said signal representing the integral and said correcting signal.
7. The combination of claim 6 wherein the sum of said correcting signal and said signal representing said integral form the input to said output signal producing means.
8. The combination of claim 7 wherein said output signal producing means comprising in combination: means for producing one or more samples of said signal representing said integral; and means for storing the value of said samples over a predetermined period of time.
9. The combination of claim 6 wherein said correcting signal producing means comprises: means for storing the output signals from the previous pulses; means for multiplying said error signal by the stored output signal;
means for averaging the product produced by said multiplying means; and means for multiplying the averaged signal produced by said multiplying means by said output signal.
means for averaging the product produced by said multiplying means; and means for multiplying the averaged signal produced by said multiplying means by said output signal.
10. The combination of claim 9 wherein said correcting signal is produced in response to overlapping of adjacent ones of said pulses.
11. In combination: means for receiving multipath distorted phase shift keyed pulse signals; means for deriving a reference signal having substantially the same envelope as the received signal pulses and a phase state independent of changes of phase state in said received signals; means for detecting the phase state of said received signal pulses, said detecting means comprising means for comparing the phase state of said received signals with the phase state of said reference signal; means for integrating the detected signal; means for summing the integrated detected signal with a correcting signal; means for sampling the sum produced by said summing means;
means for producing an output signal in response to the sampled sum; means for producing a signal representing the difference between said sum produced by said summing means and said output signal; means for storing a signal representing the phase state of the immediately previously received pulse signal; first multiplying means for multiplying said signal representing said difference by said signal stored in said storing means; means for producing a signal representing the average of the output of said first multiplying means over at least a portion of a pulse period; second multiply-ing means for multiplying said signal representing said average by said signal stored in said storing means, said correcting signal being produced as by the product produced by said second multiplying means.
means for producing an output signal in response to the sampled sum; means for producing a signal representing the difference between said sum produced by said summing means and said output signal; means for storing a signal representing the phase state of the immediately previously received pulse signal; first multiplying means for multiplying said signal representing said difference by said signal stored in said storing means; means for producing a signal representing the average of the output of said first multiplying means over at least a portion of a pulse period; second multiply-ing means for multiplying said signal representing said average by said signal stored in said storing means, said correcting signal being produced as by the product produced by said second multiplying means.
12. The combination of claim 11 wherein said sampling means samples said sum produced by said summing means a plurality of times during a pulse processing time at predetermined intervals until said correcting signal is substantially zero.
13. The combination of claim 12 wherein said phase state of said received signals may be of two predetermined values.
14. The combination of claim 13 wherein said phase state of said received signals may be of four or more predetermined values.
15. In combination: means for receiving multipath distorted phase shift keyed signals upon a plurality of channels; means for deriving a reference signal for each of said channels having substantially the same complex envelope as the signals received in that channel; means for compar-ing the received signals in each channel with the reference signal of that channel; means for producing a detected signal in each of said channels as a result of said comparing means; means for producing the integral of the output signal from said detecting means in each of said channels; means for sampling the output of each of said integrating means in each of said channels; means for producing an output signal in each of said channels representing the amplitude of the sampled signal in each of said channels;
and means for producing a correcting signal in each of said channels in response to the output of each channel representing the amount of overlay between adjacent signals within that channel and between signals in that channel and other ones of said channel.
and means for producing a correcting signal in each of said channels in response to the output of each channel representing the amount of overlay between adjacent signals within that channel and between signals in that channel and other ones of said channel.
16. The combination of claim 15 wherein said correcting signal pro-ducing means comprising in combination: means for producing an error signal in each of said channels as the difference between said output signal and the sum of said output from said integrating means and said correcting signal; means in each of said channels for storing the value of said output signal from the pulse processed immediately previous to the pulse then being processed in that channel; first multiplying means in each channel for multiplying said error signal by the stored values for each of said channels;
means for averaging the product of said error signal and said stored value for each product formed within each channel of said error signal within said channel; means for multiplying the averaged signal within each channel by said stored value in each channel; and means for forming the sum of the products in each of said channels of all of said products produced by said second multiplying means in each of said channels, said correcting signal in each channel being produced as said sum of said products of said second multiplying means.
means for averaging the product of said error signal and said stored value for each product formed within each channel of said error signal within said channel; means for multiplying the averaged signal within each channel by said stored value in each channel; and means for forming the sum of the products in each of said channels of all of said products produced by said second multiplying means in each of said channels, said correcting signal in each channel being produced as said sum of said products of said second multiplying means.
17. The method comprising the steps of: producing a signal represent-ing the integral of detected received signals, said received signals com-prising a series of pulses, each of said pulses representing a discrete digital state; producing an output signal representing the discrete digital states of said received signals; producing an error signal representing the difference between said output signal and said signal representing said integral of detected received signals; and producing a correcting signal in response to said error signal.
18. The method of claim 17 wherein the sum of said correcting signal and said signal representing said integral form the input of said output signal producing means.
19. The method of claim 18 wherein said step of producing said output signal comprises: producing one or more samples of said signal representing said integral; and storing the value of said samples over a predetermined period of time.
20. The method of claim 17 wherein said step of producing said correcting signal comprises: storing the output signal from the previous pulses; multiplying said error signal by the stored output signal; averaging the product of said error signal and said stored output signal; and multiply-ing the averaged signal by said stored output signal.
21. The method of claim 20 wherein said correcting signal is produced in response to overlapping of adjacent ones of said pulses.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/647,261 US4032847A (en) | 1976-01-05 | 1976-01-05 | Distortion adapter receiver having intersymbol interference correction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1080807A true CA1080807A (en) | 1980-07-01 |
Family
ID=24596274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA267,422A Expired CA1080807A (en) | 1976-01-05 | 1976-12-08 | Distortion adapter receiver having intersymbol interference correction |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US4032847A (en) |
| JP (1) | JPS5287308A (en) |
| BE (1) | BE849930A (en) |
| CA (1) | CA1080807A (en) |
| DE (1) | DE2700354C2 (en) |
| DK (1) | DK1577A (en) |
| FR (1) | FR2337469A1 (en) |
| GB (1) | GB1535445A (en) |
| IT (1) | IT1073789B (en) |
| NL (1) | NL7614433A (en) |
Families Citing this family (56)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2375773A1 (en) * | 1976-12-23 | 1978-07-21 | Ibm France | ADAPTIVE PHASE DETECTION METHOD AND DEVICE |
| DE2727874C3 (en) * | 1976-06-25 | 1979-07-12 | Cselt-Centro Studi E Laboratori Telecomunicazioni S.P.A., Turin (Italien) | Method and equalizer for the non-linear equalization of digital signals |
| US4186349A (en) * | 1977-12-27 | 1980-01-29 | E-Systems, Inc. | Adaptive narrow band noise estimator/suppressor radio receiver |
| JPS5829012B2 (en) * | 1978-05-16 | 1983-06-20 | ケイディディ株式会社 | Echo control method |
| US4383324A (en) * | 1979-11-16 | 1983-05-10 | The General Electric Company Limited | Digital data transmission systems |
| DE2950339C2 (en) * | 1979-12-14 | 1984-06-07 | ANT Nachrichtentechnik GmbH, 7150 Backnang | Method and arrangement for digital control of the carrier phase in receivers of data transmission systems |
| US4503545A (en) * | 1980-02-19 | 1985-03-05 | Paradyne Corporation | System for evaluating transmission line impairments |
| US4349916A (en) * | 1980-08-06 | 1982-09-14 | The United States Of America As Represented By The Secretary Of The Air Force | Adaptive interference tracker for suppression of narrow band interference |
| US4692931A (en) * | 1984-10-31 | 1987-09-08 | Nec Corporation | Synchronization circuit capable of establishing synchronism even when a sampling rate is invariable |
| US4689805A (en) * | 1986-04-29 | 1987-08-25 | Oy Nokia Ab | Method of and a device for correcting signal distortion caused by a cable |
| US4803701A (en) * | 1987-06-25 | 1989-02-07 | The United States Of America As Represented By The Secretary Of The Air Force | Digital detection circuit |
| US4953186A (en) * | 1988-02-19 | 1990-08-28 | Silicon Systems, Inc. | Phase jitter tracker |
| US5086340A (en) * | 1990-10-19 | 1992-02-04 | Zenith Electronics Corporation | Co-channel interference reduction system for digital high definition television |
| US5132797A (en) * | 1990-10-19 | 1992-07-21 | Zenith Electronics Corporation | Co-channel interference filter for digital high definition television receiver |
| US5353301A (en) * | 1993-09-17 | 1994-10-04 | Motorola, Inc. | Method and apparatus for combining multipath spread-spectrum signals |
| US7515896B1 (en) | 1998-10-21 | 2009-04-07 | Parkervision, Inc. | Method and system for down-converting an electromagnetic signal, and transforms for same, and aperture relationships |
| US6694128B1 (en) | 1998-08-18 | 2004-02-17 | Parkervision, Inc. | Frequency synthesizer using universal frequency translation technology |
| US6061551A (en) | 1998-10-21 | 2000-05-09 | Parkervision, Inc. | Method and system for down-converting electromagnetic signals |
| US6061555A (en) | 1998-10-21 | 2000-05-09 | Parkervision, Inc. | Method and system for ensuring reception of a communications signal |
| US7027786B1 (en) | 1998-10-21 | 2006-04-11 | Parkervision, Inc. | Carrier and clock recovery using universal frequency translation |
| US6542722B1 (en) | 1998-10-21 | 2003-04-01 | Parkervision, Inc. | Method and system for frequency up-conversion with variety of transmitter configurations |
| US6813485B2 (en) | 1998-10-21 | 2004-11-02 | Parkervision, Inc. | Method and system for down-converting and up-converting an electromagnetic signal, and transforms for same |
| US7039372B1 (en) | 1998-10-21 | 2006-05-02 | Parkervision, Inc. | Method and system for frequency up-conversion with modulation embodiments |
| US7236754B2 (en) | 1999-08-23 | 2007-06-26 | Parkervision, Inc. | Method and system for frequency up-conversion |
| US6049706A (en) | 1998-10-21 | 2000-04-11 | Parkervision, Inc. | Integrated frequency translation and selectivity |
| US6560301B1 (en) | 1998-10-21 | 2003-05-06 | Parkervision, Inc. | Integrated frequency translation and selectivity with a variety of filter embodiments |
| US7295826B1 (en) | 1998-10-21 | 2007-11-13 | Parkervision, Inc. | Integrated frequency translation and selectivity with gain control functionality, and applications thereof |
| US6370371B1 (en) | 1998-10-21 | 2002-04-09 | Parkervision, Inc. | Applications of universal frequency translation |
| US6704549B1 (en) | 1999-03-03 | 2004-03-09 | Parkvision, Inc. | Multi-mode, multi-band communication system |
| US6704558B1 (en) | 1999-01-22 | 2004-03-09 | Parkervision, Inc. | Image-reject down-converter and embodiments thereof, such as the family radio service |
| US7006805B1 (en) | 1999-01-22 | 2006-02-28 | Parker Vision, Inc. | Aliasing communication system with multi-mode and multi-band functionality and embodiments thereof, such as the family radio service |
| US6853690B1 (en) | 1999-04-16 | 2005-02-08 | Parkervision, Inc. | Method, system and apparatus for balanced frequency up-conversion of a baseband signal and 4-phase receiver and transceiver embodiments |
| US6879817B1 (en) | 1999-04-16 | 2005-04-12 | Parkervision, Inc. | DC offset, re-radiation, and I/Q solutions using universal frequency translation technology |
| US6873836B1 (en) | 1999-03-03 | 2005-03-29 | Parkervision, Inc. | Universal platform module and methods and apparatuses relating thereto enabled by universal frequency translation technology |
| US7110435B1 (en) | 1999-03-15 | 2006-09-19 | Parkervision, Inc. | Spread spectrum applications of universal frequency translation |
| US7065162B1 (en) | 1999-04-16 | 2006-06-20 | Parkervision, Inc. | Method and system for down-converting an electromagnetic signal, and transforms for same |
| US7693230B2 (en) | 1999-04-16 | 2010-04-06 | Parkervision, Inc. | Apparatus and method of differential IQ frequency up-conversion |
| US7110444B1 (en) | 1999-08-04 | 2006-09-19 | Parkervision, Inc. | Wireless local area network (WLAN) using universal frequency translation technology including multi-phase embodiments and circuit implementations |
| US8295406B1 (en) | 1999-08-04 | 2012-10-23 | Parkervision, Inc. | Universal platform module for a plurality of communication protocols |
| US7072390B1 (en) | 1999-08-04 | 2006-07-04 | Parkervision, Inc. | Wireless local area network (WLAN) using universal frequency translation technology including multi-phase embodiments |
| US7054296B1 (en) | 1999-08-04 | 2006-05-30 | Parkervision, Inc. | Wireless local area network (WLAN) technology and applications including techniques of universal frequency translation |
| US7082171B1 (en) | 1999-11-24 | 2006-07-25 | Parkervision, Inc. | Phase shifting applications of universal frequency translation |
| US6963734B2 (en) | 1999-12-22 | 2005-11-08 | Parkervision, Inc. | Differential frequency down-conversion using techniques of universal frequency translation technology |
| US7292835B2 (en) | 2000-01-28 | 2007-11-06 | Parkervision, Inc. | Wireless and wired cable modem applications of universal frequency translation technology |
| US7010286B2 (en) | 2000-04-14 | 2006-03-07 | Parkervision, Inc. | Apparatus, system, and method for down-converting and up-converting electromagnetic signals |
| US7554508B2 (en) | 2000-06-09 | 2009-06-30 | Parker Vision, Inc. | Phased array antenna applications on universal frequency translation |
| US7010559B2 (en) | 2000-11-14 | 2006-03-07 | Parkervision, Inc. | Method and apparatus for a parallel correlator and applications thereof |
| US7454453B2 (en) | 2000-11-14 | 2008-11-18 | Parkervision, Inc. | Methods, systems, and computer program products for parallel correlation and applications thereof |
| US7577192B2 (en) | 2001-03-29 | 2009-08-18 | Applied Wave Research, Inc. | Method and apparatus for characterizing the distortion produced by electronic equipment |
| US7085335B2 (en) | 2001-11-09 | 2006-08-01 | Parkervision, Inc. | Method and apparatus for reducing DC offsets in a communication system |
| US7072427B2 (en) | 2001-11-09 | 2006-07-04 | Parkervision, Inc. | Method and apparatus for reducing DC offsets in a communication system |
| US6975848B2 (en) | 2002-06-04 | 2005-12-13 | Parkervision, Inc. | Method and apparatus for DC offset removal in a radio frequency communication channel |
| US7321640B2 (en) | 2002-06-07 | 2008-01-22 | Parkervision, Inc. | Active polyphase inverter filter for quadrature signal generation |
| US7379883B2 (en) | 2002-07-18 | 2008-05-27 | Parkervision, Inc. | Networking methods and systems |
| US7460584B2 (en) | 2002-07-18 | 2008-12-02 | Parkervision, Inc. | Networking methods and systems |
| JP7004503B2 (en) * | 2017-01-27 | 2022-01-21 | ラピスセミコンダクタ株式会社 | Automatic gain control circuit (AGC), despreading circuit and method of reproducing received data |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3605018A (en) * | 1968-09-13 | 1971-09-14 | Sylvania Electric Prod | Interference suppression in a receiver by envelope variation modulation |
| US3633107A (en) * | 1970-06-04 | 1972-01-04 | Bell Telephone Labor Inc | Adaptive signal processor for diversity radio receivers |
| JPS5717361B2 (en) * | 1971-10-08 | 1982-04-10 | ||
| US3794921A (en) * | 1971-11-24 | 1974-02-26 | Raytheon Co | Differentially adaptive communication system |
| FR2216715B1 (en) * | 1973-01-31 | 1976-06-11 | Ibm France | |
| US3879664A (en) * | 1973-05-07 | 1975-04-22 | Signatron | High speed digital communication receiver |
| DE2416058B2 (en) * | 1973-07-12 | 1980-12-18 | International Business Machines Corp., Armonk, N.Y. (V.St.A.) | Method and circuit arrangements for equalizing a quadrature-modulated data signal |
-
1976
- 1976-01-05 US US05/647,261 patent/US4032847A/en not_active Expired - Lifetime
- 1976-12-08 CA CA267,422A patent/CA1080807A/en not_active Expired
- 1976-12-20 GB GB53026/76A patent/GB1535445A/en not_active Expired
- 1976-12-24 JP JP15610376A patent/JPS5287308A/en active Pending
- 1976-12-24 FR FR7639071A patent/FR2337469A1/en active Granted
- 1976-12-27 NL NL7614433A patent/NL7614433A/en not_active Application Discontinuation
- 1976-12-28 BE BE173702A patent/BE849930A/en not_active IP Right Cessation
- 1976-12-30 IT IT52848/76A patent/IT1073789B/en active
-
1977
- 1977-01-04 DK DK1577A patent/DK1577A/en unknown
- 1977-01-05 DE DE2700354A patent/DE2700354C2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| IT1073789B (en) | 1985-04-17 |
| FR2337469A1 (en) | 1977-07-29 |
| JPS5287308A (en) | 1977-07-21 |
| BE849930A (en) | 1977-04-15 |
| DK1577A (en) | 1977-07-06 |
| FR2337469B1 (en) | 1982-10-01 |
| NL7614433A (en) | 1977-07-07 |
| GB1535445A (en) | 1978-12-13 |
| DE2700354C2 (en) | 1985-03-21 |
| DE2700354A1 (en) | 1977-07-14 |
| US4032847A (en) | 1977-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1080807A (en) | Distortion adapter receiver having intersymbol interference correction | |
| US3879664A (en) | High speed digital communication receiver | |
| US4567599A (en) | Automatic adaptive equalizer having improved reset function | |
| US4870370A (en) | Method and apparatus for two stage automatic gain control | |
| US4835790A (en) | Carrier-to-noise detector for digital transmission systems | |
| US8238494B2 (en) | Apparatus and method for RF packet detection and symbol timing recovery | |
| US4736455A (en) | Interference cancellation system | |
| CA1338153C (en) | Interference canceller | |
| US5566214A (en) | Automatic noise normalization and reacquisition control for a QPSK demodulator symbol tracking loop | |
| US4271525A (en) | Adaptive diversity receiver for digital communications | |
| US5195106A (en) | Method for channel adaptive detecting/equalize | |
| US20010043658A1 (en) | Erasure based instantaneous loop control in a data receiver | |
| US4262360A (en) | Method and device for detecting a pseudo-random sequence of carrier phase changes of 0° and 180° in a data receiver | |
| EP0482927B1 (en) | Digital radio receiver | |
| US5434889A (en) | Receiver comprising an arrangement for estimating a frequency deviation | |
| US4458355A (en) | Adaptive phase lock loop | |
| CA2229182A1 (en) | Transmission/reception unit with bidirectional equalization | |
| US4475211A (en) | Digitally controlled transversal equalizer | |
| US5511097A (en) | Delay detection circuit | |
| US4945312A (en) | Method and device for the demodulation of signals with constant envelope and continuous phase angle modulation by a train of binary symbols tolerating frequency drifts | |
| US4071829A (en) | Coherent phase detector using a frequency discriminator | |
| JPH04259125A (en) | Automatic equalizer | |
| KR100323788B1 (en) | Loop Filters and Phase Synchronous Loops | |
| US6032029A (en) | Receiver selecting either a first demodulated signal or a second demodulated signal in accordance with characteristics of a received signal | |
| EP0517533B1 (en) | Demodulator for digital modulation signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |